Changes

Summary

[AArch64][GlobalISel] Implement widenScalar for signed overflow (details)
[TargetLowering] Simplify some code in SimplifySetCC that tries to handle SIGN_EXTEND_INREG operand types that should never happen. NFCI (details)
[AMDGPU] Test clean up (NFC) (details)
Update filename to workers.py file in documentation (details)
NFC: Remove simple_ilist comment mentioning ilist/iplist allocating (details)
[TargetLowering] Use getBoolConstant instead of assuming zero or one for boolean contents. (details)
[clang][cli] Port visibility LangOptions to marshalling system (details)
[RISCV] Fix intrinsic CodeGen test cases for vrgather (details)

Commit 541d98efa222b00e16c67348810898c2fa11f398 by Amara Emerson [AArch64][GlobalISel] Implement widenScalar for signed overflow Implement widening for G_SADDO and G_SSUBO. Previously it was only implemented for G_UADDO and G_USUBO. Also add legalize-add/sub tests for narrow overflowing add/sub on AArch64. Differential Revision: https://reviews.llvm.org/D95034
	llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
	llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
	llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
Commit 5660dc5968ec6dacba1917b741d660c582f69e9e by craig.topper [TargetLowering] Simplify some code in SimplifySetCC that tries to handle SIGN_EXTEND_INREG operand types that should never happen. NFCI There was code to handle the first operand being different than the result type. And code to handle first operand having the same type as the type to extend from. This should never happen for a correctly formed SIGN_EXTEND_INREG. I've replace the code with asserts. I also noticed we created the same APInt twice so I've reused it.
	llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit c971bcd2102b905e6469463fb8309ab3f7b2b8f2 by Christudasan.Devadasan [AMDGPU] Test clean up (NFC)
	llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
Commit f20bb857addaf5479d9b1d4ac29e315a3971ff1c by douglas.yung Update filename to workers.py file in documentation Commit be9f322e8dc530a56f03356aad31fa9031b27e26 moved the list of workers from slaves.py to workers.py, but the documentation in "How To Add A Builder" was never updated and now references a non-existing file. This fixes that. Reviewed By: gkistanova Differential Revision: https://reviews.llvm.org/D94886
	llvm/docs/HowToAddABuilder.rst
Commit 75f10c957477b269d9b954a686231342aeb8004b by nathan NFC: Remove simple_ilist comment mentioning ilist/iplist allocating Allocation was removed from ilist in 2016 in the git commit b5da00533510. Reviewed By: dexonsmith Differential Revision: https://reviews.llvm.org/D93953
	llvm/include/llvm/ADT/simple_ilist.h
Commit c953a8334707951d172e8061c8dc9054eb0c5c3f by craig.topper [TargetLowering] Use getBoolConstant instead of assuming zero or one for boolean contents. Noticed while I was touching other nearby code. I don't have a test where this matters because the targets I work on use zero or one boolean contents. And the tests cases I've seen this fire on happen before type legalization where the result type is MVT::i1 so the distinction doesn't matter.
	llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit ff5f42e413386b1b3730879abf7b35756891e1c3 by Jan Svoboda [clang][cli] Port visibility LangOptions to marshalling system This patch introduces Clang-specific MarshallingInfoVisibility TableGen class. Reviewed By: dexonsmith Differential Revision: https://reviews.llvm.org/D95147
	clang/include/clang/Driver/Options.td
	clang/lib/Frontend/CompilerInvocation.cpp
Commit 4edb63bbbe338b890119a307bc323c24d0a1afc7 by shihpo.hung [RISCV] Fix intrinsic CodeGen test cases for vrgather 1. Op2 type in vrgather.vx should be XLEN instead of SEW 2. Add double type in vrgather-rv32 cases. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D95207
	llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
	llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll