1. Mark output as text if it is really text (details)
  2. [VPlan] Make VPRecipeBase inherit from VPUser directly (NFC). (details)
  3. [mlir] Use target-specific GPU kernel attributes in lowering pipelines (details)
  4. [Vectorizers][TTI] remove option to bypass creation of vector reduction intrinsics (details)
  5. [SVE][LoopVectorize] Support for vectorization of loops with function calls (details)
  6. [mlir][spirv] Lower sexti -> SConvert (details)
  7. [ARM] Single source VMOVNT (details)
  8. [clangd] Remove the cross-file-rename option. (details)
  9. [mlir][Linalg] Improve region support in Linalg ops. (details)
  10. [clangd] Move command handlers into a map in ClangdLSPServer. NFC (details)
  11. [TableGen][GlobalISel] Allow duplicate RendererFns (details)
  12. [analyzer][Liveness][NFC] Remove an unneeded pass to collect variables that appear in an assignment (details)
  13. Improve hover scopes for Objective-C code (details)
Commit fdb640ea30d416368b76b68b106deda580c6aced by Abhina.Sreeskantharajan
Mark output as text if it is really text

This is a continuation of The following places need to set the OF_Text flag correctly.

Reviewed By: JDevlieghere

Differential Revision:
The file was modifiedclang/lib/Driver/Driver.cpp
The file was modifiedclang/lib/Frontend/Rewrite/FrontendActions.cpp
The file was modifiedllvm/tools/dsymutil/DwarfLinkerForBinary.cpp
Commit 85fe5c93456776f313e25efaf49d3ae9e8703c86 by flo
[VPlan] Make VPRecipeBase inherit from VPUser directly (NFC).

The individual recipes have been updated to manage their operands using
VPUser a while back. Now that the transition is done, we can instead
make VPRecipeBase a VPUser and get rid of the toVPUser helper.
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Commit 4c4876c314577e253a198ca3868b26fd35ec8a6e by zinenko
[mlir] Use target-specific GPU kernel attributes in lowering pipelines

Until now, the GPU translation to NVVM or ROCDL intrinsics relied on the
presence of the generic `gpu.kernel` attribute to attach additional LLVM IR
metadata to the relevant functions. This would be problematic if each dialect
were to handle the conversion of its own options, which is the intended
direction for the translation infrastructure. Introduce `nvvm.kernel` and
`rocdl.kernel` in addition to `gpu.kernel` and base translation on these new
attributes instead.

Reviewed By: herhut

Differential Revision:
The file was modifiedmlir/test/Target/rocdl.mlir
The file was modifiedmlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
The file was addedmlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/
The file was modifiedmlir/lib/Conversion/GPUCommon/GPUOpsLowering.h
The file was modifiedmlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
The file was modifiedmlir/lib/Conversion/GPUToNVVM/CMakeLists.txt
The file was modifiedmlir/lib/Conversion/GPUToROCDL/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/
The file was modifiedmlir/lib/Target/LLVMIR/ConvertToNVVMIR.cpp
The file was modifiedmlir/test/Target/nvvmir.mlir
The file was modifiedmlir/lib/Conversion/GPUCommon/CMakeLists.txt
The file was modifiedmlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
The file was modifiedmlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
The file was modifiedmlir/lib/Target/LLVMIR/ConvertToROCDLIR.cpp
Commit 79b1b4a5815127badaf4939773b47e280f57835d by spatel
[Vectorizers][TTI] remove option to bypass creation of vector reduction intrinsics

The vector reduction intrinsics started life as experimental ops, so backend support
was lacking. As part of promoting them to 1st-class intrinsics, however, codegen
support was added/improved:

So I think it is safe to now remove this complication from IR.

Note that we still have an IR-level codegen expansion pass for these as discussed
in D95690. Removing that is another step in simplifying the logic. Also note that
x86 was already unconditionally forming reductions in IR, so there should be no
difference for x86.

I spot checked a couple of the tests here by running them through opt+llc and did
not see any asm diffs.

If we do find functional differences for other targets, it should be possible
to (at least temporarily) restore the shuffle IR with the ExpandReductions IR

Differential Revision:
The file was modifiedllvm/test/Transforms/LoopVectorize/reduction.ll
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.h
The file was modifiedllvm/test/Transforms/LoopVectorize/induction.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/loop-form.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
The file was modifiedllvm/test/Transforms/LoopVectorize/debugloc.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
The file was modifiedllvm/lib/Transforms/Utils/LoopUtils.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/fix-reduction-dbg.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/minmax_reduction.ll
The file was modifiedllvm/lib/Analysis/TargetTransformInfo.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/reduction-predselect.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/reduction-inloop.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/if-reduction.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h
The file was modifiedllvm/test/Transforms/LoopVectorize/float-minmax-instruction-flag.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/select-reduction.ll
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/sphinx.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/flags.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.h
The file was modifiedllvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-vfabi-attr.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
Commit fea06efe7c92b4069f63bbba46a8079678de3d9c by kerry.mclaughlin
[SVE][LoopVectorize] Support for vectorization of loops with function calls

Changes `getScalarizationOverhead` to return an invalid cost for scalable VFs
and adds some simple tests for loops containing a function for which
there is a vectorized variant available.

Reviewed By: david-arm

Differential Revision:
The file was modifiedllvm/lib/Analysis/TargetTransformInfo.cpp
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 530d6ea97b884656d59e4701b40d9e6d546b4bef by benny.kra
[mlir][spirv] Lower sexti -> SConvert
The file was modifiedmlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.cpp
Commit 541828e35da28f8bae0fad58ba86ac0cc3a0f898 by
[ARM] Single source VMOVNT

Our current lowering of VMOVNT goes via a shuffle vector of the form
<0, N, 2, N+2, 4, N+4, ..>. That can of course also be a single input
shuffle of the form <0, 0, 2, 2, 4, 4, ..>, where we use a VMOVNT to
insert a vector into the top lanes of itself. This adds lowering of that
case, re-using the existing isVMOVNMask.

Differential Revision:
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vmovn.ll
Commit ee4dd0f87698330a8d86ed268d69c4fe9be49e6f by hokein.wu
[clangd] Remove the cross-file-rename option.

and simplify the code.

Differential Revision:
The file was modifiedclang-tools-extra/clangd/refactor/Rename.h
The file was modifiedclang-tools-extra/clangd/unittests/RenameTests.cpp
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
The file was modifiedclang-tools-extra/clangd/refactor/Rename.cpp
Commit 973e133b769773c89ce4b8bbfd6c77612d2ff9d4 by nicolas.vasilache
[mlir][Linalg] Improve region support in Linalg ops.

This revision takes advantage of the newly extended `ref` directive in assembly format
to allow better region handling for LinalgOps. Specifically, FillOp and CopyOp now build their regions explicitly which allows retiring older behavior that relied on specific op knowledge in both lowering to loops and vectorization.

Differential Revision:
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Loops.cpp
The file was modifiedmlir/test/mlir-linalg-ods-gen/
The file was modifiedmlir/lib/Conversion/LinalgToStandard/LinalgToStandard.cpp
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
The file was modifiedmlir/test/Transforms/copy-removal.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/
The file was modifiedmlir/lib/Dialect/Linalg/EDSC/Builders.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Generalization.cpp
The file was modifiedmlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
Commit cea9f054327be2eb83093f0202a7814b904f1076 by sam.mccall
[clangd] Move command handlers into a map in ClangdLSPServer. NFC

Differential Revision:
The file was modifiedclang-tools-extra/clangd/Protocol.h
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.cpp
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.h
The file was modifiedclang-tools-extra/clangd/Protocol.cpp
Commit 7e9ceed9a2e1c040de5216a56d0aec55a9b93680 by jay.foad
[TableGen][GlobalISel] Allow duplicate RendererFns

Allow different GICustomOperandRenderers to use the same RendererFn.
This avoids the need for targets to define a bunch of identical C++
renderer functions with different names.

Without this fix TableGen would have emitted code that tried to define
the GICR enumeration with duplicate enumerators.

Differential Revision:
The file was modifiedllvm/lib/Target/AMDGPU/
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/test/TableGen/
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
Commit 33e731e62dae49d5143410248234963fc7a5e1db by dkszelethus
[analyzer][Liveness][NFC] Remove an unneeded pass to collect variables that appear in an assignment

Suppose you stumble across a DeclRefExpr in the AST, that references a VarDecl.
How would you know that that variable is written in the containing statement, or
not? One trick would be to ascend the AST through Stmt::getParent, and see
whether the variable appears on the left hand side of the assignment.

Liveness does something similar, but instead of ascending the AST, it descends
into it with a StmtVisitor, and after finding an assignment, it notes that the
LHS appears in the context of an assignemnt. However, as [1] demonstrates, the
analysis isn't ran on the AST of an entire function, but rather on CFG, where
the order of the statements, visited in order, would make it impossible to know
this information by descending.

void f() {
  int i;

  i = 5;

`-FunctionDecl 0x55a6e1b070b8 <test.cpp:1:1, line:5:1> line:1:6 f 'void ()'
  `-CompoundStmt 0x55a6e1b07298 <col:10, line:5:1>
    |-DeclStmt 0x55a6e1b07220 <line:2:3, col:8>
    | `-VarDecl 0x55a6e1b071b8 <col:3, col:7> col:7 used i 'int'
    `-BinaryOperator 0x55a6e1b07278 <line:4:3, col:7> 'int' lvalue '='
      |-DeclRefExpr 0x55a6e1b07238 <col:3> 'int' lvalue Var 0x55a6e1b071b8 'i' 'int'
      `-IntegerLiteral 0x55a6e1b07258 <col:7> 'int' 5

void f()
[B2 (ENTRY)]
   Succs (1): B1

   1: int i;
   2: 5
   3: i
   4: [B1.3] = [B1.2]
   Preds (1): B2
   Succs (1): B0

[B0 (EXIT)]
   Preds (1): B1

You can see that the arguments (rightfully so, they need to be evaluated first)
precede the assignment operator. For this reason, Liveness implemented a pass to
scan the CFG and note which variables appear in an assignment.


This problem only exists if we traverse a CFGBlock in order. And Liveness in
fact does it reverse order. So a distinct pass is indeed unnecessary, we can
note the appearance of the assignment by the time we reach the variable.


Differential Revision:
The file was modifiedclang/include/clang/Analysis/CFG.h
The file was modifiedclang/lib/Analysis/LiveVariables.cpp
Commit 07c5a800dc1769f3f684d4a864f3903ac9ffa9f3 by davg
Improve hover scopes for Objective-C code

- Instead of `AppDelegate::application:didFinishLaunchingWithOptions:` you
will now see `-[AppDelegate application:didFinishLaunchingWithOptions:]`

- Also include categories in the name when printing the scopes, e.g. `Class(Category)` and `-[Class(Category) method]`

Differential Revision:
The file was modifiedclang-tools-extra/clangd/AST.h
The file was modifiedclang-tools-extra/clangd/Hover.cpp
The file was modifiedclang-tools-extra/clangd/AST.cpp
The file was modifiedclang-tools-extra/clangd/unittests/HoverTests.cpp