1. [ARM] Extend search for increment in load/store optimizer (details)
  2. [analyzer][NFC] Fix test failures for builds w/o assertions (details)
  3. [CodeGen][SelectionDAG]Add new intrinsic  experimental.vector.reverse (details)
  4. [mlir] Use the interface-based translation for LLVM "intrinsic" dialects (details)
  5. Fix MSVC natvis visualisation of llvm::FixedVectorTyID and ScalableVectorTyID (details)
  6. [LoopVectorizer] Require no-signed-zeros-fp-math=true for fmin/fmax (details)
  7. [llvm] NFC: Cleanup llvm-yaml-numeric-parser-fuzzer (details)
  8. [llvm-nm] Tidy up error messages (details)
  9. [llvm-nm][test] Add additional test coverage for llvm-nm options (details)
  10. [mlir] use new cmake targets in mlir-*-runner (details)
  11. [X86] Add SSE2+SSE3 common check prefix to psubus tests (details)
  12. [debuginfo-tests] Remove explicit checks for Python 3 (details)
  13. [debuginfo-tests] Remove some unused config variables (details)
  14. [CostModel]Add cost model for experimental.vector.reverse (details)
  15. [debuginfo-tests] Delete unused/duplicate imports (details)
  16. Make shape.is_broadcastable/shape.cstr_broadcastable nary (details)
  17. [ARM] Add some basic Min/Max costs (details)
  18. [LangRef] Increase size of title underline for experimental.vector.reverse (details)
  19. [AArch64] Move machine bundle unpacking to PreEmit2 phase. (details)
Commit a838a4f69f500fc8e39fb4c9a1476f162ccf8423 by
[ARM] Extend search for increment in load/store optimizer

Currently the findIncDecAfter will only look at the next instruction for
post-inc candidates in the load/store optimizer. This extends that to a
search through the current BB, until an instruction that modifies or
uses the increment reg is found. This allows more post-inc load/stores
and ldm/stm's to be created, especially in cases where a schedule might
move instructions further apart.

We make sure not to look any further for an SP, as that might invalidate
stack slots that are still in use.

Differential Revision:
The file was modifiedllvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
The file was modifiedllvm/test/CodeGen/ARM/indexed-mem.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-float32regloops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vldshuffle.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
Commit 6f21adac6dd7082f7231ae342d40ed04f4885e79 by vsavchenko
[analyzer][NFC] Fix test failures for builds w/o assertions
The file was modifiedclang/test/Analysis/reinterpret-cast-pointer-to-member.cpp
Commit 2d728bbff5c688284b8b8306ecfd3000b0ab8bb1 by caroline.concatto
[CodeGen][SelectionDAG]Add new intrinsic  experimental.vector.reverse

This patch adds  a new intrinsic experimental.vector.reduce that takes a single
vector and returns a vector of matching type but with the original lane order
reversed. For example:

vector.reverse(<A,B,C,D>) ==> <D,C,B,A>

The new intrinsic supports fixed and scalable vectors types.
The fixed-width vector relies on shufflevector to maintain existing behaviour.
Scalable vector uses the new ISD node - VECTOR_REVERSE.

This new intrinsic is one of the named shufflevector intrinsics proposed on the
mailing-list in the RFC at [1].

Patch by Paul Walker (@paulwalker-arm).


Differential Revision:
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
The file was addedllvm/test/Transforms/InstSimplify/named-vector-shuffle-reverse.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
The file was modifiedllvm/include/llvm/IR/
The file was modifiedllvm/lib/Target/AArch64/
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/include/llvm/Target/
The file was addedllvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64FastISel.cpp
The file was addedllvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll
The file was modifiedllvm/include/llvm/CodeGen/ISDOpcodes.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
The file was modifiedllvm/docs/LangRef.rst
The file was addedllvm/test/CodeGen/X86/named-vector-shuffle-reverse.ll
Commit 176379e0c8f9dbde2b357fb3b6a6802b83282e71 by zinenko
[mlir] Use the interface-based translation for LLVM "intrinsic" dialects

Port the translation of five dialects that define LLVM IR intrinsics
(LLVMAVX512, LLVMArmNeon, LLVMArmSVE, NVVM, ROCDL) to the new dialect
interface-based mechanism. This allows us to remove individual translations
that were created for each of these dialects and just use one common
MLIR-to-LLVM-IR translation that potentially supports all dialects instead,
based on what is registered and including any combination of translatable
dialects. This removal was one of the main goals of the refactoring.

To support the addition of GPU-related metadata, the translation interface is
extended with the `amendOperation` function that allows the interface
implementation to post-process any translated operation with dialect attributes
from the dialect for which the interface is implemented regardless of the
operation's dialect. This is currently applied to "kernel" functions, but can
be used to construct other metadata in dialect-specific ways without
necessarily affecting operations.

Depends On D96591, D96504

Reviewed By: nicolasvasilache

Differential Revision:
The file was addedmlir/include/mlir/Target/LLVMIR/Dialect/LLVMArmSVE/LLVMArmSVEToLLVMIRTranslation.h
The file was removedmlir/include/mlir/Target/NVVMIR.h
The file was addedmlir/lib/Target/LLVMIR/Dialect/LLVMArmNeon/LLVMArmNeonToLLVMIRTranslation.cpp
The file was modifiedmlir/include/mlir/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.h
The file was modifiedmlir/lib/Target/CMakeLists.txt
The file was addedmlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
The file was addedmlir/lib/Target/LLVMIR/Dialect/NVVM/CMakeLists.txt
The file was addedmlir/include/mlir/Target/LLVMIR/Dialect/LLVMArmNeon/LLVMArmNeonToLLVMIRTranslation.h
The file was addedmlir/lib/Target/LLVMIR/Dialect/LLVMArmSVE/CMakeLists.txt
The file was addedmlir/lib/Target/LLVMIR/Dialect/LLVMArmNeon/CMakeLists.txt
The file was removedmlir/lib/Target/LLVMIR/ConvertToROCDLIR.cpp
The file was modifiedmlir/test/Target/nvvmir.mlir
The file was removedmlir/include/mlir/Target/ROCDLIR.h
The file was modifiedmlir/include/mlir/Target/LLVMIR.h
The file was addedmlir/include/mlir/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.h
The file was addedmlir/lib/Target/LLVMIR/Dialect/LLVMAVX512/CMakeLists.txt
The file was modifiedmlir/test/Target/arm-sve.mlir
The file was modifiedmlir/include/mlir/Target/LLVMIR/LLVMTranslationInterface.h
The file was removedmlir/lib/Target/LLVMIR/LLVMArmSVEIntr.cpp
The file was modifiedmlir/tools/mlir-rocm-runner/mlir-rocm-runner.cpp
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/
The file was modifiedmlir/examples/standalone/test/Standalone/standalone-translate.mlir
The file was modifiedmlir/include/mlir/InitAllTranslations.h
The file was removedmlir/lib/Target/LLVMIR/ConvertToNVVMIR.cpp
The file was addedmlir/include/mlir/Target/LLVMIR/Dialect/ROCDL/ROCDLToLLVMIRTranslation.h
The file was modifiedmlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
The file was modifiedmlir/test/Target/rocdl.mlir
The file was modifiedmlir/tools/mlir-cuda-runner/mlir-cuda-runner.cpp
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/
The file was modifiedmlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt
The file was addedmlir/include/mlir/Target/LLVMIR/Dialect/LLVMAVX512/LLVMAVX512ToLLVMIRTranslation.h
The file was modifiedmlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
The file was removedmlir/lib/Target/LLVMIR/LLVMAVX512Intr.cpp
The file was removedmlir/lib/Target/LLVMIR/LLVMArmNeonIntr.cpp
The file was addedmlir/lib/Target/LLVMIR/Dialect/LLVMAVX512/LLVMAVX512ToLLVMIRTranslation.cpp
The file was modifiedmlir/lib/Target/LLVMIR/ModuleTranslation.cpp
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/
The file was addedmlir/lib/Target/LLVMIR/Dialect/ROCDL/CMakeLists.txt
The file was modifiedmlir/lib/Target/LLVMIR/ConvertToLLVMIR.cpp
The file was modifiedmlir/test/lib/Transforms/TestConvertGPUKernelToHsaco.cpp
The file was modifiedmlir/include/mlir/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.h
The file was addedmlir/lib/Target/LLVMIR/Dialect/ROCDL/ROCDLToLLVMIRTranslation.cpp
The file was modifiedmlir/test/Target/avx512.mlir
The file was modifiedmlir/test/lib/Transforms/TestConvertGPUKernelToCubin.cpp
The file was addedmlir/lib/Target/LLVMIR/Dialect/LLVMArmSVE/LLVMArmSVEToLLVMIRTranslation.cpp
The file was modifiedmlir/test/Target/arm-neon.mlir
The file was modifiedmlir/test/lib/Transforms/CMakeLists.txt
The file was modifiedmlir/tools/mlir-tblgen/LLVMIRConversionGen.cpp
Commit 50c19b4c11ec9946fca536b9940680311726d2ef by llvm-dev
Fix MSVC natvis visualisation of llvm::FixedVectorTyID and ScalableVectorTyID

VectorTyID was replaced with FixedVectorTyID and ScalableVectorTyID
The file was modifiedllvm/utils/LLVMVisualizers/llvm.natvis
Commit 5fe15934388f9ce7b3c564eb48d2fe8bafea14cf by kerry.mclaughlin
[LoopVectorizer] Require no-signed-zeros-fp-math=true for fmin/fmax

Currently, setting the `no-nans-fp-math` attribute to true will allow
loops with fmin/fmax to vectorize, though we should be requiring that
`no-signed-zeros-fp-math` is also set.

This patch adds the check for no-signed-zeros at the function level and includes
tests to make sure we don't vectorize functions with only one of the attributes

Reviewed By: spatel

Differential Revision:
The file was modifiedllvm/test/Transforms/LoopVectorize/float-minmax-instruction-flag.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/minmax_reduction.ll
The file was modifiedllvm/include/llvm/Analysis/IVDescriptors.h
The file was modifiedllvm/lib/Analysis/IVDescriptors.cpp
Commit eefd620a2572d1a640b9085ea60dbf37e680159a by kbobyrev
[llvm] NFC: Cleanup llvm-yaml-numeric-parser-fuzzer

* Use static variables instead of non-trivially destructible global ones.
* Remove unused header.

Differential Revision:
The file was modifiedllvm/tools/llvm-yaml-numeric-parser-fuzzer/yaml-numeric-parser-fuzzer.cpp
Commit 94828afd0a178d00abec87143b48fe0d7c063198 by james.henderson
[llvm-nm] Tidy up error messages

This adds colons to separate the file name from the message, removes a
duplicate space, and removes a trailing full stop from some messages.
These help bring the error messages into line with other tools, as well
as making all llvm-nm message more self-consistent.

Differential Revision:

Reviewed by: Higuoxing, rupprecht, MaskRay
The file was modifiedllvm/test/Object/nm-archive.test
The file was modifiedllvm/test/Object/macho-invalid.test
The file was modifiedllvm/tools/llvm-nm/llvm-nm.cpp
The file was modifiedllvm/test/Object/nm-shared-object.test
The file was modifiedllvm/test/Object/nm-tapi-invalids.test
The file was modifiedllvm/test/tools/llvm-nm/dynamic.test
The file was modifiedllvm/test/tools/llvm-nm/invalid-input.test
Commit 37c89803d860c6dd954cda1480dae6917f006972 by james.henderson
[llvm-nm][test] Add additional test coverage for llvm-nm options

Some of these options have a degree of incidental coverage, or are for
Mach-O only. This patch adds dedicated ELF (where applicable) coverage.

Differential Revision:

Reviewed by: rupprecht, Higuoxing
The file was addedllvm/test/tools/llvm-nm/reverse-sort.test
The file was addedllvm/test/tools/llvm-nm/defined-only.test
The file was addedllvm/test/tools/llvm-nm/X86/bitcode.test
The file was addedllvm/test/tools/llvm-nm/format-bsd.test
The file was addedllvm/test/tools/llvm-nm/just-symbol-name.test
Commit 1d6f08e61d9771baf5381198ac5d306f6cbcd302 by zinenko
[mlir] use new cmake targets in mlir-*-runner
The file was modifiedmlir/tools/mlir-cuda-runner/CMakeLists.txt
The file was modifiedmlir/tools/mlir-rocm-runner/CMakeLists.txt
Commit 65292fe3a2101a5ce9b01f089cdc077320e53b13 by llvm-dev
[X86] Add SSE2+SSE3 common check prefix to psubus tests

Noticed by @pengfei on D96703
The file was modifiedllvm/test/CodeGen/X86/psubus.ll
Commit 6c330f0df8da7f6b94f511fc3f5573003fdda093 by james.henderson
[debuginfo-tests] Remove explicit checks for Python 3

LLVM has a minimum requirement of python 3.6 now, and Python is
explicitly checked for in the LLVM CMakeLists.txt, so this check is no
longer needed here.

Differential Revision:

Reviewed by: aprantl
The file was modifieddebuginfo-tests/CMakeLists.txt
The file was modifieddebuginfo-tests/
The file was modifieddebuginfo-tests/
Commit d6236524993e81904e75e9ddc3d497230b858a89 by james.henderson
[debuginfo-tests] Remove some unused config variables

Differential Revision:

Reviewed by: aprantl
The file was modifieddebuginfo-tests/
Commit b52e6c58911f60eebd20b59bc89d7a230aececab by caroline.concatto
[CostModel]Add cost model for experimental.vector.reverse

This patch uses the function getShuffleCost with SK_Reverse to compute the cost
for experimental.vector.reverse.
For scalable vector type, it adds a table will the legal types on
AArch64TTIImpl::getShuffleCost to not assert in BasicTTIImpl::getShuffleCost,
and for fixed vector, it relies on the existing cost model in BasicTTIImpl.

Depends on D94883

Differential Revision:
The file was addedllvm/test/Analysis/CostModel/AArch64/getIntrinsicInstrCost-vector-reverse.ll
The file was addedllvm/test/Analysis/CostModel/AArch64/sve-getIntrinsicInstrCost-vector-reverse.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
Commit e8b9da712f579cbd18f5b993e984c18c501f4802 by james.henderson
[debuginfo-tests] Delete unused/duplicate imports

Differential Revision:

Reviewed by: aprantl
The file was modifieddebuginfo-tests/
Commit 3842d4b6791f6fbd67a1d12806f05a05654728cf by tpopp
Make shape.is_broadcastable/shape.cstr_broadcastable nary

This corresponds with the previous work to make shape.broadcast nary.
Additionally, simplify the ConvertShapeConstraints pass. It now doesn't
lower an implicit shape.is_broadcastable. This is still the same in
combination with shape-to-standard when the 2 passes are used in either

Differential Revision:
The file was modifiedmlir/lib/Dialect/Shape/IR/Shape.cpp
The file was modifiedmlir/lib/Dialect/Shape/IR/
The file was modifiedmlir/lib/Conversion/ShapeToStandard/
The file was modifiedmlir/lib/Conversion/ShapeToStandard/ShapeToStandard.cpp
The file was modifiedmlir/test/Conversion/ShapeToStandard/convert-shape-constraints.mlir
The file was modifiedmlir/lib/Conversion/ShapeToStandard/ConvertShapeConstraints.cpp
The file was modifiedmlir/include/mlir/Dialect/Shape/IR/
The file was modifiedmlir/test/Dialect/Shape/invalid.mlir
The file was modifiedmlir/test/Conversion/ShapeToStandard/shape-to-standard.mlir
Commit 0a98efb049393a579a1e44a68bfa886475ea672c by
[ARM] Add some basic Min/Max costs

This adds basic MVE costs for SMIN/SMAX/UMIN/UMAX, as well as MINNUM and
MAXNUM representing fmin and fmax. It tightens up the costs, not using a
ICmp+Select cost.

Differential Revision:
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll
The file was modifiedllvm/test/Analysis/CostModel/ARM/mve-minmax.ll
Commit 99dbc0fa76010f3dcbb4c1b63bfa410c1ad44e7c by caroline.concatto
[LangRef] Increase size of title underline for experimental.vector.reverse
The file was modifiedllvm/docs/LangRef.rst
Commit ca23b2c8ed2733f0584ca8bc0514b173938f1cdc by flo
[AArch64] Move machine bundle unpacking to PreEmit2 phase.

This patch adjusts the placement of the bundle unpacking to just before
code emission. In particular, this means bundle unpacking happens AFTER
the machine outliner. With the previous position, the machine outliner
may outline parts of a bundle, which breaks them up.

This is an issue for BLR_RVMARKER handling, as illustrated by the
rvmarker-pseudo-expansion-and-outlining.mir test case. The machine
outliner should not break up the bundles created during pseudo

This should fix PR49082.

Reviewed By: SjoerdMeijer

Differential Revision:
The file was modifiedllvm/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AArch64/rvmarker-pseudo-expansion-and-outlining.mir
The file was modifiedllvm/test/CodeGen/AArch64/O3-pipeline.ll
The file was modifiedllvm/test/CodeGen/AArch64/O0-pipeline.ll