1. [gn build] Port 40cc63ea6eec (details)
  2. [clangd] Give modules access to filesystem, scheduler, and index. (details)
  3. [lldb/test] Test lldb-server named pipe functionality on windows (details)
  4. [mlir][vector] Add support for unrolling vector.fma (details)
  5. [libc++] Build thread_win32.cpp only if LIBCXX_HAS_PTHREAD_API is not set (details)
  6. [mlir][vector] Move splitting transfer ops into a separate entry point (details)
  7. [mlir] Add canonicalization for tensor_cast + tensor_to_memref (details)
  8. [mlir][vector] Add missing support for contract of integer lowering. (details)
  9. Reduce the number of attributes attached to each function (details)
  10. AMDGPU: Fix debug info handling in post-RA bundler (details)
  11. [DAG] Fold shuffle(bop(shuffle(x,y),shuffle(z,w)),bop(shuffle(a,b),shuffle(c,d))) (details)
  12. AMDGPU: Remove kills following clusters of memory instruction (details)
  13. [ARM] Use rGPR for writeback vldrs (details)
  14. [flang][fir] Add fir-opt tool (details)
  15. [coro async] Don't promote allocas to the frame or rewrite  swifterror if there are no suspend points (details)
  16. [mlir] add verifiers for NVVM and ROCDL kernel attributes (details)
  17. [analyzer] Fix a warning (details)
  18. [libc][NFC] Make few maths functions buildable outside of LLVM libc build. (details)
  19. [AArch64] Convert CMP/SELECT sign patterns to OR & ASR. (details)
  20. [mlir] tighten LLVM dialect verifiers to generate valid LLVM IR (details)
Commit b2db4934ed5b55008108ccace6824ed7c1519e7a by llvmgnsyncbot
[gn build] Port 40cc63ea6eec
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
Commit b6e52d8fa7217db319e240854a9d8ff3133d02b6 by sam.mccall
[clangd] Give modules access to filesystem, scheduler, and index.

This finally makes it possible to implement useful modules.

Differential Revision: https://reviews.llvm.org/D96726
The file was modifiedclang-tools-extra/clangd/ClangdServer.cpp
The file was modifiedclang-tools-extra/clangd/Module.h
The file was modifiedclang-tools-extra/clangd/Module.cpp
The file was modifiedclang-tools-extra/clangd/unittests/ClangdLSPServerTests.cpp
Commit 85f025e5b33d148808177427eebca4cc14f93079 by pavel
[lldb/test] Test lldb-server named pipe functionality on windows

lldb-server can use a named pipe to communicate the port number it is
listening on. This windows bits of this are already implemented, but we
did not have a test for that, most likely because python does not have
native pipe functionality.

This patch implements the windows bits necessary to test this. I'm using
the ctypes package to call the native APIs directly to avoid a
dependency to non-standard python packages. This introduces some amount
of boilerplate, but our named pipe use case is fairly limited, so we
should not end up needing to wrap large chunks of windows APIs.

Surprisingly to changes to lldb-server were needed to make the test

Differential Revision: https://reviews.llvm.org/D96260
The file was modifiedlldb/test/API/tools/lldb-server/commandline/TestGdbRemoteConnection.py
Commit d8c7f442eaf21a5ad42a5ac101f66b69984ef065 by antiagainst
[mlir][vector] Add support for unrolling vector.fma

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D96781
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/test/Dialect/Vector/vector-unroll-options.mlir
The file was modifiedmlir/test/lib/Transforms/TestVectorTransforms.cpp
Commit 0f5020af7f347f029b5687f7a6d3b72174995d59 by Louis Dionne
[libc++] Build thread_win32.cpp only if LIBCXX_HAS_PTHREAD_API is not set

This allows building libc++ against winpthreads from mingw-w64 to support
operating systems older than Windows 7. The remaining libc++ code already
supports `WIN32` with `LIBCXX_HAS_PTHREAD_API`.

Note that there is also the older "pthreads-win32". However, that support
library implements `pthread_t` as a struct, which violates the libc++
assumption that `pthread_t` is always a scalar and can be compared,
ordered, and set to zero.

Differential Revision: https://reviews.llvm.org/D96339
The file was modifiedlibcxx/src/CMakeLists.txt
Commit cb1a42359bff2ba49d072df88ad3ffb4c66c16d8 by antiagainst
[mlir][vector] Move splitting transfer ops into a separate entry point

These patterns unrolls transfer read/write ops if the vector consumers/
producers are extract/insert slices op. Transfer ops can map to hardware
load/store functionalities, where the vector size matters for bandwidth
considerations. So these patterns should be collected separately, instead
of being generic canonicalization patterns.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D96782
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
The file was modifiedmlir/test/lib/Transforms/TestVectorTransforms.cpp
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.h
Commit 807e5467f3e1b115f53377ea36ecad5625ce8280 by thomasraoux
[mlir] Add canonicalization for tensor_cast + tensor_to_memref

This helps bufferization passes by removing tensor_cast operations.

Differential Revision: https://reviews.llvm.org/D96745
The file was modifiedmlir/test/Dialect/Standard/canonicalize.mlir
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
Commit 397336dcab81dd0bb95e50e95c737c3e77ee7985 by thomasraoux
[mlir][vector] Add missing support for contract of integer lowering.

Some of the lowering of vector.contract didn't support integer case. Since
reduction of integer cannot accumulate we always break up the reduction op, it
should be merged by a separate canonicalization if possible.

Differential Revision: https://reviews.llvm.org/D96461
The file was modifiedmlir/test/Dialect/Vector/vector-contract-transforms.mlir
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
Commit 3c8bf29f14e45cdf4c5dc5edcb3bb2f02cc9f394 by sguelton
Reduce the number of attributes attached to each function

This takes advantage of the implicit default behavior to reduce the number of
attributes, which in turns reduces compilation time. I've observed -3% in
instruction count when compiling sqlite3 amalgamation with -O0

Differential Revision: https://reviews.llvm.org/D96400
The file was modifiedclang/test/CodeGenOpenCL/no-signed-zeros.cl
The file was modifiedclang/lib/CodeGen/CGCall.cpp
The file was modifiedclang/test/CodeGen/attr-target-x87-softfp.c
The file was modifiedclang/test/CodeGenOpenCL/relaxed-fpmath.cl
Commit c320e8196ae67a4eaa72253ed9013dda28eaf390 by Matthew.Arsenault
AMDGPU: Fix debug info handling in post-RA bundler

This was allowing debug instructions to break the bundling, which
would change scheduling behavior. Bundle debug info / kills inside
the bundle. This seems to work OK, although the asm printer doesn't
understand these in a bundle. This implicitly expects the memory
legalizer to unbundle. It would probably be slightly nicer to move
these after.

Rewrite the loop to be clearer and make sure we don't end a bundle on
a meta instruction, only allow them in between other valid bundle
The file was modifiedllvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIPostRABundler.cpp
The file was addedllvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
Commit 5dfba562dd247f731528448ee83785b099f93629 by llvm-dev
[DAG] Fold shuffle(bop(shuffle(x,y),shuffle(z,w)),bop(shuffle(a,b),shuffle(c,d)))

Fold shuffle(bop(shuffle(x,y),shuffle(z,w)),bop(shuffle(a,b),shuffle(c,d))) -> bop(shuffle(x,y),shuffle(z,w)),bop(shuffle(a,b),shuffle(c,d))

Attempt to fold from a shuffle of a pair of binops to a binop of shuffles, as long as one/both of the binop sources are also shuffles that can be merged with the outer shuffle. This should guarantee that we remove one binop without introducing any additional shuffles.

Technically there's potential for a merged shuffle's lowering to be poorer than the original shuffle, but it could also be better, and I'm not seeing any regressions as long as we keep the 'don't merge splats' rule already present in MergeInnerShuffle.

This expands and generalizes an existing X86 combine and attempts to merge either of each binop's sources (with an on-the-fly commutation of the shuffle mask) - we couldn't do that in the x86 version as it had to stay in a form that DAGCombine's MergeInnerShuffle would still recognise.

Differential Revision: https://reviews.llvm.org/D96345
The file was modifiedllvm/test/CodeGen/X86/bitcast-and-setcc-256.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/X86/promote-cmp.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit a7455d7b7ce33bb4d04106e26f242e6cb24f3042 by Matthew.Arsenault
AMDGPU: Remove kills following clusters of memory instruction

In a future commit, soft clauses will be hinted with kill instructions
rather than forced together with bundles. Look for kills that look
like this, and erase them. I'm not sure if the check for specific uses
is worthwhile, or if it would be better to just unconditionally erase

This reduces test churn in a future patch.
The file was modifiedllvm/lib/Target/AMDGPU/SIPostRABundler.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
Commit 1e007cf43c50d4ed4b85e30d4a0416c137075b98 by david.green
[ARM] Use rGPR for writeback vldrs

From what I can tell, a writeback is unpredictable with LR for both
loads and stores. This changes the operand from a gprnopc to a rGPR in
both cases (which I believe is essentially a NFC due to the tied-def
already being a rGPR.)

Differential Revision: https://reviews.llvm.org/D96723
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/count_dominates_start.mir
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
Commit 8260232cdd138d1357d308e43c33f0f16044f44c by clementval
[flang][fir] Add fir-opt tool

This patch introduce the fir-opt tool. Similar to mlir-opt for FIR.
It will be used in following patches to test fir opt and round-trip.

Reviewed By: schweitz, mehdi_amini

Differential Revision: https://reviews.llvm.org/D96535
The file was modifiedflang/test/CMakeLists.txt
The file was modifiedflang/tools/CMakeLists.txt
The file was modifiedflang/test/Fir/fir-ops.fir
The file was addedflang/tools/fir-opt/fir-opt.cpp
The file was modifiedflang/test/Fir/fir-types.fir
The file was addedflang/tools/fir-opt/CMakeLists.txt
Commit 627cfd4394b0c4677c8a33338d92bd92101b8ee1 by aschwaighofer
[coro async] Don't promote allocas to the frame or rewrite  swifterror if there are no suspend points

Also don't call function to update the call graph if there are no
clones. The function will fail.


Differential Revision: https://reviews.llvm.org/D96620
The file was modifiedllvm/test/Transforms/Coroutines/coro-async.ll
The file was modifiedllvm/lib/Transforms/Coroutines/CoroFrame.cpp
The file was modifiedllvm/lib/Transforms/Coroutines/CoroSplit.cpp
Commit 9cd47a26d593985ad2b36857cb9fcbc7659ffde8 by zinenko
[mlir] add verifiers for NVVM and ROCDL kernel attributes

Make sure they can only be attached to LLVM functions as a result of converting
GPU functions to the LLVM Dialect.
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
The file was modifiedmlir/test/Dialect/LLVMIR/rocdl.mlir
The file was modifiedmlir/lib/Target/LLVMIR/Dialect/ROCDL/ROCDLToLLVMIRTranslation.cpp
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
The file was modifiedmlir/test/Dialect/LLVMIR/nvvm.mlir
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
The file was modifiedmlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
Commit 1a323c8a96afc53ef965a4268cd419cfde2f1890 by kazu
[analyzer] Fix a warning

This patch fixes a warning from -Wcovered-switch-default.  The switch
statement in question handles all the enum values.
The file was modifiedclang/lib/StaticAnalyzer/Core/SValBuilder.cpp
Commit dba14814a69143a8763ed4276a38fa9509b5973d by sivachandra
[libc][NFC] Make few maths functions buildable outside of LLVM libc build.

Few math functions manipulate errno. They assumed that LLVM libc's errno
is available. However, that might not be the case when these functions
are used in a libc which does not use LLVM libc's errno. This change
switches such uses of LLVM libc's errno to the normal public errno macro.
This does not affect LLVM libc's build because the include order ensures
we get LLVM libc's errno. Also, the header check rule ensures we are only
including LLVM libc's errno.h.
The file was modifiedlibc/utils/FPUtil/NearestIntegerOperations.h
The file was modifiedlibc/utils/FPUtil/CMakeLists.txt
The file was modifiedlibc/test/src/math/RoundToIntegerTest.h
Commit 211147c5ba49a17c8624186f50519885d89ca33d by flo
[AArch64] Convert CMP/SELECT sign patterns to OR & ASR.

ICMP & SELECT patterns extracting the sign of a value can be simplified
to OR & ASR (see  https://alive2.llvm.org/ce/z/Xx4iZ0).

This does not save any instructions in IR, but it is profitable on
AArch64, because we need at least 2 extra instructions to materialize 1
and -1 for the SELECT.

The improvements result in ~5% speedups on loops of the form

    static int sign_of(int x) {
      if (x < 0) return -1;
      return 1;

    void foo(const int *x, int *res, int cnt) {
      for (int i=0;i<cnt;i++)
        res[i] = sign_of(x[i]);

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D96596
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/cmp-select-sign.ll
Commit 2ab57c503ed9d235bf7bf9334a414e1d3c628d17 by zinenko
[mlir] tighten LLVM dialect verifiers to generate valid LLVM IR

Verification of the LLVM IR produced when translating various MLIR dialects was
only active when calling the translation programmatically. This has led to
several cases of invalid LLVM IR being generated that could not be caught with
textual mlir-translate tests. Add verifiers for these cases and fix the tests
in preparation for enforcing the validation of LLVM IR.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D96774
The file was modifiedmlir/test/Dialect/LLVMIR/invalid.mlir
The file was modifiedmlir/test/Target/rocdl.mlir
The file was modifiedmlir/test/Target/llvmir.mlir
The file was modifiedmlir/test/Target/llvmir-intrinsics.mlir
The file was modifiedmlir/test/Target/import.ll
The file was modifiedmlir/test/Target/avx512.mlir
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
The file was modifiedmlir/test/Dialect/LLVMIR/global.mlir
The file was modifiedmlir/test/Target/nvvmir.mlir
The file was modifiedmlir/test/Dialect/LLVMIR/roundtrip.mlir