SuccessChanges

Summary

  1. [NFC] Use the same type for bit fields in MCSchedClassDesc (details)
  2. [clang][cli] Documentation of CompilerInvocation parsing/generation (details)
  3. [libcxx] Implement parsing of root_name for paths on windows (details)
  4. [ARM] MVE abs intrinsic costs. NFC (details)
  5. [mlir][spirv] Add spv.GLSL.FrexpStruct (details)
  6. Use LoopRotate PrepareForLTO stage in NPM (details)
  7. [AMDGPU] Add implicit vcc_lo on S_CBRANCH_VCCNZ in wave32 (details)
  8. [OpenCL] Support enum and typedef args in TableGen BIFs (details)
  9. [ARM] Add MVE abs costs (details)
  10. [PowerPC] Handle FP physical register in inline asm constraint. (details)
  11. [clangd] Pass file when possible to resolve URI. (details)
  12. [clangd] IndexedFiles should include Fils from RefSlab and RelationSlab. (details)
  13. [PowerPC][AIX] Enable Shrinkwrapping on 32 and 64 bit AIX. (details)
  14. [Fuzzer][Test] Use %python substitution for trace-malloc-unbalanced.test (details)
  15. [lldb][NFC] Delete deleted const char* overloads of SetValueFromString (details)
  16. [mlir][StandardToSPIRV] Add support for lowering trunci to SPIR-V to i1 types. (details)
  17. build: Add LLVM_WINSYSROOT to make setting /winsysroot easy on Win (details)
  18. [InstCombine] add tests for fcmp-of-copysign; NFC (details)
  19. [InstCombine] fold fcmp-of-copysign idiom (details)
Commit 4bee0dc918d20a52be9d1766c82a642268b5e1ee by andrew.savonichev
[NFC] Use the same type for bit fields in MCSchedClassDesc

Otherwise they are not allocated as a single bit field and take 4
bytes instead of 2.

Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D95954
The file was modifiedllvm/include/llvm/MC/MCSchedule.h
Commit 8ddfcec91b7801af058f43906073822d7f146bf5 by Jan Svoboda
[clang][cli] Documentation of CompilerInvocation parsing/generation

This patch documents command line parsing in `-cc1`, `CompilerInvocation` and the marshalling infrastructure for command line options.

Reviewed By: Bigcheese

Differential Revision: https://reviews.llvm.org/D95790
The file was modifiedclang/docs/InternalsManual.rst
Commit 929f0bcc24e246ea02ab57df8009a6fd5751d45c by martin
[libcxx] Implement parsing of root_name for paths on windows

Differential Revision: https://reviews.llvm.org/D91176
The file was modifiedlibcxx/src/filesystem/operations.cpp
Commit 415deff10b439c3ecda3230432709f678f5847ae by david.green
[ARM] MVE abs intrinsic costs. NFC
The file was addedllvm/test/Analysis/CostModel/ARM/mve-abs.ll
Commit 7742620620b9e62476abc4aedfa5e14ea8336ad1 by antiagainst
[mlir][spirv] Add spv.GLSL.FrexpStruct

co-authored-by: Alan Liu <alanliu.yf@gmail.com>

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D96527
The file was modifiedmlir/test/Target/SPIRV/glsl-ops.mlir
The file was modifiedmlir/test/Dialect/SPIRV/IR/glsl-ops.mlir
The file was modifiedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLSLOps.td
The file was modifiedmlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
Commit 93d9a4c95aff62bad9603029ee38faedfee40dea by Sanne.Wouda
Use LoopRotate PrepareForLTO stage in NPM

The PrepareForLTO stage of LoopRotate tries to avoid unrolling loops
with calls that might be inlined later.  See D94232 where this was
introduced.

We didn't catch all occurances of the LoopRotatePass in the New Pass
Manager, so the original regression in astar returned with the pass
manager switch.
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
Commit c72a63b4b06a0e96cecba36f6bc8df9f8ef81cce by Piotr Sobczak
[AMDGPU] Add implicit vcc_lo on S_CBRANCH_VCCNZ in wave32

* Update skip-if-dead.ll with tests for wave32.
* Fix the crash in verifier in one newly enabled test by adding
  missing fixImplicitOperands in branch insertion code.

```
*** Bad machine code: Using an undefined physical register ***
- function:    test_kill_divergent_loop
- basic block: %bb.2 bb (0xad96308)
- instruction: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo
- operand 1:   implicit $vcc_lo
LLVM ERROR: Found 1 machine code errors.
```

* Simplify "cbranch_kill" to not use interp instructions.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D96793
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/skip-if-dead.ll
Commit 23d65aa446312402a0b4615122f0a18d4467ed60 by sven.vanhaastregt
[OpenCL] Support enum and typedef args in TableGen BIFs

Add enum and typedef argument support to `-fdeclare-opencl-builtins`,
which was the last major missing feature.

Adding the remaining missing builtins is left as future work.

Differential Revision: https://reviews.llvm.org/D96051
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/SemaOpenCL/fdeclare-opencl-builtins.cl
The file was modifiedclang/lib/Sema/SemaLookup.cpp
The file was modifiedclang/lib/Sema/OpenCLBuiltins.td
The file was modifiedclang/utils/TableGen/ClangOpenCLBuiltinEmitter.cpp
Commit 6d835c5fcd63dd875f78e53d9124a53491fa471e by david.green
[ARM] Add MVE abs costs

Similar to min/max, this increases the accuracy of abs intrinsics costs
under MVE.
The file was modifiedllvm/test/Analysis/CostModel/ARM/mve-abs.ll
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
Commit 4e127bce2d1133ba95a551d69bd0e8fc3b4f9e71 by sd.fertile
[PowerPC] Handle FP physical register in inline asm constraint.

Do not defer to the base class when the register constraint is a
physical fpr. The base class will select SPILLTOVSRRC as the register
class and register allocation will fail on subtargets without VSX
registers.

Differential Revision: https://reviews.llvm.org/D91629
The file was addedllvm/test/CodeGen/PowerPC/inline-asm-physical-fpr.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was addedllvm/test/CodeGen/PowerPC/inline-asm-physical-fpr-spe.ll
Commit e030de7e5a28de1bcc337ede445600f8d282d252 by hokein.wu
[clangd] Pass file when possible to resolve URI.

Some URI scheme needs the hint path to do a correct resolution, we pass
one of the open files as hint path.

This is not perfect, and it might not work for opening files across
project, but it would fix a bug with our internal scheme.

in the long run, removing URIs from all the index internals is a more proper fix.

Differential Revision: https://reviews.llvm.org/D96844
The file was modifiedclang-tools-extra/clangd/index/dex/Dex.cpp
The file was modifiedclang-tools-extra/clangd/index/MemIndex.cpp
Commit 7048cb5371f93788ee650c521995a85211f3ae46 by hokein.wu
[clangd] IndexedFiles should include Fils from RefSlab and RelationSlab.

This looks like an oversight.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D96845
The file was modifiedclang-tools-extra/clangd/index/FileIndex.cpp
Commit cb2876800cc827431f4143c4fc5595c6c1191269 by sidharth.baveja
[PowerPC][AIX] Enable Shrinkwrapping on 32 and 64 bit AIX.

Summary:
Currently Shrinkwrap is not enabled on AIX.
This patch enables shrink wrap on 32 and 64 bit AIX, and 64 bit ELF.

Reviewed By: sfertile, nemanjai

Differential Revision: https://reviews.llvm.org/D95094
The file was modifiedllvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll
The file was modifiedllvm/test/CodeGen/PowerPC/shrink-wrap.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCFrameLowering.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
The file was modifiedllvm/test/CodeGen/PowerPC/shrink-wrap.mir
Commit f8ed31cd991bf84372369409595707f6e3cebbce by greg.bedwell
[Fuzzer][Test] Use %python substitution for trace-malloc-unbalanced.test

This test was found to fail for some of our downstream builds, on
computers where python was not on the default $PATH. Therefore
add a %python substitution to use sys.executable, based on similar
solutions for python calls in tests elsewhere in LLVM.

Differential Revision: https://reviews.llvm.org/D96799
The file was modifiedcompiler-rt/test/fuzzer/trace-malloc-unbalanced.test
The file was modifiedcompiler-rt/test/fuzzer/lit.cfg.py
Commit 8bcc03767e440f229749d101f470f73b8e1cd2e5 by Raphael Isemann
[lldb][NFC] Delete deleted const char* overloads of SetValueFromString

This came up during the review of D96817 because those deleted overloads force
the caller to explicitly create a StringRef when passing a string literal.

It seems they were added as some kind of help while migrating the code base to
StringRef in D24847, but I don't think they have any use these days and make
these functions awkward to use.

This patch just removes all the deleted overloads.

Reviewed By: tatyana-krasnukha

Differential Revision: https://reviews.llvm.org/D96861
The file was modifiedlldb/include/lldb/Interpreter/OptionValueRegex.h
The file was modifiedlldb/include/lldb/Interpreter/OptionValueString.h
The file was modifiedlldb/include/lldb/Interpreter/OptionValueChar.h
The file was modifiedlldb/include/lldb/Interpreter/OptionValueFileSpec.h
The file was modifiedlldb/include/lldb/Interpreter/OptionValuePathMappings.h
The file was modifiedlldb/include/lldb/Interpreter/OptionValueUInt64.h
The file was modifiedlldb/include/lldb/Interpreter/OptionValueArch.h
The file was modifiedlldb/include/lldb/Interpreter/OptionValueFormat.h
The file was modifiedlldb/include/lldb/Interpreter/OptionValueFileSpecList.h
The file was modifiedlldb/include/lldb/Interpreter/OptionValueArray.h
The file was modifiedlldb/include/lldb/Interpreter/OptionValueUUID.h
The file was modifiedlldb/include/lldb/Interpreter/OptionValueLanguage.h
The file was modifiedlldb/include/lldb/Interpreter/OptionValueFileColonLine.h
The file was modifiedlldb/include/lldb/Interpreter/OptionValueFormatEntity.h
The file was modifiedlldb/include/lldb/Interpreter/OptionValueSInt64.h
The file was modifiedlldb/include/lldb/Interpreter/OptionValueEnumeration.h
The file was modifiedlldb/include/lldb/Interpreter/OptionValueBoolean.h
Commit c80484e16ed8a69f1bef7bedc687a3b31707ac30 by hanchung
[mlir][StandardToSPIRV] Add support for lowering trunci to SPIR-V to i1 types.

Add a pattern to converting some value to a boolean. spirv.S/UConvert does not
work on i1 types. Thus, the pattern is lowered to cmpi + select.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D96851
The file was modifiedmlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.cpp
Commit 44ea794cf9ab8590a6abdf6d61622ba85e5ab1bc by thakis
build: Add LLVM_WINSYSROOT to make setting /winsysroot easy on Win

Also add a script for sysroot management. For now, it can only create
fake sysroots that just symlink to local folders. This is useful for
testing.

Differential Revision: https://reviews.llvm.org/D96868
The file was modifiedllvm/utils/gn/build/BUILD.gn
The file was modifiedllvm/cmake/modules/HandleLLVMOptions.cmake
The file was addedllvm/utils/sysroot.py
Commit 236f82c64088c63fcb333d0f9999154c4e77f2c5 by spatel
[InstCombine] add tests for fcmp-of-copysign; NFC

https://llvm.org/PR49179
The file was modifiedllvm/test/Transforms/InstCombine/fcmp.ll
Commit 85294703a74a532448b3d3801d4e9a5c6024547a by spatel
[InstCombine] fold fcmp-of-copysign idiom

As discussed in:
https://llvm.org/PR49179
...this pattern shows up in library code.
There are several potential generalizations as noted,
but we need to be careful that we get FP special-values
right, and it's not clear how much variation we should
expect to see from this exact idiom.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
The file was modifiedllvm/test/Transforms/InstCombine/fcmp.ll