SuccessChanges

Summary

  1. NFC. Some getSingleBranchSchedulers code cleaning. (details)
Commit a0380870f2f3703e0a47c7161946f8821bc3e1fd by gkistanova
NFC. Some getSingleBranchSchedulers code cleaning.
The file was modifiedbuildbot/osuosl/master/config/schedulers.py (diff)

Summary

  1. [gn build] Port 7397905ab0a0 (details)
  2. [flang][fir][NFC] clang-tidy change (details)
  3. [obj2yaml,yaml2obj] Add NumBlocks to the BBAddrMapEntry yaml field. (details)
  4. [AMDGPU] gfx90a support (details)
  5. [WebAssembly] Remove dependency of reference types from EH (details)
  6. [gn build] add a comment to the goma_dir arg (details)
  7. [WPD] Add an optional checking mode for debugging devirtualization (details)
  8. [AMDGPU] Mark SMRD atomics (details)
  9. [NetBSD] Use cortex-a8 as default CPU for ARMv7 (details)
  10. [libunwind] Add support for PC reg column in arm64 (details)
  11. [flang][fir][NFC] Merge tablegen files. (details)
  12. [XCOFF][NFC] make csect properties optional for getXCOFFSection (details)
  13. [flang][fir][NFC] clang-tidy change. Add include. (details)
  14. [AMDGPU] Fixed msan build (details)
  15. [Clang][RISCV] Define RISC-V V builtin types (details)
  16. [mlir][sparse] generalize sparse storage format to many more types (details)
  17. [RISCV] Guard the ISD::EXTRACT_VECTOR_ELT handling in ReplaceNodeResults against fixed vectors and non-MVT types. (details)
  18. [LV] Add analysis remark for mixed precision conversions (details)
Commit ebcf921e4aa319c2b8294f5a6e5298cfce8d719b by llvmgnsyncbot
[gn build] Port 7397905ab0a0
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn
Commit 0d4534237de38fcf1b2a71bcb0f74cb5675fe7e1 by eschweitz
[flang][fir][NFC] clang-tidy change

Differential Revision: https://reviews.llvm.org/D96911
The file was modifiedflang/include/flang/Optimizer/Dialect/FIRAttr.h
Commit 0252e6ead192f7c61e5a02ceea420bee28a2f251 by rahmanl
[obj2yaml,yaml2obj] Add NumBlocks to the BBAddrMapEntry yaml field.

As discussed in D95511, this allows us to encode invalid BBAddrMap
sections to be used in more rigorous testing.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D96831
The file was modifiedllvm/lib/ObjectYAML/ELFYAML.cpp
The file was modifiedllvm/lib/ObjectYAML/ELFEmitter.cpp
The file was modifiedllvm/test/tools/obj2yaml/ELF/bb-addr-map.yaml
The file was modifiedllvm/include/llvm/ObjectYAML/ELFYAML.h
The file was modifiedllvm/test/tools/yaml2obj/ELF/bb-addr-map.yaml
The file was modifiedllvm/tools/obj2yaml/elf2yaml.cpp
Commit a8d9d50762c42d726274d3f1126ec97ff96e2a22 by Stanislav.Mekhanoshin
[AMDGPU] gfx90a support

Differential Revision: https://reviews.llvm.org/D96906
The file was modifiedllvm/test/CodeGen/AMDGPU/fold-multiple.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/schedule-barrier.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
The file was modifiedclang/lib/Basic/Targets/AMDGPU.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
The file was addedclang/test/SemaOpenCL/builtins-amdgcn-error-gfx90a-param.cl
The file was modifiedllvm/test/CodeGen/AMDGPU/subvector-test.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/merge-image-sample-gfx10.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
The file was addedllvm/test/MC/AMDGPU/hsa-gfx90a-v3.s
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
The file was addedllvm/test/MC/AMDGPU/gfx90a_err.s
The file was modifiedllvm/lib/Target/AMDGPU/SIFoldOperands.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
The file was addedllvm/test/CodeGen/AMDGPU/reserved-reg-in-clause.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir
The file was addedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-loop-irreducible.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
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The file was addedllvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f32.ll
The file was modifiedllvm/docs/AMDGPUUsage.rst
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The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td
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The file was addedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.fadd.gfx90a.ll
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The file was modifiedllvm/test/CodeGen/AMDGPU/regbank-reassign.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/mai-hazards.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
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The file was addedllvm/test/CodeGen/AMDGPU/coalesce-vgpr-alignment.ll
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The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.td
The file was modifiedllvm/test/Analysis/CostModel/AMDGPU/fmul.ll
The file was modifiedllvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/dead_copy.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
The file was addedllvm/test/CodeGen/AMDGPU/waitcnt-agpr.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIDefines.h
The file was modifiedllvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-meta-instructions.mir
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The file was addedllvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
The file was modifiedclang/test/Driver/amdgpu-features.c
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The file was modifiedllvm/include/llvm/BinaryFormat/ELF.h
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The file was modifiedllvm/lib/Target/AMDGPU/GCNRegPressure.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
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The file was modifiedllvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx10.mir
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The file was modifiedllvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir
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The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/pei-build-spill.mir
The file was modifiedllvm/include/llvm/Support/AMDHSAKernelDescriptor.h
The file was modifiedllvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
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The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
The file was addedllvm/test/CodeGen/AMDGPU/adjust-writemask-vectorized.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
The file was modifiedllvm/include/llvm/Support/TargetParser.h
The file was modifiedclang/test/Driver/hip-toolchain-features.hip
The file was modifiedllvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
The file was addedllvm/test/MC/Disassembler/AMDGPU/dpp64.txt
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrFormats.td
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The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir
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The file was modifiedllvm/test/CodeGen/AMDGPU/merge-image-load.mir
The file was modifiedllvm/lib/Target/AMDGPU/FLATInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/GCNSubtarget.h
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The file was modifiedllvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd.ll
The file was modifiedllvm/lib/ObjectYAML/ELFYAML.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
The file was modifiedllvm/lib/Target/AMDGPU/VOPInstructions.td
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The file was addedllvm/test/CodeGen/AMDGPU/agpr-csr.ll
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The file was modifiedclang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
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The file was modifiedllvm/lib/Target/AMDGPU/SIProgramInfo.h
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The file was modifiedllvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
The file was modifiedllvm/lib/Target/AMDGPU/GCNProcessors.td
The file was modifiedllvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
The file was modifiedllvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
The file was addedllvm/test/MC/AMDGPU/mimg-gfx90a.s
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The file was modifiedllvm/test/CodeGen/AMDGPU/limit-coalesce.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-overflow.mir
The file was modifiedclang/test/Driver/amdgpu-mcpu.cl
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The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIAddIMGInit.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
The file was addedllvm/test/CodeGen/MIR/AMDGPU/load-store-opt-scc.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
The file was modifiedclang/docs/ClangCommandLineReference.rst
The file was modifiedclang/test/Driver/cuda-bad-arch.cu
The file was addedllvm/test/CodeGen/AMDGPU/twoaddr-fma-f64.mir
The file was addedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
The file was addedllvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.fadd.ll
The file was modifiedclang/include/clang/Basic/Cuda.h
The file was modifiedllvm/lib/Support/TargetParser.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/sdwa-ops.mir
The file was addedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.gfx90a.ll
The file was modifiedllvm/test/MC/AMDGPU/vop_dpp.s
The file was addedllvm/test/CodeGen/AMDGPU/dpp64_combine.mir
The file was modifiedclang/lib/Basic/Targets/NVPTX.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
The file was addedllvm/test/CodeGen/AMDGPU/gfx90a-enc.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/s_code_end.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd-with-ret.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/hazard-inlineasm.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/mfma-loop.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
The file was modifiedllvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/syncscopes.ll
The file was modifiedllvm/test/tools/llvm-readobj/ELF/amdgpu-elf-headers.test
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
The file was modifiedllvm/test/Analysis/CostModel/AMDGPU/fadd.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/hazard-in-bundle.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/collapse-endcf2.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
The file was modifiedllvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/nsa-vmem-hazard.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir
The file was modifiedclang/test/Misc/target-invalid-cpu-note.c
The file was modifiedllvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
The file was modifiedllvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/insert-skips-flat-vmem.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.td
The file was modifiedllvm/test/CodeGen/AMDGPU/fma.f64.ll
The file was modifiedllvm/lib/Target/AMDGPU/BUFInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/memory_clause.mir
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/bundle-latency.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/wqm.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
The file was modifiedclang/lib/Basic/Cuda.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
The file was modifiedllvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
The file was addedllvm/test/CodeGen/AMDGPU/reserved-vgpr-tuples.mir
The file was modifiedllvm/lib/Target/AMDGPU/SISchedule.td
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-agpr.ll
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
Commit 0b5d2b0efd3eb9a6c1d454a7fc50942e906f522c by aheejin
[WebAssembly] Remove dependency of reference types from EH

The new spec does not have `exnref` so EH does not have dependency of
the reference types proposal anymore.

Reviewed By: dschuff

Differential Revision: https://reviews.llvm.org/D96903
The file was modifiedclang/lib/Driver/ToolChains/WebAssembly.cpp
The file was modifiedclang/test/Driver/wasm-toolchain.c
Commit 2f0f67afb24b81b22dc586440eae47a3e8ba3178 by thakis
[gn build] add a comment to the goma_dir arg
The file was modifiedllvm/utils/gn/build/toolchain/BUILD.gn
Commit d55d46f43bf68e4b28cbf0a50e28b2045b54e140 by tejohnson
[WPD] Add an optional checking mode for debugging devirtualization

This adds an internal option -wholeprogramdevirt-check which if enabled
will guard each devirtualization with a runtime check against the
expected target, and an invocation of a debug trap if the check fails.
This is useful for debugging WPD failures involving undefined behavior
(e.g. casting to another class type not in the inheritance chain).

Differential Revision: https://reviews.llvm.org/D95969
The file was modifiedllvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
The file was addedllvm/test/ThinLTO/X86/devirt_check.ll
Commit 48d2e04152366890e0b219a5f7c6f5b4905af480 by Stanislav.Mekhanoshin
[AMDGPU] Mark SMRD atomics

We did not have atomic flags on SMRD, did not copy TSFlags
to real instructions, and did not have ret/noret atomic map.

At the moment it is NFC, but needed for D96469.

Differential Revision: https://reviews.llvm.org/D96823
The file was modifiedllvm/lib/Target/AMDGPU/SMInstructions.td
Commit 2628e9146120507b2cf025f5c4ccc857cc3724c4 by joerg
[NetBSD] Use cortex-a8 as default CPU for ARMv7

This matches the platform default for GCC. It primarily matters when the
integrated assembler is not used as there is no default CPU defined for
ARMv7-A and GNU as is upset with -mcpu=generic.
The file was modifiedclang/test/Driver/netbsd.c
The file was modifiedllvm/lib/Support/Triple.cpp
Commit 78eabcaa48df72e01b352b4b5077cece0693950c by mvanotti
[libunwind] Add support for PC reg column in arm64

This change adds support for the dwarf PC register column in arm64, allowing
CFI directives to make use of it.

As of the last revision of the DWARF for ARM 64-bit architecture[0], the pc
register has been added as a valir register, with number 32.

This allows libunwinder to restore both pc and lr, which is useful
for stack switches and signal contexts.

[0]:
https://github.com/ARM-software/abi-aa/blob/f52e1ad3f81254497a83578dc102f6aac89e52d0/aadwarf64/aadwarf64.rst

Reviewed By: phosek, #libunwind

Differential Revision: https://reviews.llvm.org/D96901
The file was modifiedlibunwind/include/libunwind.h
The file was modifiedlibunwind/src/Registers.hpp
Commit 930150781da15f93811568760a60c7319de916b5 by eschweitz
[flang][fir][NFC] Merge tablegen files.

Differential Revision: https://reviews.llvm.org/D96908
The file was addedflang/include/flang/Optimizer/Dialect/FIRDialect.td
The file was modifiedflang/include/flang/Optimizer/Dialect/FIROps.td
The file was modifiedflang/include/flang/Optimizer/Dialect/FIRTypes.td
Commit 5517923b1cacf3e0ace438fd536b333940c3153d by czhengsz
[XCOFF][NFC] make csect properties optional for getXCOFFSection

We are going to support debug sections for XCOFF. So the csect
properties are not necessary. This patch makes these properties
optional.

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D95931
The file was modifiedllvm/include/llvm/MC/MCContext.h
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was modifiedllvm/include/llvm/BinaryFormat/XCOFF.h
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/lib/MC/MCObjectFileInfo.cpp
The file was modifiedllvm/lib/MC/MCContext.cpp
Commit fd3297dc32fab5c7a0a53efe71cf5c98cc365d50 by eschweitz
[flang][fir][NFC] clang-tidy change. Add include.

Differential Revision: https://reviews.llvm.org/D96912
The file was modifiedflang/include/flang/Optimizer/Dialect/FIROps.h
Commit 75997e84077451cff548901fd1637383a0d5515e by Stanislav.Mekhanoshin
[AMDGPU] Fixed msan build

LoadStoreOptimizer was using uninitialized SCC value for
instructions where it is unsupported.
The file was modifiedllvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
Commit 766ee1096f0b32616c3e96b7acddc293e56c16ef by kai.wang
[Clang][RISCV] Define RISC-V V builtin types

Add the types for the RISC-V V extension builtins.

These types will be used by the RISC-V V intrinsics which require
types of the form <vscale x 1 x i64>(LMUL=1 element size=64) or
<vscale x 4 x i32>(LMUL=2 element size=32), etc. The vector_size
attribute does not work for us as it doesn't create a scalable
vector type. We want these types to be opaque and have no operators
defined for them. We want them to be sizeless. This makes them
similar to the ARM SVE builtin types. But we will have quite a bit
more types. This patch adds around 60. Later patches will add
another 230 or so types representing tuples of these types similar
to the x2/x3/x4 types in ARM SVE. But with extra complexity that
these types are combined with the LMUL concept that is unique to
RISCV.

For more background see this RFC
http://lists.llvm.org/pipermail/llvm-dev/2020-October/145850.html

Authored-by: Roger Ferrer Ibanez <roger.ferrer@bsc.es>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

Differential Revision: https://reviews.llvm.org/D92715
The file was addedclang/include/clang/Basic/RISCVVTypes.def
The file was modifiedclang/lib/CodeGen/ItaniumCXXABI.cpp
The file was modifiedclang/lib/AST/ItaniumMangle.cpp
The file was modifiedclang/lib/Index/USRGeneration.cpp
The file was modifiedclang/lib/AST/Type.cpp
The file was modifiedclang/lib/Serialization/ASTReader.cpp
The file was modifiedclang/include/clang/Basic/TargetInfo.h
The file was modifiedclang/tools/libclang/CIndex.cpp
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/lib/AST/TypeLoc.cpp
The file was modifiedclang/lib/Serialization/ASTCommon.cpp
The file was modifiedclang/lib/AST/ExprConstant.cpp
The file was modifiedclang/lib/AST/MicrosoftMangle.cpp
The file was addedclang/test/Sema/riscv-types.c
The file was modifiedclang/include/clang/Serialization/ASTBitCodes.h
The file was modifiedclang/lib/Basic/TargetInfo.cpp
The file was modifiedclang/lib/CodeGen/CodeGenTypes.cpp
The file was modifiedclang/lib/Basic/Targets/RISCV.h
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
The file was modifiedclang/lib/AST/PrintfFormatString.cpp
The file was modifiedclang/include/clang/AST/ASTContext.h
The file was modifiedclang/lib/AST/ASTImporter.cpp
The file was modifiedclang/lib/Sema/Sema.cpp
The file was modifiedclang/include/clang/AST/TypeProperties.td
The file was modifiedclang/lib/AST/ASTContext.cpp
The file was modifiedclang/lib/AST/NSAPI.cpp
The file was addedclang/test/CodeGen/RISCV/riscv-v-debuginfo.c
The file was modifiedclang/include/clang/AST/Type.h
The file was modifiedclang/include/clang/module.modulemap
Commit ff6c84b803c6a7f5e79dcdbad25332dc7936303c by ajcbik
[mlir][sparse] generalize sparse storage format to many more types

Rationale:
Narrower types for overhead storage yield a smaller memory footprint for
sparse tensors and thus needs to be supported. Also, more value types
need to be supported to deal with all kinds of kernels. Since the
"one-size-fits-all" sparse storage scheme implementation is used
instead of actual codegen, the library needs to be able to support
all combinations of desired types. With some crafty templating and
overloading, the actual code for this is kept reasonably sized though.

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D96819
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/SparseLowering.cpp
The file was modifiedmlir/test/Dialect/Linalg/sparse_lower.mlir
The file was modifiedmlir/integration_test/Sparse/CPU/sparse_sum.mlir
The file was modifiedmlir/lib/ExecutionEngine/SparseUtils.cpp
The file was modifiedmlir/test/Dialect/Linalg/sparse_lower_calls.mlir
The file was addedmlir/integration_test/Sparse/CPU/sparse_sampled_matmul.mlir
Commit 00c4e0a8f60b73a92a319963e84bfc9fdeee5b19 by craig.topper
[RISCV] Guard the ISD::EXTRACT_VECTOR_ELT handling in ReplaceNodeResults against fixed vectors and non-MVT types.

The type legalizer is calling this code based on the scalar type so
we need to verify the input type is a scalable vector.

The vector type has also not been legalized yet when this is called
so we need to use EVT for it.
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit c3a3d200932347837283019a3870f185734f702d by jhuber6
[LV] Add analysis remark for mixed precision conversions

Floating point conversions inside vectorized loops have performance
implications but are very subtle. The user could specify a floating
point constant, or call a function without realizing that it will
force a change in the vector width. An example of this behaviour is
seen in https://godbolt.org/z/M3nT6c . The vectorizer should indicate
when this happens becuase it is most likely unintended behaviour.

This patch adds a simple check for this behaviour by following floating
point stores in the original loop and checking if a floating point
conversion operation occurs.

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D95539
The file was addedllvm/test/Transforms/LoopVectorize/mixed-precision-remarks.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp