SuccessChanges

Summary

  1. add -use-color option to clang-tidy-diff.py (details)
  2. [TableGen] Improve algorithms for processing template arguments (details)
  3. [NFC][RISCV] Use concise way to describe load/store instructions. (details)
  4. [RISCV] Fix bugs in pseudo instructions for masked segment load. (details)
  5. [PowerPC] Exploit the vinsw, vinsd, and vins[wd][lr]x instructions on P10 (details)
  6. Revert "[TableGen] Improve algorithms for processing template arguments" (details)
  7. [AMDGPU] Tidy up a FIXME fixed by D34973 (details)
  8. [lldb] Fix shared library directory computation on windows (details)
  9. [ARM] Expand the range of allowed post-incs in load/store optimizer (details)
  10. [SystemZ][ZOS] Guard using declaration for ::fchmodat (details)
  11. [ASTMatchers] Fix hasParent while ignoring unwritten nodes (details)
  12. [RISCV] Fix typo. Use ValueType instead of LLVMType. (details)
  13. [Verifier] add tests for vector reductions; NFC (details)
  14. Pass the cmdline aapcs bitfield options to cc1 (details)
  15. sysroot.py: add support for darwin (details)
  16. [clangd] Populate detail field in document symbols (details)
  17. [clang] functions with the 'const' or 'pure' attribute must always return. (details)
  18. [instcombine] Exploit UB implied by nofree attributes (details)
  19. [regalloc] Add a couple of dump routines for ease of debugging [NFC] (details)
  20. [AArch64] Allow folding FMUL/FADD into FMA for FP16 types (details)
  21. [TableGen][SelectionDAG] Improve efficiency of encoding negative immediates for isel's CheckInteger opcode. (details)
  22. [AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD (details)
  23. AMDGPU: Fix checks in llvm.amdgcn.workitem.id.ll (details)
  24. [gn build] fix mistake in 0ec448194e29 (details)
  25. libcxx: fix a documentation typo (details)
  26. [splitkit] Add a minor wrapper function for readability [NFC] (details)
  27. [RISCV] Support isel of scalable vector bitcasts (details)
  28. [RISCV] Add support for fixed vector sign/zero extend from mask types. (details)
Commit af06ff1cf87ecd387a65a6f7d4d00e0b06e983fb by aaron
add -use-color option to clang-tidy-diff.py

Clang-tidy seems to output color only when printing directly to
terminal, but an option to force color-output has been added in
https://reviews.llvm.org/D7947
The file was modifiedclang-tools-extra/clang-tidy/tool/clang-tidy-diff.py
Commit d248cce44e290b70a84495885559f41701422d2a by Paul C. Anagnostopoulos
[TableGen] Improve algorithms for processing template arguments

Rework template argument checking so that all arguments are type-checked
and cast if necessary.

Add a test.

Differential Revision: https://reviews.llvm.org/D96416
The file was modifiedllvm/docs/TableGen/ProgRef.rst
The file was modifiedllvm/test/TableGen/self-reference-typeerror.td
The file was addedllvm/test/TableGen/template-args.td
The file was modifiedllvm/lib/TableGen/Record.cpp
The file was modifiedllvm/lib/TableGen/TGParser.h
The file was modifiedllvm/include/llvm/TableGen/Record.h
The file was modifiedllvm/lib/TableGen/TGParser.cpp
Commit b97d8b32c32bd38ab5f7aa75a25dc31a9564fdc2 by kai.wang
[NFC][RISCV] Use concise way to describe load/store instructions.

Differential Revision: https://reviews.llvm.org/D96923
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
Commit f1efa8abaf8e4fac5ef37aeb10d607ceecdb4ece by kai.wang
[RISCV] Fix bugs in pseudo instructions for masked segment load.

For masked segment load, the destination register should not overlap
with mask register. It could not be V0.

In the original implementation, there is no segment load/store register
class without V0. In this patch, I added these register classes and
modify `GetVRegNoV0` to get the correct one.

Differential Revision: https://reviews.llvm.org/D96937
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Commit 34dc1ccb9606d1de7d4de7286fcc355fa8f7bcd7 by amy.kwan1
[PowerPC] Exploit the vinsw, vinsd, and vins[wd][lr]x instructions on P10

This patch generates the vinsw, vinsd, vinsblx, vinshlx, vinswlx, vinsdlx,
vinsbrx, vinshrx, vinswrx and vinsdrx instructions for vector insertion on P10.

Differential Revision: https://reviews.llvm.org/D94454
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
The file was modifiedllvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was addedllvm/test/CodeGen/PowerPC/vec_insert_elt.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td
Commit 49d663d5468c144eb7566e81a1a5f598f02a022b by Paul C. Anagnostopoulos
Revert "[TableGen] Improve algorithms for processing template arguments"

This reverts commit e589207d5aaee6cbf1d7c7de8867a17727d14aca.
The file was modifiedllvm/docs/TableGen/ProgRef.rst
The file was modifiedllvm/include/llvm/TableGen/Record.h
The file was modifiedllvm/lib/TableGen/TGParser.cpp
The file was modifiedllvm/lib/TableGen/Record.cpp
The file was removedllvm/test/TableGen/template-args.td
The file was modifiedllvm/test/TableGen/self-reference-typeerror.td
The file was modifiedllvm/lib/TableGen/TGParser.h
Commit e1b1119f21cb7718f80c1ba81318a6c288bac2e3 by jay.foad
[AMDGPU] Tidy up a FIXME fixed by D34973
The file was modifiedllvm/test/CodeGen/AMDGPU/v_cndmask.ll
Commit 004a264f8c923922ecd34255bcb10f4adaa27ac5 by pavel
[lldb] Fix shared library directory computation on windows

Our code for locating the shared library directory works via dladdr (or
the windows equivalent) to locate the path of an address known to reside
in liblldb. This works great for C++ programs, but there's a catch.

When (lib)lldb is used from python (like in our test suite), this dladdr
call will return a path to the _lldb.so (or such) file in the python
directory. To compensate for this, we have code which attempts to
resolve this symlink, to ensure we get the canonical location. However,
here's the second catch.

On windows, this file is not a symlink (but a copy), so this logic
fails. Since most of our other paths are derived from the liblldb
location, all of these paths will be wrong, when running the test suite.
One effect of this was the failure to find lldb-server in D96202.

To fix this issue, I add some windows-specific code to locate the
liblldb directory. Since it cannot rely on symlinks, it works by
manually walking the directory tree -- essentially doing the opposite of
what we do when computing the python directory.

To avoid python leaking back into the host code, I implement this with
the help of a callback which can be passed to HostInfo::Initialize in
order to assist with the directory location. The callback lives inside
the python plugin.

I also strenghten the existing path test to ensure the returned path is
the right one.

Differential Revision: https://reviews.llvm.org/D96779
The file was modifiedlldb/include/lldb/Host/linux/HostInfoLinux.h
The file was modifiedlldb/source/Host/linux/HostInfoLinux.cpp
The file was modifiedlldb/include/lldb/Host/HostInfoBase.h
The file was modifiedlldb/include/lldb/Initialization/SystemInitializerCommon.h
The file was modifiedlldb/source/Host/common/HostInfoBase.cpp
The file was modifiedlldb/test/API/functionalities/paths/TestPaths.py
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
The file was modifiedlldb/tools/lldb-test/SystemInitializerTest.cpp
The file was modifiedlldb/source/Initialization/SystemInitializerCommon.cpp
The file was modifiedlldb/include/lldb/Host/windows/HostInfoWindows.h
The file was modifiedlldb/source/API/SystemInitializerFull.cpp
The file was modifiedlldb/tools/lldb-server/SystemInitializerLLGS.h
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.h
The file was modifiedlldb/source/Host/windows/HostInfoWindows.cpp
Commit 3b34b06fc5908b4f7dc720c0655d5756bd8e2a28 by david.green
[ARM] Expand the range of allowed post-incs in load/store optimizer

Currently the load/store optimizer will only fold in increments of the
same size as the load/store. This patch expands that to any legal
immediate for the post-inc instruction.

Differential Revision: https://reviews.llvm.org/D95885
The file was modifiedllvm/test/CodeGen/Thumb2/mve-float32regloops.ll
The file was modifiedllvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.h
The file was modifiedllvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
Commit 25aa0d12445eed6e278489546d18fcb7a33cfaa6 by zibi
[SystemZ][ZOS] Guard using declaration for ::fchmodat

The use of fchmodat() is beeing guarded but its using declaration is not. Let's use the same guard in both places to avoid compiler errors on platforms where `fchmodat` does not exist.

Reviewed By: #libc, ldionne

Differential Revision: https://reviews.llvm.org/D96303
The file was modifiedlibcxx/src/filesystem/posix_compat.h
Commit e4d5f00093bec4099f1d0496181dc670c42ac220 by steveire
[ASTMatchers] Fix hasParent while ignoring unwritten nodes

For example, before this patch we can use has() to get from a
cxxRewrittenBinaryOperator to its operand, but hasParent doesn't get
back to the cxxRewrittenBinaryOperator.  This patch fixes that.

Differential Revision: https://reviews.llvm.org/D96113
The file was modifiedclang/lib/AST/ParentMapContext.cpp
The file was modifiedclang/include/clang/AST/ParentMapContext.h
The file was modifiedclang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
Commit 065a187f337f2a3204c69c2a73a65aad49a44be1 by kai.wang
[RISCV] Fix typo. Use ValueType instead of LLVMType.
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
Commit a1e5388a7ca1d0d46ed84ac2dedf52ade7ac8200 by spatel
[Verifier] add tests for vector reductions; NFC

Checking existing functionality before D96904.
The file was addedllvm/test/Verifier/reduction-intrinsics.ll
Commit 5f7715d8780a1d16ad023995d282a7d94cb923a9 by ties.stuij
Pass the cmdline aapcs bitfield options to cc1

The following commits added commandline arguments to control following the Arm
Procedure Call Standard for certain volatile bitfield operations:
- https://reviews.llvm.org/D67399
- https://reviews.llvm.org/D72932

This commit fixes the oversight that these args weren't passed from the driver
to cc1 if appropriate.

Where *appropriate* means:
- `-faapcs-bitfield-width`: is the default, so won't be passed
- `-fno-aapcs-bitfield-width`: should be passed
- `-faapcs-bitfield-load`: should be passed

Differential Revision: https://reviews.llvm.org/D96784
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was addedclang/test/Driver/arm-aarch64-bitfield-flags.c
Commit 0ec448194e2928a3d1dc2eceeb764c6e19bcec3e by thakis
sysroot.py: add support for darwin

This is a tiny bit messy because compiler-rt needs different sysroots for
macOS, iOS, etc. We want sysroot.py to create something that is a hermetic
representation of all build deps, so it needs to create a directory that
contains all needed SDKs, and these subdirectories are then passed to
cmake which passes each of these _subdirectories_ as different -isysroot
flags while building the runtime libraries.

Differential Revision: https://reviews.llvm.org/D96958
The file was modifiedllvm/utils/sysroot.py
The file was modifiedllvm/utils/gn/secondary/compiler-rt/BUILD.gn
The file was modifiedllvm/utils/gn/build/BUILD.gn
The file was modifiedllvm/utils/gn/build/mac_sdk.gni
Commit 2e851c4172a35cc37fe6bf4ce8150c628fd66c0c by sam.mccall
[clangd] Populate detail field in document symbols

This commit fix https://github.com/clangd/clangd/issues/520 and https://github.com/clangd/clangd/issues/601.
{F15544293}

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D96751
The file was modifiedclang-tools-extra/clangd/unittests/FindSymbolsTests.cpp
The file was modifiedclang-tools-extra/clangd/test/symbols.test
The file was modifiedclang-tools-extra/clangd/FindSymbols.cpp
Commit 46757ccb49ab88da54ca8ddd43665d5255ee80f7 by jeroen.dobbelaere
[clang] functions with the 'const' or 'pure' attribute must always return.

As described in
* https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-pure-function-attribute
* https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-const-function-attribute

An `__attribute__((pure))` function must always return, as well as an `__attribute__((const))` function.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D96960
The file was modifiedclang/test/CodeGenCXX/2009-05-04-PureConstNounwind.cpp
The file was modifiedclang/test/Sema/libbuiltins-ctype-powerpc64.c
The file was modifiedclang/test/Sema/libbuiltins-ctype-x86_64.c
The file was modifiedclang/test/CodeGen/complex-libcalls.c
The file was modifiedclang/test/CodeGen/complex-builtins.c
The file was modifiedclang/lib/CodeGen/CGCall.cpp
The file was modifiedclang/test/CodeGen/function-attributes.c
Commit 86664638898e9c3756ad17d612de1873fead6813 by listmail
[instcombine] Exploit UB implied by nofree attributes

This patch simply implements the documented UB of the current nofree attributes as specified. It doesn't try to be fancy about inference (yet), it just implements the cases already specified and inferred.

Note: When this lands, it may expose miscompiles. If so, please revert and provide a test case. It's likely the bug is in the existing inference code and without a relatively complete test case, it will be hard to debug.

Differential Revision: https://reviews.llvm.org/D96349
The file was modifiedllvm/test/Transforms/InstCombine/malloc-free-delete.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp
Commit 1dfb06d0b40e875d524b2b43fc95ce81a41ce014 by listmail
[regalloc] Add a couple of dump routines for ease of debugging [NFC]
The file was modifiedllvm/lib/CodeGen/SpillPlacement.cpp
The file was modifiedllvm/lib/CodeGen/SplitKit.cpp
The file was modifiedllvm/lib/CodeGen/SplitKit.h
The file was modifiedllvm/lib/CodeGen/SpillPlacement.h
Commit 5b094bfeb3ccaf3ba118f161277ade9fc5147272 by bradley.smith
[AArch64] Allow folding FMUL/FADD into FMA for FP16 types

isFMAFasterThanFMulAndFAdd should return true for FP16 types when
HasFullFP16 is present, since we have the instructions to handle it for
both SVE and NEON. (SVE patterns and tests will follow).

Differential Revision: https://reviews.llvm.org/D96599
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/f16-instructions.ll
Commit 61d4d9a5d33505727afe52f524b90943f8caf21e by craig.topper
[TableGen][SelectionDAG] Improve efficiency of encoding negative immediates for isel's CheckInteger opcode.

CheckInteger uses an int64_t encoded using a variable width encoding
that is optimized for encoding a number with a lot of leading zeros.
Negative numbers have no leading zeros so use the largest encoding
requiring 9 bytes.

I believe its most like we want to check for positive and negative
numbers near 0. -1 is quite common due to its use in the 'not'
idiom.

To optimize for this, we can borrow an idea from the bitcode format
and move the sign bit to bit 0 with the magnitude stored in the
upper bits. This will drastically increase the number of leading
zeros for small magnitudes. Then we can run this value through
VBR encoding.

This gives a small reduction in the table size on all in tree
targets except VE where size increased by about 300 bytes due
to intrinsic ids now requiring 3 bytes instead of 2. Since the
intrinsic enum space is shared by all targets this an unfortunate
consquence of where VE is currently located in the range.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D96317
The file was modifiedllvm/test/TableGen/dag-isel-regclass-emit-enum.td
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
The file was modifiedllvm/test/TableGen/dag-isel-subregs.td
The file was modifiedllvm/utils/TableGen/DAGISelMatcherEmitter.cpp
Commit 8bad8a43c339729bf722d519c3a25708a54bc205 by bradley.smith
[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD

Adjust generateFMAsInMachineCombiner to return false if SVE is present
in order to combine fmul+fadd into fma. Also add new pseudo instructions
so as to select the most appropriate of FMLA/FMAD depending on register
allocation.

Depends on D96599

Differential Revision: https://reviews.llvm.org/D96424
The file was modifiedllvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was addedllvm/test/CodeGen/AArch64/sve-fp-combine.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fp.ll
Commit 622652bf735c82869ff9d51897deacc8e6511e5a by kzhuravl_dev
AMDGPU: Fix checks in llvm.amdgcn.workitem.id.ll

Differential Revision: https://reviews.llvm.org/D96967
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
Commit c9c17144c1e270f4a8f6454aaabbe825a7c3cbc4 by thakis
[gn build] fix mistake in 0ec448194e29
The file was modifiedllvm/utils/gn/build/mac_sdk.gni
Commit 9d36f70ef28a1e6bba763b40c9c49a76c520a56e by thakis
libcxx: fix a documentation typo

See `grep 'option.LIBCXX_INCLUDE_TESTS' libcxx/CMakeLists.txt`.
The file was modifiedlibcxx/docs/BuildingLibcxx.rst
Commit 5318d9e5165a6e7f10c602ab85cb24ed2dfceed4 by listmail
[splitkit] Add a minor wrapper function for readability [NFC]
The file was modifiedllvm/lib/CodeGen/SplitKit.h
The file was modifiedllvm/lib/CodeGen/SplitKit.cpp
Commit c7dd92e8a590cd456b4daad87af9d3b746d05ca6 by craig.topper
[RISCV] Support isel of scalable vector bitcasts

These should be NOPs so we can just replace with the input. This
matches what SVE does with isel patterns for all permutations.
Custom isel saves us from having to list all permurations for
all LMULs.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D96921
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat-rv32.ll
Commit 792627be359e5d3386c4d8bb97eb1e5e5ec43b0c by craig.topper
[RISCV] Add support for fixed vector sign/zero extend from mask types.

Due to vXi64 on RV32, I've directly emitted this using _VL ISD
opcodes. If it wasn't for that we could just use fixed vector
BUILD_VECTOR and VSELECT and let those each be legalized.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D96910
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp