SuccessChanges

Summary

  1. [TableGen] Use ListSeparator (NFC) (details)
  2. [Support] Use static_assert instead of assert (NFC) (details)
  3. [CodeGen] Use range-based for loops (NFC) (details)
  4. [RISCV] Prune unneeded indexed load/store pseudo instructions. (details)
  5. [mlir][sparse] assert fail on mismatch between rank and annotations array (details)
  6. LanguageRuntime can provide an UnwindPlan for special occasions (details)
  7. Reland "[Debugify] Make the debugify aware of the original (-g) Debug Info" (details)
  8. [mlir] Better support for rank-reducing subview / subtensor type inference. (details)
  9. [NPM][LTO] Do not enable MemorySSA with LoopFullUnrollPass (details)
  10. [debuginfo-tests] Recommit test sret.cpp (details)
  11. [llvm-exegesis] [PowerPC] Add basic LIT test (details)
  12. [llvm-exegesis] Ignore instructions using custom inserter (details)
  13. [AArch64] Add some missing Neoverse features (details)
  14. [X86] Fix a codegen crash in getSetCCResultType (details)
  15. [docs] Fix the GlobalISel/GenericOpcode.rst (details)
  16. [mlir] Add a TensorLoadToMemref canonicalization (details)
Commit 744a96afed9edcfec6143113ef6a8e442989b667 by kazu
[TableGen] Use ListSeparator (NFC)
The file was modifiedllvm/utils/TableGen/DFAEmitter.cpp
Commit 2d5eb67235c763898f7c3327fb97b1ae1307d8e4 by kazu
[Support] Use static_assert instead of assert (NFC)

Identified with misc-static-assert.
The file was modifiedllvm/lib/Support/SHA256.cpp
Commit fd04f3a30cbb6506aea1ef0b104ab707c4331241 by kazu
[CodeGen] Use range-based for loops (NFC)
The file was modifiedllvm/lib/CodeGen/RegAllocPBQP.cpp
The file was modifiedllvm/lib/CodeGen/TwoAddressInstructionPass.cpp
The file was modifiedllvm/lib/CodeGen/SpillPlacement.cpp
The file was modifiedllvm/lib/CodeGen/StackSlotColoring.cpp
The file was modifiedllvm/lib/CodeGen/RegisterScavenging.cpp
The file was modifiedllvm/lib/CodeGen/ShadowStackGCLowering.cpp
The file was modifiedllvm/lib/CodeGen/SlotIndexes.cpp
The file was modifiedllvm/lib/CodeGen/RegisterCoalescer.cpp
The file was modifiedllvm/lib/CodeGen/SplitKit.cpp
Commit cd4051ac802fdc5664a3432f57d99bbcb4c07a92 by craig.topper
[RISCV] Prune unneeded indexed load/store pseudo instructions.

We were creating more combinations of value and index lmul than
we needed.

I've copied the loop structure used here from VPseudoAMOEI with
all data sew values instead of just 32/64.

Similar can be done for segment loads/store.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D97008
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Commit 2556d622828ae5631ac483d82592440fa1910d80 by ajcbik
[mlir][sparse] assert fail on mismatch between rank and annotations array

Rationale:
Providing the wrong number of sparse/dense annotations was silently
ignored or caused unrelated crashes. This minor change verifies that
the provided number matches the rank.

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D97034
The file was modifiedmlir/lib/ExecutionEngine/SparseUtils.cpp
Commit d82ecb0ac72261189ec3a5dccd3ad55aeafe07b4 by Jason Molenda
LanguageRuntime can provide an UnwindPlan for special occasions

Add a facility in the LanguageRuntime to provide a special
UnwindPlan based on the register values in a RegisterContext,
instead of using the return-pc to find a function and use its
normal UnwindPlans.

Needed when the runtime has special stack frames that we want
to show the user, but aren't actually on the real stack.
Specifically for Swift asynchronous functions.

With feedback from Greg Clayton, Jonas Devlieghere, Dave Lee

<rdar://problem/70398009>

Differential Revision: https://reviews.llvm.org/D96839
The file was modifiedlldb/source/Target/LanguageRuntime.cpp
The file was modifiedlldb/include/lldb/Target/LanguageRuntime.h
The file was modifiedlldb/source/Target/RegisterContextUnwind.cpp
Commit 1a2b3536efef20f12c44201c2834a383b7c5c4c2 by djtodoro
Reland "[Debugify] Make the debugify aware of the original (-g) Debug Info"

    As discussed on the RFC [0], I am sharing the set of patches that
    enables checking of original Debug Info metadata preservation in
    optimizations. The proof-of-concept/proposal can be found at [1].

    The implementation from the [1] was full of duplicated code,
    so this set of patches tries to merge this approach into the existing
    debugify utility.

    For example, the utility pass in the original-debuginfo-check
    mode could be invoked as follows:

      $ opt -verify-debuginfo-preserve -pass-to-test sample.ll

    Since this is very initial stage of the implementation,
    there is a space for improvements such as:
      - Add support for the new pass manager
      - Add support for metadata other than DILocations and DISubprograms

    [0] https://groups.google.com/forum/#!msg/llvm-dev/QOyF-38YPlE/G213uiuwCAAJ
    [1] https://github.com/djolertrk/llvm-di-checker

    Differential Revision: https://reviews.llvm.org/D82545

The test that was failing is now forced to use the old PM.
The file was modifiedllvm/lib/Transforms/Utils/Debugify.cpp
The file was modifiedllvm/unittests/Transforms/Utils/CMakeLists.txt
The file was addedllvm/unittests/Transforms/Utils/DebugifyTest.cpp
The file was modifiedllvm/docs/HowToUpdateDebugInfo.rst
The file was modifiedllvm/include/llvm/Transforms/Utils/Debugify.h
The file was addedllvm/test/DebugInfo/debugify-original-no-dbg-info.ll
The file was modifiedllvm/tools/opt/opt.cpp
Commit b3c227a25a231248e3752918c2cac1a7b9414ef1 by nicolas.vasilache
[mlir] Better support for rank-reducing subview / subtensor type inference.

Differential Revision: https://reviews.llvm.org/D96995
The file was modifiedmlir/test/Dialect/Standard/canonicalize.mlir
The file was modifiedmlir/test/Transforms/canonicalize.mlir
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
Commit c141c6551be64f220b71786d24e98f6de906e6de by david.green
[NPM][LTO] Do not enable MemorySSA with LoopFullUnrollPass

As with the standard opt pipeline, we disable the MemorySSA dependency
in the LTO LPM pipeline as not all passes preserve MemorySSA.
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
Commit 54b6d01685ef3b3bce4f0b1e9262291a9d535725 by orlando.hyams
[debuginfo-tests] Recommit test sret.cpp

This test was accidently removed when the directory structure was shuffled
around for dexter in f78c236efda8.

Reviewed By: aprantl

Differential Revision: https://reviews.llvm.org/D96968
The file was addeddebuginfo-tests/llgdb-tests/sret.cpp
Commit d7d4dca15fdaecd368978067fb26d64e96744cb9 by qiucofan
[llvm-exegesis] [PowerPC] Add basic LIT test

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D94897
The file was addedllvm/test/tools/llvm-exegesis/PowerPC/lit.local.cfg
The file was addedllvm/test/tools/llvm-exegesis/PowerPC/latency-by-opcode-name.s
Commit 9d2f06445ffaceb501abd9477d3b5ce7231af49d by qiucofan
[llvm-exegesis] Ignore instructions using custom inserter

Some instructions defined in table-gen files sets usesCustomInserter
bit, which means it has to be lowered by target code and isn't actually
valid instruction at MC level. So we should treat them like pseudo
instructions.

Reviewed By: gchatelet

Differential Revision: https://reviews.llvm.org/D94898
The file was addedllvm/test/tools/llvm-exegesis/PowerPC/unsupported-opcode.s
The file was modifiedllvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp
The file was modifiedllvm/tools/llvm-exegesis/llvm-exegesis.cpp
Commit 260f90bb3d1aef90764de3506f86dedd1339e37c by sjoerd.meijer
[AArch64] Add some missing Neoverse features

This enables AES fusion and the post RA scheduler for the Neoverse cores.
And while we are it also for the A55 that we had missed earlier.

Differential Revision: https://reviews.llvm.org/D96866
The file was modifiedllvm/lib/Target/AArch64/AArch64.td
The file was modifiedllvm/test/CodeGen/AArch64/misched-fusion-aes.ll
The file was modifiedclang/test/Driver/aarch64-cpus.c
Commit c98644c2ece2f00da5e4510d6fbd07ef89263220 by pengfei.wang
[X86] Fix a codegen crash in getSetCCResultType

This patch fixes some crashes coming from
X86ISelLowering::getSetCCResultType, which would occasionally return
an EVT constructed from an invalid MVT, which has a null Type pointer.

This patch refers to D95434.

Differential Revision: https://reviews.llvm.org/D97036
The file was addedllvm/test/CodeGen/X86/vec3-setcc-crash.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 0d829802969fc455c41ee27ec08fb1f8db1321d9 by djolertrk
[docs] Fix the GlobalISel/GenericOpcode.rst

This couses docs build to fail.
Introduced with D96890.
The file was modifiedllvm/docs/GlobalISel/GenericOpcode.rst
Commit d12fa33d736d60d419f86b4ec5f3e77e602d4b1e by nicolas.vasilache
[mlir] Add a TensorLoadToMemref canonicalization

A folder of `tensor_load + tensor_to_memref` exists but it only applies when
source and destination memref types are the same.

This revision adds a canonicalize `tensor_load + tensor_to_memref` to `memref_cast`
when type mismatches prevent folding to kick in.

Differential Revision: https://reviews.llvm.org/D97038
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/test/Dialect/Standard/canonicalize.mlir