SuccessChanges

Summary

  1. [LV] Remove VPCallback. (details)
  2. Revert "[ARM] Expand the range of allowed post-incs in load/store optimizer" (details)
  3. [lldb/Commands] Fix help text typo for 'breakpoint set' -a|--address. (details)
  4. [llvm-dwarfdump][locstats] Unify handling of inlined vars with no loc (details)
  5. [mlir][Linalg] NFC - Expose more options to the CodegenStrategy (details)
  6. [DAG] visitTRUNCATE - attempt to truncate USUBSAT (details)
  7. [AMDGPU] Add some GFX9 test coverage. NFC. (details)
  8. [ARM] Correct vector predicate type in MVE getCmpSelInstrCost (details)
  9. Make fixed-abi default for AMD HSA OS (details)
Commit edc92a1c42590a1fb5e852cea6ffbc253e5e0a7f by flo
[LV] Remove VPCallback.

Now that all state for generated instructions is managed directly in
VPTransformState, VPCallBack is no longer needed. This patch updates the
last use of `getOrCreateScalarValue` to instead manage the value
directly in VPTransformState and removes VPCallback.

Reviewed By: gilr

Differential Revision: https://reviews.llvm.org/D95383
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
Commit 7a5c26e99afab1a79fc6777fc424510ce4caec9f by david.green
Revert "[ARM] Expand the range of allowed post-incs in load/store optimizer"

This reverts commit 3b34b06fc5908b4f7dc720c0655d5756bd8e2a28 as runtime
errors were reported.
The file was modifiedllvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
The file was modifiedllvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-float32regloops.ll
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.h
Commit 08331281af7bebf76d541cfb33d01dca22ed4d79 by jan.kratochvil
[lldb/Commands] Fix help text typo for 'breakpoint set' -a|--address.
The file was modifiedlldb/source/Commands/Options.td
Commit b6db47d7e044730dc3c9b35dae6697eee0885dbf by djtodoro
[llvm-dwarfdump][locstats] Unify handling of inlined vars with no loc

The presence or absence of an inline variable (as well as formal
parameter) with only an abstract_origin ref (without DW_AT_location)
should not change the location coverage.

It means, for both:

DW_TAG_inlined_subroutine
  DW_AT_abstract_origin (0x0000004e "f")
  DW_AT_low_pc  (0x0000000000000010)
  DW_AT_high_pc (0x0000000000000013)
  DW_TAG_formal_parameter
    DW_AT_abstract_origin       (0x0000005a "b")

and,

DW_TAG_inlined_subroutine
   DW_AT_abstract_origin (0x0000004e "f")
   DW_AT_low_pc  (0x0000000000000010)
   DW_AT_high_pc (0x0000000000000013)

we should report 0% location coverage. If we add DW_AT_location,
for both cases the coverage should be improved.

Differential Revision: https://reviews.llvm.org/D96045
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/statistics-dwo.test
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/statistics.ll
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/stats-scope-bytes-covered.yaml
The file was modifiedllvm/tools/llvm-dwarfdump/Statistics.cpp
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/statistics-v3.test
The file was addedllvm/test/tools/llvm-dwarfdump/X86/locstats-for-inlined-vars.yaml
Commit 62f5c46eecf8d356b76e840fb6cab09360f25f76 by nicolas.vasilache
[mlir][Linalg] NFC - Expose more options to the CodegenStrategy
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/CodegenStrategy.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/CodegenStrategy.h
Commit 5d3930bb8feb2c0c6abc1a6ea73a8fbf00c8bfb9 by llvm-dev
[DAG] visitTRUNCATE - attempt to truncate USUBSAT

Fold trunc(usubsat(zext(x),y)) -> usubsat(x,trunc(umin(y,satlimit)))
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/X86/combine-sub-usat.ll
Commit b2c7f06db1d0892a22c4c159383ca40c533d9244 by jay.foad
[AMDGPU] Add some GFX9 test coverage. NFC.
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
Commit a1c34a9d6a5cbb25826455f67d98c2099d27391c by david.green
[ARM] Correct vector predicate type in MVE getCmpSelInstrCost
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
Commit 3c297a256442fb8363e70ed80407018cded0fcd4 by Madhur.Amilkanthwar
Make fixed-abi default for AMD HSA OS

fixed-abi uses pre-defined and predictable
SGPR/VGPRs for passing arguments. This patch makes
this scheme default when HSA OS is specified in triple.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D96340
The file was modifiedllvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/call-constexpr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sibling-call.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/ipra.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/addrspacecast.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/call-argument-types.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fdiv-nofpexcept.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/need-fp-from-csr-vgpr-spill.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-non-entry-func.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/reserve-vgpr-for-sgpr-spill.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/call-waitcnt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/cc-update.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/agpr-register-count.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wave32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/stack-realign.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll

Summary

  1. [test-suite] SPEC2017 CPU ROMS floating point tests. (details)
Commit 0e6fde52a15cf7d75733bac87329ebec0a28296b by naromero
[test-suite] SPEC2017 CPU ROMS floating point tests.

  - ~~Helper macro for managing intermediate dependencies on Fortran modules.~~
  - Add SPEC2017 CPU ROMS floating point tests.
  - Emit warning message about using recent Ninja version.

Reviewed By: Meinersbur

Differential Revision: https://reviews.llvm.org/D96746
The file was modifiedCMakeLists.txt (diff)
The file was addedExternal/SPEC/CFP2017speed/654.roms_s/CMakeLists.txt
The file was modifiedExternal/SPEC/CFP2017speed/CMakeLists.txt (diff)
The file was modifiedExternal/SPEC/CFP2017rate/CMakeLists.txt (diff)
The file was addedExternal/SPEC/CFP2017rate/554.roms_r/CMakeLists.txt