1. [NFC][Regalloc] Share the VirtRegAuxInfo object with LiveRangeEdit (details)
  2. [OpenMP] Fix always,from and delete for data absent at exit (details)
  3. [OpenMP] Fix nvptx CUDA_VERSION conversion (details)
  4. [libc++] Turn off clang-format for auto-generated version header. NFC. (details)
  5. [SCEV] Use both known bits and sign bits when computing range of SCEV unknowns (details)
  6. Hwasan InitPrctl check for error using internal_iserror (details)
  7. [MemCopyOpt] Enable MemorySSA by default (details)
  8. [LV] Fold single-use variable into assert. NFC. (details)
  9. [MLIR] Delete unused functions getCollapsedInitTensor and getExpandedInitTensor (details)
  10. [mlir] Add folding of tensor.cast -> subtensor_insert (details)
  11. [AArch64][GlobalISel] Run redundant_sext_inreg in the post-legalizer combiner (details)
  12. [Sanitizer][NFC] Fix typo (details)
  13. [CUDA] fix builtin constraints for PTX 7.2 (details)
  14. [SampleFDO] Add PromotedInsns to prevent repeated ICP. (details)
  15. [RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64 (details)
  16. [RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics. (details)
Commit 82492f24ffa74825cc7990aa7e06b6b0b8c32e81 by mtrofin
[NFC][Regalloc] Share the VirtRegAuxInfo object with LiveRangeEdit

VirtRegAuxInfo is an extensibility point, so the register allocator's
decision on which implementation to use should be communicated to the
other users - namely, LiveRangeEdit.

Differential Revision:
The file was modifiedllvm/lib/CodeGen/RegAllocBasic.cpp
The file was modifiedllvm/include/llvm/CodeGen/Spiller.h
The file was modifiedllvm/lib/CodeGen/SplitKit.cpp
The file was modifiedllvm/lib/CodeGen/SplitKit.h
The file was modifiedllvm/lib/CodeGen/RegAllocPBQP.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocGreedy.cpp
The file was modifiedllvm/include/llvm/CodeGen/LiveRangeEdit.h
The file was modifiedllvm/lib/CodeGen/LiveRangeEdit.cpp
The file was modifiedllvm/lib/CodeGen/InlineSpiller.cpp
Commit d2147b1a876187e6addd89b681d47f9f98a89669 by jdenny.ornl
[OpenMP] Fix always,from and delete for data absent at exit

Without this patch, there's a runtime error for those map types at
exit from an "omp target data" or at "omp target exit data", but the
spec says the list item should be ignored.

This patch tests that fix in data_absent_at_exit.c, and it also
improves other testing for data that is not fully present at exit.

Reviewed By: grokos, RaviNarayanaswamy

Differential Revision:
The file was addedopenmp/libomptarget/test/mapping/present/target_exit_data_delete.c
The file was removedopenmp/libomptarget/test/mapping/present/target_exit_data.c
The file was modifiedopenmp/libomptarget/src/omptarget.cpp
The file was addedopenmp/libomptarget/test/mapping/data_absent_at_exit.c
The file was modifiedopenmp/libomptarget/test/mapping/target_data_array_extension_at_exit.c
The file was addedopenmp/libomptarget/test/mapping/present/target_exit_data_release.c
Commit ef8b3b5ffd562955fbb78c72c7820cd9cd99d313 by jdenny.ornl
[OpenMP] Fix nvptx CUDA_VERSION conversion

As mentioned in PR#49250, without this patch, ptxas for CUDA 9.1 fails
in the following two tests:

- openmp/libomptarget/test/mapping/lambda_mapping.cpp
- openmp/libomptarget/test/offloading/bug49021.cpp

The error looks like:

ptxas /tmp/lambda_mapping-081ea9.s, line 828; error   : Not a name of any known instruction: 'activemask'

The problem is that our cmake script converts CUDA version strings
incorrectly: 9.1 becomes 9100, but it should be 9010, as shown in
`getCudaVersion` in `clang/lib/Driver/ToolChains/Cuda.cpp`.  Thus,
inadvertently enables `activemask` because it apparently becomes
available in 9.2.  This patch fixes the conversion.

This patch does not fix the other two tests in PR#49250.

Reviewed By: tianshilei1992

Differential Revision:
The file was modifiedopenmp/libomptarget/deviceRTLs/nvptx/CMakeLists.txt
Commit bcb5a124aea8ecba090ffe2815e357480830d53b by marek
[libc++] Turn off clang-format for auto-generated version header. NFC.
The file was modifiedlibcxx/include/version
The file was modifiedlibcxx/utils/
Commit 4a5edea1930ddbcd3af46827f6cc976cc1b30e2a by listmail
[SCEV] Use both known bits and sign bits when computing range of SCEV unknowns

When computing a range for a SCEVUnknown, today we use computeKnownBits for unsigned ranges, and computeNumSignBots for signed ranges. This means we miss opportunities to improve range results.

One common missed pattern is that we have a signed range of a value which CKB can determine is positive, but CNSB doesn't convey that information. The current range includes the negative part, and is thus double the size.

Per the removed comment, the original concern which delayed using both (after some code merging years back) was a compile time concern. CTMark results (provided by Nikita, thanks!) showed a geomean impact of about 0.1%. This doesn't seem large enough to avoid higher quality results.

Differential Revision:
The file was modifiedllvm/test/Analysis/ScalarEvolution/extract-highbits-sameconstmask.ll
The file was modifiedllvm/test/Analysis/ScalarEvolution/add-expr-pointer-operand-sorting.ll
The file was modifiedllvm/test/Analysis/ScalarEvolution/ranges.ll
The file was modifiedllvm/test/Analysis/ScalarEvolution/max-be-count-not-constant.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/scev-custom-dl.ll
The file was modifiedllvm/test/Analysis/ScalarEvolution/ptrtoint.ll
The file was modifiedllvm/test/Analysis/ScalarEvolution/increasing-or-decreasing-iv.ll
The file was modifiedllvm/test/Analysis/ScalarEvolution/sext-to-zext.ll
The file was modifiedllvm/test/Analysis/ScalarEvolution/ashr.ll
The file was modifiedllvm/test/Analysis/StackSafetyAnalysis/memintrin.ll
The file was modifiedllvm/test/Analysis/ScalarEvolution/ptrtoint-constantexpr-loop.ll
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was modifiedllvm/test/Analysis/StackSafetyAnalysis/local.ll
Commit c1653b8cc7bd8e7e3168089b6c6dad0aa4b6fdd6 by matthew.malcomson
Hwasan InitPrctl check for error using internal_iserror

When adding this function in I did not
notice that internal_prctl has the API of the syscall to prctl rather
than the API of the glibc (posix) wrapper.

This means that the error return value is not necessarily -1 and that
errno is not set by the call.

For InitPrctl this means that the checks do not catch running on a
kernel *without* the required ABI (not caught since I only tested this
function correctly enables the ABI when it exists).
This commit updates the two calls which check for an error condition to
use internal_iserror. That function sets a provided integer to an
equivalent errno value and returns a boolean to indicate success or not.

Tested by running on a kernel that has this ABI and on one that does
not. Verified that running on the kernel without this ABI the current
code prints the provided error message and does not attempt to run the
program. Verified that running on the kernel with this ABI the current
code does not print an error message and turns on the ABI.
This done on an x86 kernel (where the ABI does not exist), an AArch64
kernel without this ABI, and an AArch64 kernel with this ABI.

In order to keep running the testsuite on kernels that do not provide
this new ABI we add another option to the HWASAN_OPTIONS environment
variable, this option determines whether the library kills the process
if it fails to enable the relaxed syscall ABI or not.
This new flag is `fail_without_syscall_abi`.
The check-hwasan testsuite results do not change with this patch on
either x86, AArch64 without a kernel supporting this ABI, and AArch64
with a kernel supporting this ABI.

Differential Revision:
The file was modifiedcompiler-rt/test/hwasan/
The file was modifiedcompiler-rt/lib/hwasan/hwasan_linux.cpp
The file was modifiedcompiler-rt/lib/hwasan/
Commit 71a8e4e7d6b947c8b954ec0763ff7969b3879d7b by nikita.ppv
[MemCopyOpt] Enable MemorySSA by default

This enables use of MemorySSA instead of MemDep in MemCpyOpt. To
allow this without significant compile-time impact, the MemCpyOpt
pass is moved directly before DSE (in the cases where this was not
already the case), which allows us to reuse the existing MemorySSA

Unlike the MemDep-based implementation, the MemorySSA-based MemCpyOpt
can also perform simple optimizations across basic blocks.

Differential Revision:
The file was modifiedllvm/lib/Transforms/IPO/PassManagerBuilder.cpp
The file was modifiedllvm/test/Other/opt-Os-pipeline.ll
The file was modifiedllvm/test/Other/new-pm-defaults.ll
The file was modifiedllvm/test/Analysis/BasicAA/phi-values-usage.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/opt-pipeline.ll
The file was modifiedllvm/test/Other/opt-LTO-pipeline.ll
The file was modifiedllvm/test/Other/opt-O3-pipeline.ll
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/test/Other/opt-O3-pipeline-enable-matrix.ll
The file was modifiedllvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
The file was modifiedclang/test/CodeGen/thinlto-distributed-newpm.ll
The file was modifiedllvm/test/Other/new-pm-lto-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
The file was modifiedllvm/test/Other/opt-O2-pipeline.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
Commit 59f442e6bb7314d8efad1a8e7d9c84f29a873be6 by benny.kra
[LV] Fold single-use variable into assert. NFC.
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
Commit 236aab0b0c9c0c98bec7175072721fc15e247231 by gcmn
[MLIR] Delete unused functions getCollapsedInitTensor and getExpandedInitTensor

These are unused since

Reviewed By: nicolasvasilache

Differential Revision:
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
Commit 0ee4bf151c0985027e82ec0036a655d68b4d6c37 by nicolas.vasilache
[mlir] Add folding of tensor.cast -> subtensor_insert

Differential Revision:
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
The file was modifiedmlir/include/mlir/Dialect/Tensor/IR/Tensor.h
The file was modifiedmlir/test/Dialect/Standard/canonicalize.mlir
The file was modifiedmlir/lib/Dialect/Tensor/IR/TensorOps.cpp
Commit 8d3442eddb88e2e52bee89f333df0c6cf12e1237 by Jessica Paquette
[AArch64][GlobalISel] Run redundant_sext_inreg in the post-legalizer combiner

This is to ensure that we can eliminate G_ASSERT_SEXT.

In a follow-up patch, I'm going to make CallLowering emit G_ASSERT_SEXT for
signext parameters.

Differential Revision:
The file was modifiedllvm/lib/Target/AArch64/
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-redundant-sextinreg.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/combine-sext-trunc-sextload.mir
Commit 43fa23a01f0a82c42c348c0c02982900ffba1207 by luismarques
[Sanitizer][NFC] Fix typo
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_primary64.h
Commit 1a368ae3b78dd7a364e8f17658fddaf86b1e98db by rupprecht
[CUDA] fix builtin constraints for PTX 7.2

This fixes build issues w/ CUDA-11 introduced by

Reviewed By: yaxunl

Differential Revision:
The file was modifiedclang/include/clang/Basic/BuiltinsNVPTX.def
The file was modifiedclang/test/CodeGen/
Commit 4ffad1fb489f691825d6c7d78e1626de142f26cf by wmi
[SampleFDO] Add PromotedInsns to prevent repeated ICP.

We use 0 count value profile to memorize which target has been promoted
and prevent repeated ICP for the same target, so we delete PromotedInsns.
However, I found the implementation in the patch has some shortcomings
to be fixed otherwise there will still be repeated ICP. So I add
PromotedInsns back temorarily. Will remove it after I get a thorough fix.
The file was modifiedllvm/lib/Transforms/IPO/SampleProfile.cpp
Commit 98dff5e804229d1d2fc139e44e7a04fc06bb6f92 by craig.topper
[RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64

We previously used isel patterns for this, but that used quite
a bit of space in the isel table due to OR being associative
and commutative. It also wouldn't handle shifts/ands being in
reversed order.

This generalizes the shift/and matching from GREVI to
take the expected mask table as input so we can reuse it for

There is no SHFLIW instruction, but we can promote a 32-bit
SHFLI to i64 on RV64. As long as bit 4 of the control bit isn't
set, a 64-bit SHFLI will preserve 33 sign bits if the input had
at least 33 sign bits. ComputeNumSignBits has been updated to
account for that to avoid sext.w in the tests.

Reviewed By: frasercrmck

Differential Revision:
The file was modifiedllvm/test/CodeGen/RISCV/rv64Zbp.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/lib/Target/RISCV/
Commit dbf910f0d95011e9485af859a10efb75bf28ee89 by craig.topper
[RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics.

Just like we do for isel patterns, we need to call selectVLOp
to prevent 0 from being selected to X0 by the default isel.

Reviewed By: frasercrmck

Differential Revision:
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll


  1. [test-suite] Unit tests to improve code coverage (details)
Commit 8c29bdc46cfc41dceb5809e1405c9d3d34f55b32 by archibald.elliott
[test-suite] Unit tests to improve code coverage

Adds a batch of C tests that have been found to cover several hundred
lines of Clang/LLVM that are not covered by the unit and regression
tests of the main LLVM project, nor by the test suite when run with the
-O3 configuration.

The tests were originally generated using Csmith, and were then reduced
using C-Reduce.  They have been checked for undefined behaviour-freedom
using Frama-C and CompCert, and manually checked to eliminate
implementation-defined behaviour.

Most of the new coverage achieved by these tests is in:


Reviewed By: lenary

Differential Revision:

Change-Id: Iee2a5de679ce343f1ec1d1f0ac5d8a5a177131e2
The file was addedSingleSource/UnitTests/2020-01-06-coverage-004.c
The file was addedSingleSource/UnitTests/2020-01-06-coverage-008.c
The file was addedSingleSource/UnitTests/2020-01-06-coverage-003.c
The file was addedSingleSource/UnitTests/2020-01-06-coverage-003.reference_output
The file was addedSingleSource/UnitTests/2020-01-06-coverage-007.c
The file was addedSingleSource/UnitTests/2020-01-06-coverage-009.reference_output
The file was addedSingleSource/UnitTests/2020-01-06-coverage-009.c
The file was addedSingleSource/UnitTests/2020-01-06-coverage-001.reference_output
The file was addedSingleSource/UnitTests/2020-01-06-coverage-002.c
The file was addedSingleSource/UnitTests/2020-01-06-coverage-008.reference_output
The file was addedSingleSource/UnitTests/2020-01-06-coverage-001.c
The file was addedSingleSource/UnitTests/2020-01-06-coverage-006.c
The file was addedSingleSource/UnitTests/2020-01-06-coverage-002.reference_output
The file was addedSingleSource/UnitTests/2020-01-06-coverage-005.reference_output
The file was addedSingleSource/UnitTests/2020-01-06-coverage-006.reference_output
The file was addedSingleSource/UnitTests/2020-01-06-coverage-004.reference_output
The file was addedSingleSource/UnitTests/2020-01-06-coverage-010.c
The file was addedSingleSource/UnitTests/2020-01-06-coverage-010.reference_output
The file was addedSingleSource/UnitTests/2020-01-06-coverage-005.c
The file was addedSingleSource/UnitTests/2020-01-06-coverage-007.reference_output