SuccessChanges

Summary

  1. [lit testing] "END." not "END:" (details)
  2. [RISCV] Improve register allocation around vector masks (details)
  3. [RISCV] Support extraction of misaligned subvectors (details)
Commit 4550fdff2b2eec15143fac536e41ce967e522a3a by dave
[lit testing] "END." not "END:"
The file was modifiedllvm/utils/lit/tests/xfail-cl.py
Commit 9aa20caee6b47ac601602c674749fb6c1d2179cf by fraser
[RISCV] Improve register allocation around vector masks

With vector mask registers only allocatable to V0 (VMV0Regs) it is
relatively simple to generate code which uses multiple masks and naively
requires spilling.

This patch aims to improve codegen in such cases by telling LLVM it can
use VRRegs to hold masks. This will prevent spilling in many cases by
having LLVM copy to an available VR register.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D97055
The file was modifiedllvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.h
Commit 3e1317fd323bf92c6adaf67598697049b08bb373 by fraser
[RISCV] Support extraction of misaligned subvectors

This patch extends the support for RVV EXTRACT_SUBVECTOR to cover those
which don't align to a vector register boundary. It accomplishes this by
extracting the nearest register-sized subvector (a subregister
operation), then sliding the vector down with VSLIDEDOWN and extracting
the subvector from the first position (a COPY operation).

Since this procedure involves the use of VSCALE and multiplication, the
handling of such operations is done during lowering to simplify the
implementation and make use of DAG combining. This necessitated moving
some helper functions from RISCVISelDAGToDAG to RISCVTargetLowering.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D96959
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp