SuccessChanges

Summary

  1. [lldb] [docs] Update platform support status (details)
  2. Revert "[lldb-vscode] Emit the breakpoint changed event on location resolved" (details)
  3. [X86] Add common CHECK check-prefix to sub combine tests (details)
  4. [X86] Add 'sub C1, (xor X, C1) -> add (xor X, ~C2), C1+1' tests (details)
  5. [X86] Regenerate sub.ll test (details)
  6. [X86] Replace explicit constant handling in sub(C1, xor(X, C2)) -> add(xor(X, ~C2), C1+1) fold. NFCI. (details)
  7. [X86] Add vector support to sub(C1, xor(X, C2)) -> add(xor(X, ~C2), C1+1) fold. (details)
  8. Implement simple type polymorphism for linalg named ops. (details)
  9. [KnownBits][RISCV] Improve known bits for srem. (details)
Commit 7850bb5f2a595a5dc0edf7f9be3d2250281aabe8 by mgorny
[lldb] [docs] Update platform support status

Update supported features on FreeBSD, and supported platform list
on FreeBSD, Linux and NetBSD.

Differential Revision: https://reviews.llvm.org/D97114
The file was modifiedlldb/docs/index.rst
The file was modifiedlldb/docs/status/status.rst
Commit 878d82c4f2b308f35394a6339e74e7e20434146a by antonio.afonso
Revert "[lldb-vscode] Emit the breakpoint changed event on location resolved"

This reverts commit 1f21d488bd79a06c9cf405cc5db985fcd71c4f70.
The file was modifiedlldb/tools/lldb-vscode/lldb-vscode.cpp
The file was modifiedlldb/test/API/tools/lldb-vscode/breakpoint-events/Makefile
The file was removedlldb/test/API/tools/lldb-vscode/breakpoint-events/TestVSCode_breakpointLocationResolvedEvent.py
The file was removedlldb/test/API/tools/lldb-vscode/breakpoint-events/dylib_loader.c
The file was removedlldb/test/API/tools/lldb-vscode/breakpoint-events/dylib.c
Commit 0b372c029e4ac3af500c04a8954612ec4a0257a7 by llvm-dev
[X86] Add common CHECK check-prefix to sub combine tests
The file was modifiedllvm/test/CodeGen/X86/combine-sub.ll
Commit 9872cfc5b1774a9d0ab777a3c905013619db5c32 by llvm-dev
[X86] Add 'sub C1, (xor X, C1) -> add (xor X, ~C2), C1+1' tests

This is also in sub.ll but that's for a specific i686 pattern - this adds x86_64 and vector tests
The file was modifiedllvm/test/CodeGen/X86/combine-sub.ll
Commit e7e35e17584a8c31fddd5382aabdbb08114642ff by llvm-dev
[X86] Regenerate sub.ll test
The file was modifiedllvm/test/CodeGen/X86/sub.ll
Commit 3ab32c94a4aeb688a2df127fe14b3a7a42c71c97 by llvm-dev
[X86] Replace explicit constant handling in sub(C1, xor(X, C2)) -> add(xor(X, ~C2), C1+1) fold. NFCI.

NFC cleanup before adding vector support - rely on the SelectionDAG to handle everything for us.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit b568d3d6c915a515624f6292af0785c43ffaba37 by llvm-dev
[X86] Add vector support to sub(C1, xor(X, C2)) -> add(xor(X, ~C2), C1+1) fold.
The file was modifiedllvm/test/CodeGen/X86/combine-sub.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 6c9541d4ddfdab0dcb11436485b466a759c3126c by stellaraccident
Implement simple type polymorphism for linalg named ops.

* It was decided that this was the end of the line for the existing custom tc parser/generator, and this is the first step to replacing it with a declarative format that maps well to mathy source languages.
* One such source language is implemented here: https://github.com/stellaraccident/mlir-linalgpy/blob/main/samples/mm.py
  * In fact, this is the exact source of the declarative `polymorphic_matmul` in this change.
  * I am working separately to clean this python implementation up and add it to MLIR (probably as `mlir.tools.linalg_opgen` or equiv). The scope of the python side is greater than just generating named ops: the ops are callable and directly emit `linalg.generic` ops fully dynamically, and this is intended to be a feature for frontends like npcomp to define custom linear algebra ops at runtime.
* There is more work required to handle full type polymorphism, especially with respect to integer formulations, since they require more specificity wrt types.
* Followups to this change will bring the new generator to feature parity with the current one and delete the current. Roughly, this involves adding support for interface declarations and attribute symbol bindings.

Differential Revision: https://reviews.llvm.org/D97135
The file was addedmlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-yaml-gen.cpp
The file was addedmlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
The file was modifiedmlir/docs/Dialects/Linalg.md
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/CMakeLists.txt
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/tools/mlir-linalg-ods-gen/CMakeLists.txt
The file was addedmlir/test/Dialect/Linalg/generalize-named-polymorphic-ops.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
The file was modifiedmlir/lib/Dialect/Linalg/IR/CMakeLists.txt
Commit 183bbad1d78a4bf445ec4db1ce01673f6a7feb37 by craig.topper
[KnownBits][RISCV] Improve known bits for srem.

The result must be less than or equal to the LHS side, so any
leading zeros in the left hand side must also exist in the result.
This is stronger than the previous behavior where we only considered
the sign bit being 0.

The affected test case used the sign bit being known 0 to change
a sign extend to a zero extend pre type legalization. After type
legalization the types were promoted to i64, but we no longer
knew bit 31 was zero. This shifts are are the equivalent of an
AND with 0xffffffff or zext_inreg X, i32. This patch allows us to
see that bit 31 is zero and remove the shifts.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D97124
The file was modifiedllvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
The file was modifiedllvm/lib/Support/KnownBits.cpp