SuccessChanges

Summary

  1. [LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. (details)
  2. Revert "Module: Use FileEntryRef and DirectoryEntryRef in Umbrella, Header, and DirectoryName, NFC" (details)
  3. [InstructionSimplify] SimplifyShift - rename shift amount KnownBits. NFCI. (details)
  4. make Affine parallel and yield ops MemRefsNormalizable (details)
  5. [OpenMP][NVPTX] Fixed a compilation error in deviceRTLs caused by unsupported feature in release verion of LLVM (details)
  6. [flang][test] Share all driver test dirs between `f18` and `flang-new` (details)
  7. [AMDGPU] Set threshold for regbanks reassign pass (details)
  8. [InstSimplify] Handle nsw shl -> poison patterns (details)
  9. [clang-tidy] Add cppcoreguidelines-prefer-member-initializer to ReleaseNotes (details)
  10. [LV] Ensure fixNonInductionPHIs uses a valid insertion point. (details)
  11. [NFC][VPlan] Use VPUser to store block's predicate (details)
  12. [AArch64] Regenerate check lines for neon-compare-instructions.ll. (details)
  13. [AArch64][GlobalISel] Lower G_USUBSAT and G_UADDSAT for scalars. (details)
  14. Recommit "[AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt" (details)
  15. [RISCV] Use a different constant in one of the smulo test cases to avoid converting the mul to an add. (details)
  16. Revert "[docs][ORC] Fix section title and reference." (details)
  17. [AArch64] Introduce UDOT/SDOT DAG nodes (details)
Commit eb165090bb063cb6b73433c30adeed6fef995108 by craig.topper
[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO.

This code creates 3 setccs that need to be expanded. It was
creating a sign bit test as setge X, 0 which is non-canonical.
Canonical would be setgt X, -1. This misses the special case in
IntegerExpandSetCCOperands for sign bit tests that assumes
canonical form. If we don't hit this special case we end up
with a multipart setcc instead of just checking the sign of
the high part.

To fix this I've reversed the polarity of all of the setccs to
setlt X, 0 which is canonical. The rest of the logic should
still work. This seems to produce better code on RISCV which
lacks a setgt instruction.

This probably still isn't the best code sequence we could use here.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D97181
The file was modifiedllvm/test/CodeGen/ARM/ssub_sat_plus.ll
The file was modifiedllvm/test/CodeGen/RISCV/sadd_sat.ll
The file was modifiedllvm/test/CodeGen/RISCV/ssub_sat_plus.ll
The file was modifiedllvm/test/CodeGen/RISCV/ssub_sat.ll
The file was modifiedllvm/test/CodeGen/ARM/sadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
The file was modifiedllvm/test/CodeGen/AArch64/sadd_sat_vec.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
The file was modifiedllvm/test/CodeGen/RISCV/sadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/ARM/sadd_sat.ll
The file was modifiedllvm/test/CodeGen/RISCV/xaluo.ll
The file was modifiedllvm/test/CodeGen/AArch64/ssub_sat_vec.ll
The file was modifiedllvm/test/CodeGen/ARM/ssub_sat.ll
Commit 64d8c7818db2bd428d4e2a9f27661ee49225477f by Duncan P. N. Exon Smith
Revert "Module: Use FileEntryRef and DirectoryEntryRef in Umbrella, Header, and DirectoryName, NFC"

This (mostly) reverts 32c501dd88b62787d3a5ffda7aabcf4650dbe3cd.  Hit a
case where this causes a behaviour change, perhaps the same root cause
that triggered the revert of a40db5502b2515a6f2f1676b5d7a655ae0f41179 in
7799ef7121aa7d59f4bd95cdf70035de724ead6f.

(The API changes in DirectoryEntry.h have NOT been reverted as a number
of subsequent commits depend on those.)

https://reviews.llvm.org/D90497#2582166
The file was modifiedclang/include/clang/Lex/ModuleMap.h
The file was modifiedclang/lib/Basic/Module.cpp
The file was modifiedclang/lib/Serialization/ASTReader.cpp
The file was modifiedclang/lib/Lex/ModuleMap.cpp
The file was modifiedclang/include/clang/Basic/Module.h
The file was modifiedclang/lib/Frontend/FrontendActions.cpp
Commit 18b9fc48f1b64061699533740dd6218c982f5b58 by llvm-dev
[InstructionSimplify] SimplifyShift - rename shift amount KnownBits. NFCI.

As suggested on D97305.
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
Commit af8adea155a14b99381532fc22122b7218e65db4 by jeremy.bruestle
make Affine parallel and yield ops MemRefsNormalizable

Affine parallel ops may contain and yield results from MemRefsNormalizable ops in the loop body.  Thus, both affine.parallel and affine.yield should have the MemRefsNormalizable trait.

Reviewed By: bondhugula

Differential Revision: https://reviews.llvm.org/D96821
The file was modifiedmlir/lib/Transforms/NormalizeMemRefs.cpp
The file was modifiedmlir/test/Transforms/normalize-memrefs.mlir
The file was modifiedmlir/include/mlir/Dialect/Affine/IR/AffineOps.td
Commit f6c2984a090e78947f75e096d43b476bf2ae73eb by tianshilei1992
[OpenMP][NVPTX] Fixed a compilation error in deviceRTLs caused by unsupported feature in release verion of LLVM

`ptx71` is not supported in release version of LLVM yet. As a result,
the support of CUDA 11.2 and CUDA 11.1 caused a compilation error as mentioned
in D97004. Since the support in D97004 is just a WA for releease, and we'll not
use it in the near future, using `ptx70` for CUDA 11 is feasible.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D97195
The file was modifiedopenmp/libomptarget/deviceRTLs/nvptx/CMakeLists.txt
Commit 5e54bef4d291d4353bb26e0782539b6f79625f68 by andrzej.warzynski
[flang][test] Share all driver test dirs between `f18` and `flang-new`

Originally, when we added the new driver, we created dedicated test
directories for `flang-new`. This way we separated the tests for the
`throwaway` and the new driver.

As we are increasing test coverage and starting to share tests between
the two drivers, it makes sense to share all directories and instead
rely on:
```
! REQUIRES: new-flang-driver
```
to mark tests as exclusively for the new driver.

Differential Revision: https://reviews.llvm.org/D97207
The file was modifiedflang/test/lit.cfg.py
The file was modifiedflang/test/Frontend/prescanner-diag.f90
Commit d1b92c91afd0be8939bddbf04f55ec53cf29227a by Stanislav.Mekhanoshin
[AMDGPU] Set threshold for regbanks reassign pass

This is to limit compile time. I did experiments with some
inputs and found that compile time keeps reasonable for this
pass if we have less than 100000 virtual registers and then
starts to explode somewhere between 100000 and 150000.

Differential Revision: https://reviews.llvm.org/D97218
The file was modifiedllvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
Commit 1020d161565df48ec454509724e60ab8fbbdfd66 by llvm-dev
[InstSimplify] Handle nsw shl -> poison patterns

Pulled out from D90479 - this recognises invalid nsw shl patterns with signbit changes that result in poison.

Differential Revision: https://reviews.llvm.org/D97305
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
The file was modifiedllvm/test/Transforms/InstSimplify/icmp-constant.ll
The file was modifiedllvm/test/Transforms/InstCombine/known-signbit-shift.ll
Commit 2af5275f72dad18b76d4db641c3c861d76aa29be by n.james93
[clang-tidy] Add cppcoreguidelines-prefer-member-initializer to ReleaseNotes

Following a discussion about the current state of this check on the 12.X branch, it was decided to purge the check as it wasn't in a fit to release state, see https://llvm.org/PR49318.
This check has since had some of those issues addressed and should be good for the next release cycle now, pending any more bug reports about it.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D97275
The file was modifiedclang-tools-extra/docs/ReleaseNotes.rst
Commit de40423c8512c9cfa0b244314b5e342056ec6d49 by flo
[LV] Ensure fixNonInductionPHIs uses a valid insertion point.

In some cases, Builder's insertion point may be invalidated before using
it in VPTransformState::get. Make sure the insertion point is
up-to-date.

This should fix various sanitizer errors, like
https://lab.llvm.org/buildbot/#/builders/5/builds/4933/steps/9/logs/stdio
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 3605b873f6f0df36037f418974433e2c759e978b by andrei.elovikov
[NFC][VPlan] Use VPUser to store block's predicate

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D96529
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
Commit fd03e359ddbb47fd06dc1d37777434e43b85480d by flo
[AArch64] Regenerate check lines for neon-compare-instructions.ll.

Auto-generate tests so they can be updated more easily, e.g. for D97303.
The file was modifiedllvm/test/CodeGen/AArch64/neon-compare-instructions.ll
Commit 939b5ce73461e9a6bbd57ffb27b3ef9f28b0e1ec by Amara Emerson
[AArch64][GlobalISel] Lower G_USUBSAT and G_UADDSAT for scalars.

We have some missing optimization counterparts to LowerXALUO, but it's a start.
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
Commit ef1f7f1d7db1e9bf7e256e208c295b605b014059 by Jessica Paquette
Recommit "[AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt"

Attempted fix for the added test failing.

https://lab.llvm.org/buildbot/#/builders/104/builds/2355/steps/5/logs/stdio

I can't reproduce the failure anywhere, so I'm going to guess that passing a
std::function as MatchInfo is sketchy in this context.

Switch it to a std::tuple and hope for the best.
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
Commit 5e233ff144e2f05254469ae0e20a4597b03d11b7 by craig.topper
[RISCV] Use a different constant in one of the smulo test cases to avoid converting the mul to an add.
The file was modifiedllvm/test/CodeGen/RISCV/xaluo.ll
Commit 479db97a34e3fa387c7549a4b10bce8e993605eb by Lang Hames
Revert "[docs][ORC] Fix section title and reference."

This reverts commit 6e1affe71c79a1cb5ea9d805ff7baae5cba59c0e, which caused an
error on the Sphinx doc bot.
The file was modifiedllvm/docs/ORCv2.rst
Commit f51b3de4e851812b5f7d7c307ddb7b6ec61c05ab by david.green
[AArch64] Introduce UDOT/SDOT DAG nodes

This is used to lower UDOT/SDOT instructions, as opposed to relying on
the intrinsic. Subsequent optimizations will be able to optimize them
more cleanly based on these nodes.
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h