SuccessChanges

Summary

  1. [mlir][NFC] Add missing namespace qualifier to ODS generated code (details)
  2. [clang][sema] Ignore xor-used-as-pow if both sides are macros (details)
  3. Fix a test case that should check whether or not it is passed into lld (details)
  4. [RISCV] Add isel pattern to match X > -1 to bgez. (details)
  5. [arm builtin crosscompile docs] alphabetize flags, no behavior change (details)
  6. [arm builtin crosscompile docs] add COMPILER_RT_BUILD_MEMPROF=OFF (details)
  7. [RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli (details)
  8. [IndVars] Add test cases inspired by PR48965. (details)
  9. [CodeGen] Format code comment to 80 columns. NFC. (details)
  10. [MLIR][affine-loop-fusion] Handle defining ops between the source and dest loops (details)
  11. [mlir] Check 'iter_args' in 'isLoopParallel' utility (details)
  12. [SampleFDO][NFC] Refactor: make SampleProfileLoaderBaseImpl a template class (details)
  13. [AMDGPU] require s-memtime-inst for __builtin_amdgcn_s_memtime (details)
  14. [X86] Remove custom lowering of vXi1 ADD/SUB now that they are canonicalized to XOR in getNode. (details)
  15. Support `#pragma clang section` directives on MachO targets (details)
Commit f4d78a5e3aee53d46e0f13e77f08ee610bade7fc by vlad.vinogradov
[mlir][NFC] Add missing namespace qualifier to ODS generated code

Use `::mlir::Region` inside array ref for `VariadicRegion`.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D97376
The file was modifiedmlir/test/mlir-tblgen/op-decl.td
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
Commit 2cc58463caf4c8a43c2954e4206d3647c762ba30 by tbaeder
[clang][sema] Ignore xor-used-as-pow if both sides are macros

This happens in codebases a lot, which use xor where both sides are
macros. Using xor in that case is not the common error-prone 2^6 code
that the warning was introduced for.

Don't diagnose such a use of xor.

Differential Revision: https://reviews.llvm.org/D97445
The file was modifiedclang/test/SemaCXX/warn-xor-as-pow.cpp
The file was modifiedclang/lib/Sema/SemaExpr.cpp
Commit 3b7104a2f2033d100aebb605c46fbe0495ea320b by conanap
Fix a test case that should check whether or not it is passed into lld

This test case was causing a PowerPC buildbot to fail as it happened to
be named lld-multistage,
which matches with the original regex and therefore fails the check-not.
This should better represent the desired check.

Differential Revision: https://reviews.llvm.org/D97423
The file was modifiedclang/test/Driver/hip-sanitize-options.hip
Commit 25c6b7ddd2b4d9631d0aff312b076843c16239d7 by craig.topper
[RISCV] Add isel pattern to match X > -1 to bgez.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D97262
The file was modifiedllvm/test/CodeGen/RISCV/xaluo.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.td
The file was modifiedllvm/test/CodeGen/RISCV/branch.ll
Commit b4f8daa5ec6c7c5a84fe6d36859f1ff38780ffa2 by thakis
[arm builtin crosscompile docs] alphabetize flags, no behavior change
The file was modifiedllvm/docs/HowToCrossCompileBuiltinsOnArm.rst
Commit 03b7bc0ba1ce3804f92f1c9e990b4aaa54583862 by thakis
[arm builtin crosscompile docs] add COMPILER_RT_BUILD_MEMPROF=OFF

Reported by artok on irc, thanks!
The file was modifiedllvm/docs/HowToCrossCompileBuiltinsOnArm.rst
Commit 95c68249952803330739b7311dd2bdc7b18e272f by craig.topper
[RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli

Reviewed By: frasercrmck, arcbbb

Differential Revision: https://reviews.llvm.org/D97408
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVCleanupVSETVLI.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
Commit 261f219ffc2ad0a0c7b45912e288ba6448911120 by flo
[IndVars] Add test cases inspired by PR48965.
The file was addedllvm/test/Transforms/IndVarSimplify/simplify-pointer-arithmetic.ll
Commit b368fc735d5a485ebf8ed455e078dafbccf27659 by fraser
[CodeGen] Format code comment to 80 columns. NFC.
The file was modifiedllvm/include/llvm/CodeGen/ISDOpcodes.h
Commit 203d5eeec55b1f0e0dd2aa28f5c5ebe292802e62 by diego.caballero
[MLIR][affine-loop-fusion] Handle defining ops between the source and dest loops

This patch handles defining ops between the source and dest loop nests, and prevents loop nests with `iter_args` from being fused.

If there is any SSA value in the dest loop nest whose defining op has dependence from the source loop nest, we cannot fuse the loop nests.

If there is a `affine.for` with `iter_args`, prevent it from being fused.

Reviewed By: dcaballe, bondhugula

Differential Revision: https://reviews.llvm.org/D97030
The file was modifiedmlir/lib/Transforms/LoopFusion.cpp
The file was modifiedmlir/test/Transforms/loop-fusion.mlir
Commit ebca222b65cb847f7bf4ee3da1dd7e2df35d0338 by diego.caballero
[mlir] Check 'iter_args' in 'isLoopParallel' utility

Fix 'isLoopParallel' utility so that 'iter_args' is taken into account
and loops with loop-carried dependences are not classified as parallel.

Reviewed By: tungld, vinayaka-polymage

Differential Revision: https://reviews.llvm.org/D97347
The file was modifiedmlir/lib/Analysis/Utils.cpp
The file was modifiedmlir/test/Dialect/Affine/parallelize.mlir
Commit 6103b6ad69fed0fe300f518b5115837cf6b74148 by xur
[SampleFDO][NFC] Refactor: make SampleProfileLoaderBaseImpl a template class

This patch makes SampleProfileLoaderBaseImpl a template class so it
can be used in CodeGen transformation.

Noticeable changes:
* use one template parameter and use IRTraits to get other used
   types an type specific functions.
* remove the temporary "inline" keywords in previous refactor
   patch.
* change the template function findEquivalencesFor to a regular
   function. This function has a single caller with type of
   PostDominatorTree. It's simpler to use the type directly
   because MachinePostDominatorTree is not a derived type of
   template DominatorTreeBase.

Differential Revision: https://reviews.llvm.org/D96981
The file was modifiedllvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h
The file was modifiedllvm/lib/Transforms/IPO/SampleProfile.cpp
Commit 502b3bfc6a713e5b6640faf48e72de08d7cb0aba by Stanislav.Mekhanoshin
[AMDGPU] require s-memtime-inst for __builtin_amdgcn_s_memtime

Differential Revision: https://reviews.llvm.org/D97420
The file was modifiedclang/test/CodeGenOpenCL/builtins-amdgcn-ci.cl
The file was modifiedclang/test/CodeGenOpenCL/builtins-amdgcn-gfx10.cl
The file was modifiedclang/test/CodeGenOpenCL/builtins-amdgcn-gfx9.cl
The file was modifiedclang/test/CodeGenOpenCL/builtins-amdgcn.cl
The file was modifiedclang/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
The file was modifiedclang/include/clang/Basic/BuiltinsAMDGPU.def
The file was addedclang/test/SemaOpenCL/builtins-amdgcn-error-gfx1030.cl
Commit ceaedfb5fc3a94adf9e67616d65414ddfee71e24 by craig.topper
[X86] Remove custom lowering of vXi1 ADD/SUB now that they are canonicalized to XOR in getNode.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D97478
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 7f6e3316456f939a062aad0eeaac983251a1747c by jonathan_roelofs
Support `#pragma clang section` directives on MachO targets

rdar://59560986

Differential Revision: https://reviews.llvm.org/D97233
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
The file was modifiedclang/include/clang/Basic/TargetInfo.h
The file was modifiedclang/lib/Sema/SemaAttr.cpp
The file was modifiedllvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was modifiedllvm/lib/MC/MCParser/DarwinAsmParser.cpp
The file was modifiedllvm/lib/MC/MCSectionMachO.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was addedllvm/test/CodeGen/AArch64/clang-section-macho.ll
The file was modifiedclang/test/CodeGenCXX/clang-sections.cpp
The file was addedclang/test/Sema/pragma-clang-section-macho.c
The file was modifiedllvm/include/llvm/MC/MCSectionMachO.h
The file was modifiedclang/lib/Basic/Targets/OSTargets.h