SuccessChanges

Summary

  1. [sanitizers] Fix checkout branch name (details)
  2. [sanitizers] Fix checkout branch name (details)
Commit 578f0f92d4e88bed3f019f21037733acfee36d0f by Vitaly Buka
[sanitizers] Fix checkout branch name
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_functions.sh (diff)
Commit 7f708cc38f51de4d887e1c449f9114b3b6877e85 by Vitaly Buka
[sanitizers] Fix checkout branch name
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_functions.sh (diff)

Summary

  1. Be more mathematicly precise about definition of recurrence [NFC] (details)
  2. [RISCV] Call SelectBaseAddr on the base pointer in the custom isel for vector loads and stores. (details)
  3. [dfsan] Do not test origin-tracking in atomic.cpp (details)
  4. [cgp] Minor code improvement - reuse an existing named helper [NFC] (details)
  5. Use getAlign() on atomicrmw/cmpxchg instructions, now that it's available. (details)
  6. [SystemZ] Introducing assembler dialects for the Z backend (details)
  7. [AMDGPU] Skip unclusterd rescheduling w/o ld/st (details)
  8. [AMDGPU] Avoid second rescheduling for some regions (details)
  9. [MLIR][TOSA] Lower tosa.reshape to linalg.reshape (details)
  10. [tests] Precommit for upcoming patch (details)
  11. [WebAssembly] Fix remapping branch dests in fixCatchUnwindMismatches (details)
  12. [libcxx][test] Don't require Container<cv T> extension on non-libc++ (details)
  13. [lld/mac] Add some support for dynamic lookup symbols, and implement -U (details)
  14. [WebAssembly] Avoid `bit_cast` when printing f32 and f64 immediates (details)
  15. [mlir][vector] add higher dimensional support to gather/scatter (details)
Commit f2cfef35966a24265b9e3c1b5ef8e64dcd5f431a by listmail
Be more mathematicly precise about definition of recurrence [NFC]

This clarifies the interface of the matchSimpleRecurrence helper introduced in 8020be0b8 for non-commutative operators.  After ebd3aeba, I realized the original way I framed the routine was inconsistent.  For shifts, we only matched the the LHS form, but for sub we matched both and the caller wanted that information.  So, instead, we now consistently match both forms for non-commutative operators and the caller becomes responsible for filtering if needed.  I tried to put a clear warning in the header because I suspect the RHS form of e.g. a sub recurrence is non-obvious for most folks.  (It was for me.)
The file was modifiedllvm/include/llvm/Analysis/ValueTracking.h
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
Commit b183cbfacd32ef7ac128ec0327c5972fd7e7f9c6 by craig.topper
[RISCV] Call SelectBaseAddr on the base pointer in the custom isel for vector loads and stores.

This will allow FrameIndex as the base address instead of
emitting a separate ADDI from isel. eliminateFrameIndex will likely turn
it back into an ADDI, but this makes things consistent with the
SDPatterns and VLPatterns.

I only tested one case for simplicity. I can test more if reviewers
want.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D97221
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
Commit c5c316f6d9eeecae6de538ff554ae8066ebecb91 by jianzhouzh
[dfsan] Do not test origin-tracking in atomic.cpp

This would cause linking errors after https://reviews.llvm.org/D97483
that introduced new prefixes for ABI wrappers with origin tracking mode.
We will renable this after the full origin tracking is checked in.
The file was modifiedcompiler-rt/test/dfsan/atomic.cpp
Commit 0832a58e22dedb26c508405fbd4f0cc8de562244 by listmail
[cgp] Minor code improvement - reuse an existing named helper [NFC]
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
Commit 6de6455752c139bd3f13443be6a5046e9199f037 by jyknight
Use getAlign() on atomicrmw/cmpxchg instructions, now that it's available.

These locations were missed as part of adding alignment to the
instructions, and were still making their own alignment assumptions.
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit bcc1aba6c4ee657840a306eadafa371cecd6a957 by kai
[SystemZ] Introducing assembler dialects for the Z backend

- This patch introduces a different assembler dialect ("hlasm") for z/OS.
  The default dialect has now been given the "att" dialect name. For this
  appropriate changes have been added to SystemZ.td.
- This patch also makes a few changes to SystemZInstrFormats.td which
  restrict a few condition code mnemonics to just the "att" dialect
  variant (he, le, lh, nhe, nle, nlh). These extended condition code
  mnemonics are not available in HLASM.
- A new private function has been introduced in SystemZAsmParser.cpp to
  return the assembler dialect set in SystemZMCAsmInfo.cpp. The reason we
  couldn't/haven't explicitly queried the overriden getAssemblerDialect
  function from AsmParser is outlined in this thread here. This returned
  dialect is directly passed onto the relevant matcher functions which taken
  in a variantID, so that the matcher functions can appropriately choose an
  instruction based on the variant.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D94250
The file was modifiedllvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZ.td
The file was modifiedllvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrFormats.td
Commit 635993f07bd617818097286eca0bdacb91a9afb5 by Stanislav.Mekhanoshin
[AMDGPU] Skip unclusterd rescheduling w/o ld/st

We are attempting rescheduling without load store clustering
if occupancy limits were not met with clustering. Skip this
for regions which do not have any loads or stores at all.

In a set of kernels I am experimenting with this improves
scheduling time by ~30%.

Differential Revision: https://reviews.llvm.org/D97342
The file was modifiedllvm/lib/Target/AMDGPU/GCNSchedStrategy.h
The file was modifiedllvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
Commit 799c50fe935b610d7e3c092255779f1d5e2f39d8 by Stanislav.Mekhanoshin
[AMDGPU] Avoid second rescheduling for some regions

If a region was not constrained by a high register pressure
and was not rescheduled without clustering we can skip
rescheduling it ClusteredLowOccupancyReschedule stage.

This improves scheduling speed by 25% on some kernels.

Differential Revision: https://reviews.llvm.org/D97506
The file was modifiedllvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
The file was modifiedllvm/lib/Target/AMDGPU/GCNSchedStrategy.h
Commit caccddc52a33b246d6b44143b0e8c60cc908a3ab by rob.suderman
[MLIR][TOSA] Lower tosa.reshape to linalg.reshape

Lowering from the tosa.reshape op to linalg.reshape. For same-rank or
non-collapsed/expanded cases two linalg.reshapes are inserted.

Differential Revision: https://reviews.llvm.org/D97439
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
The file was modifiedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
Commit 83bc7815c4235786111aa2abf7193292e4a602f5 by listmail
[tests] Precommit for upcoming patch
The file was addedllvm/test/Transforms/InstCombine/recurrence.ll
Commit d8b3dc5a6853467f75cc496ffd03973076d615b5 by aheejin
[WebAssembly] Fix remapping branch dests in fixCatchUnwindMismatches

This is a case D97178 tried to solve but missed. D97178 could not handle
the case when
multiple consecutive delegates are generated:
- Before:
```
block
  br (a)
  try
  catch
  end_try
end_block
          <- (a)
```

- After
```
block
  br (a)
  try
    ...
    try
      try
      catch
      end_try
            <- (a)
    delegate
  delegate
end_block
          <- (b)
```
(The `br` should point to (b) now)

D97178 assumed `end_block` exists two BBs later than `end_try`, because
it assumed the order as `end_try` BB -> `delegate` BB -> `end_block` BB.
But it turned out there can be multiple `delegate`s in between. This
patch changes the logic so we just search from `end_try` BB until we
find `end_block`.

Fixes https://github.com/emscripten-core/emscripten/issues/13515.
(More precisely, fixes
https://github.com/emscripten-core/emscripten/issues/13515#issuecomment-784711318.)

Reviewed By: dschuff, tlively

Differential Revision: https://reviews.llvm.org/D97569
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll
Commit 30cd3dd0fb9f3160988bed723cd1a1cc2f21eede by Casey
[libcxx][test] Don't require Container<cv T> extension on non-libc++

... when testing `default_initializable`. Also, include `<memory>` for `unique_ptr`.
The file was modifiedlibcxx/test/std/concepts/concept.default.init/default_initializable.compile.pass.cpp
Commit cafb6cd10c7434fdb541a40eda89fc51880f43c0 by thakis
[lld/mac] Add some support for dynamic lookup symbols, and implement -U

Dynamic lookup symbols are symbols that work like dynamic symbols
in ELF: They're not bound to a dylib like normal Mach-O twolevel lookup
symbols, but they live in a global pool and dyld resolves them against
exported symbols from all loaded dylibs.

This adds support for dynamical lookup symbols to lld/mac. They are
represented as DylibSymbols with file set to nullptr.

This also uses this support to implement the -U flag, which makes
a specific symbol that's undefined at the end of the link a
dynamic lookup symbol.

For -U, it'd be sufficient to just to a pass over remaining undefined symbols
at the end of the link and to replace them with dynamic lookup symbols then.
But I'd like to use this code to implement flat_namespace too, and that will
require real support for resolving dynamic lookup symbols in SymbolTable. So
this patch adds this now already.

While writing tests for this, I noticed that we didn't set N_WEAK_DEF in the
symbol table for DylibSymbols, so this fixes that too.

Differential Revision: https://reviews.llvm.org/D97521
The file was modifiedlld/MachO/SymbolTable.cpp
The file was modifiedlld/MachO/Symbols.h
The file was modifiedlld/MachO/Driver.cpp
The file was modifiedlld/MachO/SymbolTable.h
The file was modifiedlld/MachO/Options.td
The file was modifiedlld/MachO/SyntheticSections.cpp
The file was modifiedlld/MachO/Writer.cpp
The file was addedlld/test/MachO/U-dynamic-lookup.s
Commit c62dabc3f501d3c60846bb6259113990d4f02e75 by Dev
[WebAssembly] Avoid `bit_cast` when printing f32 and f64 immediates

Use `APInt` to convert a 32-bit or 64-bit immediate to an `APFloat` rather than
`bit_cast` to a `float` or `double` to avoid going through host floating-point and
potentially changing the bit pattern of NaNs.

Differential Revision: https://reviews.llvm.org/D97490
The file was modifiedllvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp
Commit df5ccf5a94ad04231e8426dd0d02689a0717453b by ajcbik
[mlir][vector] add higher dimensional support to gather/scatter

Similar to mask-load/store and compress/expand, the gather and
scatter operation now allow for higher dimension uses. Note that
to support the mixed-type index, the new syntax is:
   vector.gather %base [%i,%j] [%kvector] ....
The first client of this generalization is the sparse compiler,
which needs to define scatter and gathers on dense operands
of higher dimensions too.

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D97422
The file was modifiedmlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
The file was modifiedmlir/test/Dialect/Vector/canonicalize.mlir
The file was modifiedmlir/test/Dialect/Vector/ops.mlir
The file was modifiedmlir/test/Dialect/Linalg/sparse_vector.mlir
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Sparsification.cpp
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
The file was modifiedmlir/test/Dialect/Vector/vector-mem-transforms.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-gather.mlir
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
The file was modifiedmlir/test/Dialect/Vector/invalid.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-sparse-saxpy-jagged-matvec.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-scatter.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-sparse-dot-matvec.mlir