SuccessChanges

Summary

  1. [NFC][PowerPC] Add the inheritable and additional features to make the (details)
  2. [LegalizeDAG] When expanding vector SRA/SRL/SHL add the new BUILD_VECTOR (details)
Commit 4cde2d6b8db6257739c44d339a1677934b154704 by qshanz
[NFC][PowerPC] Add the inheritable and additional features to make the
processor definition more clear
The old processor design assume that, all the old processor's feature
must be inherited into future processor. That is not true as instruction
fusion or some implementation defined features are not inheritable.
What this patch did:
* Rename the old "specific features" to "additional features" that keep
the new added inheritable features.
* Use the "specific features" to keep those features only for specific
processor.
* Add the "inheritable features" to keep all the features that
inherited from early processor.
Differential Revision: https://reviews.llvm.org/D70768
The file was modifiedllvm/lib/Target/PowerPC/PPC.td
Commit f92000187e149a51900c05056ed644f43603fb66 by craig.topper
[LegalizeDAG] When expanding vector SRA/SRL/SHL add the new BUILD_VECTOR
to the Results vector instead of just calling ReplaceNode
The code that processes the Results vector also calls ReplaceNode and
makes ExpandNode return true.
If we don't add it to the Results node, we end up returning false from
ExpandNode. This causes ConvertNodeToLibcall to be called next. But
ConvertNodeToLibcall doesn't do anything for shifts so they just pass
through unmodified. Except for printing a debug message.
Ultimately, I'd like to add more checks to ExpandNode and
ConvertNodeToLibcall to make sure we don't have nodes marked as Expand
that don't have any Expand or libcall handling.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp