SuccessChanges

Summary

  1. [libcxx][test] Fix span tests. (details)
  2. [lldb][NFC] Remove redundant ClangASTContext constructor that takes (details)
  3. AArch64: add missing Apple CPU names and use them by default. (details)
  4. Revert "[InstCombine] fold zext of masked bit set/clear" (details)
  5. [llvm-symbolizer]Fix printing of malformed address values not passed via (details)
  6. [lldb] Remove default llvm::Triple argument from ClangASTContext (details)
  7. [NFC][ARM] Update tests (details)
  8. [Dsymutil][Debuginfo][NFC] Reland: Refactor dsymutil to separate DWARF (details)
  9. [gn build] (manually) merge 1cf11a4c67a15 (details)
  10. Disallow an empty string literal in an asm label (details)
  11. [ARM][MVE] Enable masked gathers from vector of pointers (details)
  12. [gn build] Port 346f6b54bd1 (details)
  13. Fixing a formatting nit; NFC (details)
  14. [NFC] Move InPQueue into arguments of releaseNode (details)
  15. [Intrinsic] Add fixed point division intrinsics. (details)
  16. [clang-tidy] Disable match on `if constexpr` statements in template (details)
  17. [ARM,MVE] Intrinsics for partial-overwrite imm shifts. (details)
  18. [ARM,MVE] Intrinsics for variable shift instructions. (details)
  19. [JumpThreading] Thread jumps through two basic blocks (details)
  20. [OPENMP]Allow comma in combiner expression. (details)
  21. [DAGCombiner] clean up extract-of-concat fold; NFC (details)
  22. [InstCombine] Adding testcase for Z / (1.0 / Y) => (Y * Z); NFC (details)
  23. [SelectionDAG] Use llvm::Optional<APInt> for FoldValue. (details)
  24. [amdgpu] Remove unused header. NFC. (details)
  25. [lldb/CMake] Use LLDB's autodetection logic for libxml2 (details)
  26. Fix "pointer is null" static analyzer warning. NFCI. (details)
  27. Fix "pointer is null" static analyzer warning. NFCI. (details)
  28. [MC] writeFragment - assert MCFragment::FT_Fill length is legal. (details)
  29. [ELF] Don't special case weak symbols for pie with no shared objects (details)
  30. [ELF] Delete an unused special rule from isStaticLinkTimeConstant. NFC (details)
  31. [BranchAlign] Compiler support for suppressing branch align (details)
  32. [X86] Add isel patterns for bitcasting between v32i1/v64i1 and (details)
  33. [X86] Custom type legalize v4i64->v4f32 uint_to_fp on sse4.1 targets in (details)
  34. [mlir][Linalg] Lower linalg.reshape to LLVM for the static case (details)
  35. [mlir] NFC: Move the state for managing aliases out of ModuleState and (details)
  36. [clang-tidy] Remove broken test on Windows for (details)
  37. [MLIR] Fix ML IR build on Windows with Visual Studio (details)
  38. [X86] Keep cl::opts at top of file [NFC] (details)
  39. Merge memtag instructions with adjacent stack slots. (details)
  40. Add a new AST matcher 'optionally'. (details)
  41. LTOVisibility.rst: fix up syntax in example (details)
  42. [x86] add test for concat-extract corner case; NFC (details)
  43. Canonicalize static alloc followed by memref_cast and std.view (details)
  44. [LLD] [COFF] Fix post-commit suggestions for absolute symbol equality (details)
  45. [InstSimplify] add tests for select of true/false; NFC (details)
  46. [lldb/SWIG] Refactor extensions to be non Python-specific (details)
  47. Revert "[JumpThreading] Thread jumps through two basic blocks" (details)
  48. [lldb/CMake] Only auto-enable Lua when SWIG is found (details)
  49. Delete dead code. (details)
  50. Revert "Merge memtag instructions with adjacent stack slots." (details)
  51. [MLIR] Don't use SSA names directly for std.view canonicalization test (details)
  52. [cfi][test] cross-dso/stats.cpp: don't assume the order of static (details)
  53. [lldb/SWIG] Refactor extensions to be non Python-specific (2/2) (details)
  54. [X86]  Remove EFLAGS from live-in lists in X86FlagsCopyLowering. (details)
  55. [NFC] Whitespace fixes (details)
  56. [libcxx] [test] Disable refwrap/weak_result.pass.cpp in C++20 mode (details)
  57. Recommit "[MachineVerifier] Improve verification of live-in lists." (details)
  58. [PowerPC]: Add powerpcspe target triple subarch component (details)
  59. [NFC][InlineCost] Factor cost modeling out of CallAnalyzer traversal. (details)
  60. [Attributor][FIX] Avoid dangling value pointers during code modification (details)
  61. [Attributor][FIX] Carefully change invokes to calls (after manifest) (details)
  62. Revert "[NFC][InlineCost] Factor cost modeling out of CallAnalyzer (details)
  63. [PowerPC] when folding rlwinm+rlwinm. to andi., we should use first (details)
  64. [lldb] Remove various dead Compare functions (details)
  65. [MIR] Target specific MIR formating and parsing (details)
  66. Save more descriptive error msg from FBS/BKS, relay it up to lldb. (details)
  67. Revert "[MIR] Target specific MIR formating and parsing" (details)
  68. [MIR] Target specific MIR formating and parsing (details)
  69. Revert "[MIR] Target specific MIR formating and parsing" (details)
  70. Revert "Revert "[MIR] Target specific MIR formating and parsing"" (details)
  71. [DAGCombine] Fold the (fma -x, y, -z) to -(fma x, y, z) (details)
  72. [lldb/SWIG] Refactor extensions to be non Python-specific (3/3) (details)
  73. [SCEV] [NFC] add testcase for constant range for addrecexpr with nsw (details)
  74. [APFloat] Fix checked error assert failures (details)
  75. [mlir][VectorOps] Implement strided_slice conversion (details)
  76. [mlir][VectorOps] Implement insert_strided_slice conversion (details)
  77. [ARM][LowOverheadLoops] Update liveness info (details)
  78. [mlir][GPU] introduce utilities for promotion to workgroup memory (details)
  79. [LV] Still vectorise when tail-folding can't find a primary inducation (details)
  80. [DWARFDebugLoc] Tweak error message when resolving offset pairs with no (details)
  81. Revert "[ARM][LowOverheadLoops] Update liveness info" (details)
  82. [Matrix] Implement back-propagation of shape information. (details)
  83. [LoopUtils][NFC] Minor refactoring in getLoopEstimatedTripCount. (details)
  84. [VE] Target stub for NEC SX-Aurora (details)
  85. [Matrix] Propagate and use shape information for loads. (details)
  86. [clangd] Refurbish HoverInfo::present (details)
  87. [Matrix] Update shape propagation to iterate until done. (details)
  88. [lldb] Fix that TestNoSuchArch.py was passing for the wrong reason (details)
  89. Fix MSVC unhandled enum warning. NFCI. (details)
  90. [clang-tidy] For checker `readability-misleading-indentation` update (details)
  91. [ARM][MVE] Don't unroll intrinsic loops. (details)
  92. Fix "pointer is null" static analyzer warnings. NFCI. (details)
  93. Fix "pointer is null" static analyzer warnings. NFCI. (details)
  94. [lldb/DWARF] Add is_dwo member to DWARFUnit (details)
  95. [lldb/DWARF] Fix mixed v4+v5 location lists (details)
  96. Fix "pointer is null" static analyzer warning. NFCI. (details)
  97. Fix "pointer is null" static analyzer warning. NFCI. (details)
  98. [NFC][ARM] LowOverheadLoop comments (details)
  99. [Concepts] Function trailing requires clauses (details)
  100. [mlir] fix test failure in EDSC/builder-api-test (details)
  101. [lldb] Modernize OptionValue::SetValueChangedCallback (details)
  102. [InstCombine] Use minimal FMF in testcase for Z / (1.0 / Y) => (Y * Z); (details)
  103. [ARM][MVE] MVE-I should not be disabled by -mfpu=none (details)
  104. [InstSimplify] select Cond, true, false --> Cond (details)
  105. [Concepts] Fix failing test on Windows (details)
  106. [DAGCombiner] reduce extract subvector of concat (details)
  107. [OPENMP]Remove unused code, NFC. (details)
  108. IR: remove "else" after "return". NFCI. (details)
  109. [ARM,MVE] Fix valid immediate range for vsliq_n. (details)
  110. [ARM,MVE] Add missing IntrNoMem flag on IR intrinsics. (details)
  111. AMDGPU: Add register class to DS_SWIZZLE_B32 pattern (details)
  112. TableGen/GlobalISel: Fix slightly wrong generated comment (details)
  113. AMDGPU/GlobalISel: Fix add of neg inline constant pattern (details)
  114. AMDGPU/GlobalISel: Add equiv xform for bitcast_fpimm_to_i32 (details)
  115. AMDGPU/GlobalISel: Add selectVOP3Mods_nnan (details)
  116. AMDGPU/GlobalISel: Add IMMPopCount xform (details)
  117. AMDGPU/GlobalISel: Fix import of zext of s16 op patterns (details)
  118. AMDGPU: Use new PatFrag system for d16 load nodes (details)
  119. AMDGPU: Use new PatFrag system for d16 stores (details)
  120. AMDGPU: Eliminate more legacy codepred address space PatFrags (details)
  121. AMDGPU/GlobalISel: Fix import of integer med3 (details)
  122. TableGen: Remove unused code (details)
  123. [ELF][Hexagon] Add support for IE relocations (details)
  124. [InstCombine] Z / (1.0 / Y) => (Y * Z) (details)
  125. [libcxxabi] Allow tests to link with static libc++abi/libc++ even if the (details)
  126. [clangd] Respect `--sysroot` argument if it is set (details)
  127. [lldb/SWIG] Add missing '\' in macros again (details)
  128. [lldb/Lua] Make lldb.debugger et al available to Lua (details)
  129. [NFCI][LoopUnrollAndJam] Changing LoopUnrollAndJamPass to a function (details)
  130. Improve support of GNU mempcpy (details)
  131. [OpenCL][Docs] Rename C++ for OpenCL label (details)
  132. [lldb/Bindings] Move bindings into their own subdirectory (details)
  133. [clangd] Adjust diagnostic range to be inside main file (details)
  134. [lldb/SWIG] Fix capitalization for case sensitive file systems. (details)
  135. [Clang] Handle target-specific builtins returning aggregates. (details)
  136. [Support][NFC] Add a comment about the semantics of MF_HUGE_HINT flag (details)
  137. [NFC,format] Sort switch cases alphabetically (details)
  138. [Support][NFC] Make some helper functions "static" in Memory.inc (details)
  139. [lldb/SWIG] Undo incorrect substitution (details)
  140. [SystemZ] Fix matching another pattern for nxgrk (PR44496) (details)
  141. [x86] add tests for 2-way splat copy; NFC (details)
  142. [Support][NFC] Add an explicit unit test for Process::getPageSize() (details)
  143. [TargetLowering][X86] TeachSimplifyDemandedBits to handle cases where (details)
  144. [demangle] Copy back some NFC commits from LLVM (details)
  145. [PowerPC] The VK_PLT symbolref modifier is only used on 32-bit ELF. (details)
  146. [X86] AMD Znver2 (Rome) Scheduler enablement (details)
  147. [ms] [X86] Use "P" modifier on all branch-target operands in inline X86 (details)
  148. [clang] Enforce triple in mempcpy test (details)
  149. [GlobalISel][AArch64] Import + select LDR*roW and STR*roW patterns (details)
  150. [X86] Add ueq/one fp128 quiet compare tests. NFC (details)
  151. Re-apply "[ELF] Allow getErrPlace() to work before Out::bufferStart is (details)
  152. MipsDelaySlotFiller: Update registers def-uses for BUNDLE instructions (details)
  153. [mlir] NFC: Move the state for managing SSA value names out of (details)
  154. [libc++] Explicitly enumerate std::string external instantiations. (details)
  155. [clang-tidy] Refresh the add_new_check.py now that we use a table + (details)
  156. [clangd] Handle DeducedTemplateSpecializationType in TargetFinder (details)
  157. phab doc: remove the svn section (details)
  158. phab doc: also document 'arc land' (details)
  159. phab doc: Replace or remove references to svn (details)
  160. AMDGPU/GlobalISel: Widen 16-bit shift amount sources (details)
  161. AMDGPU/GlobalISel: Fix argument lowering for vectors of pointers (details)
  162. GlobalISel: Don't assert on MoreElements creating vectors (details)
  163. TableGen/GlobalISel: Address fixme (details)
  164. GlobalISel: Move getLLTForMVT/getMVTForLLT (details)
  165. Add gdb pretty printer for MutableArrayRef, remove ConstArrayRef. (details)
  166. Add builtins for aligning and checking alignment of pointers and (details)
  167. [mlir] mlir-cpu-runner test's cblas_interface should export functions on (details)
  168. [mlir] add a missing dependency for Linalg conversion (details)
  169. [AArch64][GlobalISel] Implement selection of <2 x float> vector splat. (details)
  170. CodeGen: Use LLT instead of EVT in getRegisterByName (details)
  171. GlobalISel: Fix else after return (details)
  172. DAG: Don't use unchecked dyn_cast (details)
  173. GlobalISel: Handle llvm.read_register (details)
  174. TableGen/GlobalISel: Add way for SDNodeXForm to work on timm (details)
  175. TableGen/GlobalISel: Fix pattern matching of immarg literals (details)
  176. [lldb/Lua] Add lua typemaps for INOUT params (details)
  177. [mlir] Use getDenseElementBitwidth instead of (details)
  178. When diagnosing the lack of a viable conversion function, also list (details)
  179. AVR: Update for getRegisterByName change (details)
  180. [lldb] Remove spurious file (details)
  181. [AMDGPU] Fix bundle scheduling (details)
  182. When reading Aux file in chunks, read consecutive byte ranges (details)
  183. [ELF] Fix includeInDynsym() when an undefined weak is merged with a lazy (details)
  184. AMDGPU/GlobalISel: Fix G_EXTRACT_VECTOR_ELT mapping for s-v case (details)
  185. AMDGPU/GlobalISel: Select G_EXTRACT_VECTOR_ELT (details)
  186. Relax opcode checks in test for G_READCYCLECOUNTER to check for only a (details)
  187. CWG2352: Allow qualification conversions during reference binding. (details)
  188. [NFC] Style cleanup (details)
  189. fix a few typos to cycle the bots (details)
  190. fix another typo to cycle bots (details)
  191. [ThinLTO] Pass CodeGenOpts like UnrollLoops/VectorizeLoop/VectorizeSLP (details)
  192. [xray] Remove cl::sub from alias options (details)
  193. clang-tidy doc - remove the widths (details)
  194. [Syntax] Update comment, remove stale FIXME. NFC (details)
  195. [LV] VPValues for memory operation pointers (NFCI) (details)
  196. Restore order in clang-tidy section of release notes (details)
  197. Allow system header to provide their own implementation of some builtin (details)
  198. [NFC] [PowerPC] Add isPredicable for basic instrs (details)
  199. [clangd] Improve type printing in hover (details)
  200. [clangd] Fix markdown rendering in VSCode (details)
  201. Fix several issues with compiler extensions (details)
  202. [SVEV] Recognise hardware-loop intrinsic loop.decrement.reg (details)
  203. Follow up of 67bf9a6154d4b82c, minor fix in test case, removed duplicate (details)
  204. [libcxx] Force-cache LIBCXX_CXX_ABI_LIBRARY_PATH (details)
  205. [CMake] Support running libc++abi tests in CrossWinToARMLinux cache file (details)
  206. XFAIL load_extension.ll test on macOS only (details)
  207. [MIR] Fix cyclic dependency of MIR formatter (details)
  208. [LV] Silence unused variable warning in Release builds. NFC. (details)
  209. Don't use dyn_cast_or_null if we know the pointer is nonnull. (details)
  210. [X86][AVX] Add tests for v8f32/v8i32 089abcde and 0189abcd shuffles (details)
  211. Fix Wdocumentation warning. NFCI. (details)
  212. Fix Wdocumentation warning. NFCI. (details)
  213. Data formatters: Look through array element typedefs (details)
  214. Fix "pointer is null" static analyzer warnings. NFCI. (details)
  215. [ARM,MVE] Make `vqrshrun` generate the right instruction. (details)
  216. [ARM][Thumb2] Fix ADD/SUB invalid writes to SP (details)
  217. [lldb/lua] Make convenience_variables.test compatible with lua-5.1 (details)
  218. [lldb/DWARF] Don't automatically search dwo unit attributes (details)
  219. [CodeComplete] Suggest 'return nullptr' in functions returning pointers (details)
  220. [lldb] Surpress "bitfield too small" gcc warning (details)
  221. [Support] ThreadPoolExecutor fixes for Windows/MinGW (details)
  222. [lldb][tests] Take into account all parent's categories when traverse (details)
  223. [lldb][test] NFC, re-use _getTestPath() function (details)
  224. [FPEnv] Generate constrained FP comparisons from clang (details)
  225. [lldb][tests] Cleanup '.categories' (details)
  226. Reverting, broke some bots. Need further investigation. (details)
  227. Sprinkle some constexpr on default ctors so the compiler can diagnose (details)
  228. ARMLowOverheadLoops: a few more dbg msgs to better trace rejected TP (details)
  229. RangeDataVector: Support custom sorting for D63540 (details)
  230. [ARM][MVE] Tail predicate VMAX,VMAXA,VMIN,VMINA (details)
  231. [FPEnv] Invert sense of MIFlag::FPExcept flag (details)
  232. [lldb][tests][NFC] Unify variable naming convention (details)
  233. [lldb][tests] Make it possible to expect failure for a whole category (details)
  234. AMDGPU/GlobalISel: Clamp G_ZEXT source sizes (details)
  235. [LIBOMPTARGET]Ignore empty target descriptors. (details)
  236. [DebugInfo] Improve error message text (details)
  237. [DebugInfo][NFC] Remove unused variable/fix variable naming (details)
  238. [NFC] format unittest for ExprMutAnalyzer (details)
  239. [PowerPC] Handle constant zero bits in BitPermutationSelector (details)
  240. Add support for __declspec(guard(nocf)) (details)
  241. Add missing nullptr checks. (details)
  242. [analyzer] Add PlacementNewChecker (details)
  243. [mlir][spirv] Fix typos related to (de)serialization. (details)
  244. [InstCombine] add tests for fsub; NFC (details)
  245. [BPF] extend BTF_KIND_FUNC to cover global, static and extern funcs (details)
  246. [clangd] Fix targetDecl() on certain usage of ObjC properties. (details)
  247. [gn build] Port 5e7beb0a414 (details)
  248. [X86][AVX] lowerShuffleAsLanePermuteAndShuffle - consistently normalize (details)
  249. Fix "pointer is null" static analyzer warning. NFCI. (details)
  250. Fix "pointer is null" static analyzer warning. NFCI. (details)
  251. [examples] Add missing dependency in llvm examples (details)
  252. [AIX] Allow vararg calls when all arguments reside in registers (details)
  253. Fix "pointer is null" static analyzer warning. NFCI. (details)
  254. [AArch64] Add function attribute "patchable-function-entry" to add NOPs (details)
  255. [X86] Support function attribute "patchable-function-entry" (details)
  256. Support function attribute patchable_function_entry (details)
  257. [Driver][CodeGen] Add -fpatchable-function-entry=N[,0] (details)
  258. [ELF] Make TargetInfo::writeIgotPlt a no-op (details)
  259. [LegalizeVectorOps] Improve handling of multi-result operations. (details)
  260. [lldb] Remove FieldDecl stealing hack by rerouting indirect imports to (details)
  261. [lldb/Lua] Support loading Lua modules (details)
  262. Update the attribution policy to use the 'Author' property of a git (details)
  263. [analyzer] Move PlacementNewChecker to alpha (details)
  264. [TargetLowering][ARM][X86] Change softenSetCCOperands handling of ONE to (details)
  265. [lld][WebAssembly] Add libcall symbols to the link when LTO is being (details)
  266. [CMake] Fix modules build after DWARFLinker reorganization (details)
  267. [clang] Fix out-of-bounds memory access in ComputeLineNumbers (details)
  268. [Driver][PowerPC] Move powerpcspe logic from cc1 to Driver (details)
  269. [ASTMatchers] Make test more clear about what it is verifying (details)
  270. [Tests] Precommit tests showing default branch padding on skylake (details)
  271. [lldb] Make CompleteTagDeclsScope completion order deterministic (details)
  272. [lldb] Fix TestClangASTContext.TestFunctionTemplateInRecordConstruction (details)
  273. Implement new AST matcher hasAnyCapture to match on LambdaExpr captures. (details)
  274. MakeUniqueCheck.cpp: explicit the fact that there is an autofix for this (details)
  275. clang-tidy doc: Refresh the list of checkers and polish the script (details)
  276. [TargetLowering] Use SelectionDAG::getSetCC and remove a repeated call (details)
  277. clang-tidy doc: unbreak the CI (details)
  278. Summary: update macro for OFF_T so that sanitizer works on AARCH64. (details)
  279. [lldb/Scripts] Remove buildbot.py (details)
  280. [lldb/Scripts] Remove remote-build.py (details)
  281. [lldb/Scripts] Move android script from underneath Python dir (details)
  282. [AArch64] Add isAuthenticated predicate to MCInstDesc (details)
  283. [lldb/Test] Bypass LLDB_TEST_COMMON_ARGS for certain dotest args (NFC) (details)
  284. [lldb/Utils] Remove vim-lldb (details)
  285. lldbutil: Forward ASan launch info to test inferiors (details)
  286. Let targets adjust operand latency of bundles (details)
  287. [lldb/Reproducer] Add SBReproducer::Replay overload (again) (details)
  288. Only destroy static locals if they have non-trivial destructors. (details)
  289. [LockFileManager] Make default waitForUnlock timeout a parameter, NFC (details)
  290. [NFC][InlineCost] Factor cost modeling out of CallAnalyzer traversal. (details)
  291. [mlir] NFC: put C++ code emission classes in their own files (details)
  292. [mlir][ods] Support dialect specific content emission via hooks (details)
  293. Improve precision of documentation comment. (details)
  294. [AArch64] Don't generate libcalls for wide shifts on Darwin (details)
  295. Remove redundant implicit cast creation. (details)
  296. Add a FIXME and corresponding test coverage for some suspicious behavior (details)
  297. Clean up and slightly generalize implementation of composite pointer (details)
  298. driver: Allow -fdebug-compilation-dir=foo in joined form. (details)
  299. [Driver] Fix OptionClass of -fconvergent-functions and -fms-volatile (details)
  300. [Concepts] Fix MarkUsedTemplateParameters for exprs (details)
  301. Remove umask tests (details)
  302. [COFF] Align ARM64 range extension thunks at instruction boundary (details)
  303. [TargetLowering][ARM][Mips][WebAssembly] Remove the ordered FP compare (details)
  304. [SCEV] [NFC] add more test cases for range of addrecexpr with nsw flag (details)
  305. [NFC] [PowerPC] Update mi-peephole-splat test (details)
  306. [AMDGPU] Remove unnecessary v_mov from a register to itself in WQM (details)
  307. Mark the test/Feature/load_extension.ll test as unsupported on Darwin. (details)
  308. [X86] Use ReplaceAllUsesWith instead of ReplaceAllUsesOfValueWith to (details)
  309. [X86][Disassembler] Simplify readPrefixes (details)
  310. [X86] Preserve fpexcept property when turning strict_fp_extend and (details)
  311. [X86] Simplify code by removing an unreachable condition. NFCI (details)
  312. Add test for GDB pretty printers. (details)
  313. [X86] Remove dead code from X86DAGToDAGISel::Select that is no longer (details)
  314. [InstCombine] Preserve nuw on sub of geps (PR44419) (details)
  315. [LoopSimplify] Regenerate test checks; NFC (details)
  316. [LoopRotate] Add tests for rotate with switch; NFC (details)
  317. DSE: fix bug where we would only check libcalls for name rather than (details)
  318. [X86] Add more complex tests for vector masks used with AND/OR/XOR. (details)
  319. [X86][AVX] Add lowerShuffleAsLanePermuteAndSHUFP lowering (details)
  320. Fix copy+paste typo in shuffle test name (details)
  321. [Sema] Improve -Wrange-loop-analysis warnings. (details)
  322. [X86] Fix outdated comment (details)
  323. moveOperands - assert Src/Dst MachineOperands are non-null. (details)
  324. Remove copy ctors identical to the default one. NFC. (details)
  325. Fix uninitialized value clang static analyzer warning. NFC. (details)
  326. Fix "pointer is null" static analyzer warning. NFCI. (details)
  327. Fix "pointer is null" static analyzer warnings. NFCI. (details)
  328. Fix "pointer is null" static analyzer warning. NFCI. (details)
  329. Fix "pointer is null" static analyzer warning. NFCI. (details)
  330. Fix "pointer is null" static analyzer warnings. NFCI. (details)
  331. GlobalModuleIndex - Fix use-after-move clang static analyzer warning. (details)
  332. [X86AsmBackend] Be consistent about placing definitions out of line (details)
  333. [X86AsmBackend] Move static function before sole use [NFC] (details)
  334. [X86] Adjust nop emission by compiler to consider target decode (details)
  335. [mlir] NFC: Remove Value::operator* and Value::operator-> now that Value (details)
  336. [ASTMatchers] extract public matchers from const-analysis into own patch (details)
  337. Revert "[ASTMatchers] extract public matchers from const-analysis into (details)
  338. [ExecutionEngine] Re-enable FastISel for non-iOS arm targets. (details)
  339. Add -Wrange-loop-analysis changes to ReleaseNotes (details)
  340. [X86] Turn FP_ROUND/STRICT_FP_ROUND into (details)
  341. [X86][Disassembler] Simplify and optimize reader functions (details)
  342. [LegalizeVectorOps] Only pass SDNode* instead SDValue to all of the (details)
  343. [LegalizeVectorOps] Remove some of the simpler Expand methods. Pass (details)
  344. [X86][Disassembler] Replace custom logger with LLVM_DEBUG (details)
  345. [Support] Optionally call signal handlers when a function wrapped by the (details)
  346. [ORC] Fix argv handling in runAsMain / lli. (details)
  347. [Disassembler] Delete the VStream parameter of (details)
  348. [X86][Disassembler] Optimize argument passing and immediate reading (details)
  349. [X86][Disassembler] Shrink X86GenDisassemblerTables.inc from 36M to 6.1M (details)
  350. [LegalizeVectorOps] Expand vector MERGE_VALUES immediately. (details)
  351. [TargetLowering][X86] Connect the chain from STRICT_FSETCC in (details)
  352. [LegalizeVectorOps] Parallelize the lo/hi part of STRICT_UINT_TO_FLOAT (details)
  353. [SCEV] more accurate range for addrecexpr with nsw flag. (details)
  354. [X86] Don't call LowerSETCC from LowerSELECT for (details)
  355. [NFC] Refactor memory ops cluster method (details)
  356. [profile] Support merge pool size >= 10 (details)
  357. [X86][Disassembler] Simplify (details)
  358. [X86][Disassembler] Merge X86DisassemblerDecoder.cpp into (details)
  359. [X86][AVX] lowerShuffleAsLanePermuteAndSHUFP - only set the demanded (details)
Commit a1857e2ce35e749e16d092305f53c0f2bf2e9c7b by stl
[libcxx][test] Fix span tests.
span.cons/container.pass.cpp N4842 22.7.3.2 [span.cons]/13 constrains
span's range constructor for ranges::contiguous_range (among other
criteria).
24.4.5 [range.refinements]/2 says that contiguous_range requires data(),
and (via contiguous_range, random_access_range, bidirectional_range,
forward_range, input_range, range) it also requires begin() and end()
(see 24.4.2 [range.range]/1).
Therefore, IsAContainer needs to provide begin() and end().
(Detected by MSVC's concept-constrained implementation.)
span.cons/stdarray.pass.cpp This test uses std::array, so it must
include <array>.
<span> isn't guaranteed to drag in <array>.
(Detected by MSVC's implementation which uses a forward declaration to
avoid dragging in <array>, for increased compiler throughput.)
span.objectrep/as_bytes.pass.cpp
span.objectrep/as_writable_bytes.pass.cpp Testing `sp.extent ==
std::dynamic_extent` triggers MSVC warning C4127 "conditional expression
is constant". Using `if constexpr` is a simple way to avoid this without
disrupting anyone else (as span requires C++20 mode).
span.tuple/get.pass.cpp 22.7.3.2 [span.cons]/4.3: "Preconditions: If
extent is not equal to dynamic_extent, then count is equal to extent."
These lines were triggering undefined behavior (detected by assertions
in MSVC's implementation).
I changed the count arguments in the first two chunks, followed by
changing the span extents, in order to preserve the test's coverage and
follow the existing pattern.
span.cons/span.pass.cpp 22.7.3.2 [span.cons]/18.1 constrains span's
converting constructor with
"Extent == dynamic_extent || Extent == OtherExtent is true".
This means that converting from dynamic extent to static extent is not
allowed. (Other constructors tested elsewhere, like span(It first,
size_type count), can be used to write such code.)
As this is the test for the converting constructor, I have:
* Removed the "dynamic -> static" case from checkCV(), which is
comprehensive.
* Changed the initialization of std::span<T, 0> s1{}; in
testConstexprSpan() and testRuntimeSpan(), because s1 is used below.
* Removed ASSERT_NOEXCEPT(std::span<T, 0>{s0}); from those functions, as
they are otherwise comprehensive.
* Deleted testConversionSpan() entirely. Note that this could never
compile (it had a bool return type, but forgot to say `return`). And it
couldn't have provided useful coverage, as the /18.2 constraint
"OtherElementType(*)[] is convertible to ElementType(*)[]" permits only
cv-qualifications, which are already tested by checkCV().
The file was modifiedlibcxx/test/std/containers/views/span.objectrep/as_bytes.pass.cpp
The file was modifiedlibcxx/test/std/containers/views/span.objectrep/as_writable_bytes.pass.cpp
The file was modifiedlibcxx/test/std/containers/views/span.tuple/get.pass.cpp
The file was modifiedlibcxx/test/std/containers/views/span.cons/span.pass.cpp
The file was modifiedlibcxx/test/std/containers/views/span.cons/stdarray.pass.cpp
The file was modifiedlibcxx/test/std/containers/views/span.cons/container.pass.cpp
Commit 0a4daff6e26f276dd92e777b597e94e093ae018d by Raphael Isemann
[lldb][NFC] Remove redundant ClangASTContext constructor that takes
ArchSpec
ArchSpec has a superset of the information of llvm::Triple but the
ClangASTContext just uses the Triple part of it. This deletes the
ArchSpec constructor and all the code creating ArchSpecs and instead
just uses the llvm::Triple constructor for ClangASTContext.
The file was modifiedlldb/include/lldb/Symbol/ClangASTContext.h
The file was modifiedlldb/source/Symbol/ClangASTContext.cpp
Commit 903e5c3028d61481c570c09eeb5e7a920c2d7d38 by Tim Northover
AArch64: add missing Apple CPU names and use them by default.
Apple's CPUs are called A7-A13 in official communication, occasionally
with weird suffixes which we probably don't need to care about. This
adds each one and describes its features. It also switches the default
CPU to the canonical name for Cyclone, but leaves legacy support in so
that existing bitcode still compiles.
The file was modifiedllvm/unittests/Support/TargetParserTest.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64Subtarget.h
The file was modifiedllvm/lib/Target/AArch64/AArch64SystemOperands.td
The file was modifiedclang/lib/Driver/ToolChains/Arch/AArch64.cpp
The file was modifiedclang/test/Preprocessor/aarch64-target-features.c
The file was modifiedllvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll
The file was modifiedclang/test/Driver/aarch64-cpus.c
The file was modifiedllvm/include/llvm/Support/AArch64TargetParser.def
The file was modifiedllvm/lib/Target/AArch64/AArch64.td
The file was modifiedllvm/lib/Target/AArch64/AArch64Subtarget.cpp
The file was modifiedclang/test/Driver/arm64-as.s
Commit b212eb7159b40c98b3c40619b82b996fb903282b by kadircet
Revert "[InstCombine] fold zext of masked bit set/clear"
This reverts commit a041c4ec6f7aa659b235cb67e9231a05e0a33b7d.
This looks like a non-trivial change and there has been no code reviews
(at least there were no phabricator revisions attached to the commit
description). It is also causing a regression in one of our downstream
integration tests, we haven't been able to come up with a minimal
reproducer yet.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
The file was modifiedllvm/test/Transforms/InstCombine/zext.ll
Commit dfeb8730e24c5a4493e9092907b7ff083fae43a5 by th3charlie
[llvm-symbolizer]Fix printing of malformed address values not passed via
stdin
Summary: relates https://bugs.llvm.org/show_bug.cgi?id=44443
Adding missing newline when printing bad input values.
Fix testcase
Reviewers: jhenderson
Reviewed By: jhenderson
Subscribers: rupprecht, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72313
The file was modifiedllvm/test/tools/llvm-symbolizer/sym.test
The file was modifiedllvm/test/tools/llvm-symbolizer/invalid-input-address.test
The file was modifiedllvm/tools/llvm-symbolizer/llvm-symbolizer.cpp
Commit 518597c1737646ea1f087c1fa43109f689adf7a6 by Raphael Isemann
[lldb] Remove default llvm::Triple argument from ClangASTContext
constructor
Creating an ASTContext with an unknown triple is rarely a good idea (as
usually all our ASTs have a valid triple that is either from the host or
the target) and the default argument makes it far to easy to implicitly
create such an AST. Let's remove it and force people to pass a triple.
The only place where we don't pass a triple is a
DWARFASTParserClangTests where we now just pass the host triple instead
(the test doesn't depend on any triple so this shouldn't change
anything).
The file was modifiedlldb/include/lldb/Symbol/ClangASTContext.h
The file was modifiedlldb/unittests/SymbolFile/DWARF/DWARFASTParserClangTests.cpp
Commit 96d2d96b03ff590867cd6578eb7f6d32770cbbf0 by sam.parker
[NFC][ARM] Update tests
Run the update_mir_test on some of the low-overhead loop tests.
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
Commit 1cf11a4c67a15ab5493ef424c898accf49012caa by a.v.lapshin
[Dsymutil][Debuginfo][NFC] Reland: Refactor dsymutil to separate DWARF
optimizing part. #2.
Summary: This patch relands D71271. The problem with D71271 is that it
has cyclic dependency: CodeGen->AsmPrinter->DebugInfoDWARF->CodeGen. To
avoid cyclic dependency this patch puts implementation for
DWARFOptimizer into separate library: lib/DWARFLinker.
Thus the difference between this patch and D71271 is in that
DWARFOptimizer renamed into DWARFLinker and it`s files are put into
lib/DWARFLinker.
Reviewers: JDevlieghere, friss, dblaikie, aprantl
Reviewed By: JDevlieghere
Subscribers: thegameg, merge_guards_bot, probinson, mgorny, hiraditya,
llvm-commits
Tags: #llvm, #debug-info
Differential Revision: https://reviews.llvm.org/D71839
The file was addedllvm/tools/dsymutil/DwarfLinkerForBinary.h
The file was addedllvm/include/llvm/DWARFLinker/DWARFLinkerCompileUnit.h
The file was addedllvm/lib/DWARFLinker/DWARFLinker.cpp
The file was removedllvm/tools/dsymutil/CompileUnit.h
The file was removedllvm/tools/dsymutil/DeclContext.cpp
The file was modifiedllvm/tools/dsymutil/CMakeLists.txt
The file was modifiedllvm/tools/dsymutil/DwarfStreamer.cpp
The file was modifiedllvm/tools/dsymutil/LLVMBuild.txt
The file was addedllvm/lib/DWARFLinker/DWARFLinkerCompileUnit.cpp
The file was modifiedllvm/lib/LLVMBuild.txt
The file was addedllvm/tools/dsymutil/DwarfLinkerForBinary.cpp
The file was addedllvm/include/llvm/DWARFLinker/DWARFLinkerDeclContext.h
The file was modifiedllvm/lib/CMakeLists.txt
The file was addedllvm/lib/DWARFLinker/DWARFLinkerDeclContext.cpp
The file was modifiedllvm/include/llvm/CodeGen/NonRelocatableStringpool.h
The file was removedllvm/tools/dsymutil/CompileUnit.cpp
The file was addedllvm/include/llvm/DWARFLinker/DWARFLinker.h
The file was removedllvm/tools/dsymutil/DeclContext.h
The file was modifiedllvm/lib/CodeGen/NonRelocatableStringpool.cpp
The file was removedllvm/tools/dsymutil/DwarfLinker.h
The file was addedllvm/lib/DWARFLinker/CMakeLists.txt
The file was addedllvm/lib/DWARFLinker/LLVMBuild.txt
The file was removedllvm/tools/dsymutil/DwarfLinker.cpp
The file was modifiedllvm/tools/dsymutil/DwarfStreamer.h
Commit 111ec8c2a435440a72904aeca22c9f3046de5f42 by thakis
[gn build] (manually) merge 1cf11a4c67a15
The file was addedllvm/utils/gn/secondary/llvm/lib/DWARFLinker/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/tools/dsymutil/BUILD.gn
Commit 55a51e1c79a21080289ba88d5eac4bbe54ec4272 by aaron
Disallow an empty string literal in an asm label
An empty string literal in an asm label does not make a whole lot of
sense. GCC does not diagnose such a construct, but it also generates
code that cannot be assembled by gas should two symbols have an empty
asm label within the same TU. This does not affect an asm statement with
an empty string literal, which is still a useful construct.
The file was modifiedclang/include/clang/Basic/DiagnosticParseKinds.td
The file was modifiedclang/lib/Parse/ParseDeclCXX.cpp
The file was modifiedclang/lib/Parse/ParseExprCXX.cpp
The file was modifiedclang/test/CodeGen/asm-label.c
The file was modifiedclang/include/clang/Parse/Parser.h
The file was modifiedclang/test/AST/ast-print-attr.c
The file was modifiedclang/lib/Parse/Parser.cpp
The file was modifiedclang/lib/Parse/ParseDecl.cpp
The file was modifiedclang/test/Parser/asm.c
The file was modifiedclang/lib/Parse/ParseStmtAsm.cpp
Commit 346f6b54bd1237a9a5a2d9bb1e424b57dc178998 by anna.welker
[ARM][MVE] Enable masked gathers from vector of pointers
Adds a pass to the ARM backend that takes a v4i32 gather and transforms
it into a call to MVE's masked gather intrinsics.
Differential Revision: https://reviews.llvm.org/D71743
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was addedllvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was addedllvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll
The file was addedllvm/test/CodeGen/Thumb2/mve-gather-ind32-scaled.ll
The file was addedllvm/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll
The file was modifiedllvm/lib/Target/ARM/CMakeLists.txt
The file was modifiedllvm/lib/Target/ARM/ARMTargetMachine.cpp
The file was addedllvm/test/CodeGen/Thumb2/mve-gather-ind32-unscaled.ll
The file was modifiedllvm/lib/Target/ARM/ARM.h
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.h
Commit 26ac7923e7df982081e726bb2856fadb35d6d35d by llvmgnsyncbot
[gn build] Port 346f6b54bd1
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/ARM/BUILD.gn
Commit 7a77ad144694ced7b553c644bcbcbfffac2b5fe1 by aaron
Fixing a formatting nit; NFC
The file was modifiedclang/lib/ASTMatchers/Dynamic/Registry.cpp
Commit b2c2fe72197267af90b4b6a187ab6163f806ce00 by qiucofan
[NFC] Move InPQueue into arguments of releaseNode
This patch moves `InPQueue` into function arguments instead of template
arguments of `releaseNode`, which is a cleaner approach.
Differential Revision: https://reviews.llvm.org/D72125
The file was modifiedllvm/include/llvm/CodeGen/MachineScheduler.h
The file was modifiedllvm/lib/CodeGen/MachineScheduler.cpp
Commit 8e2b44f7e0641d3776021163ee6a77089cca9cdc by mikael.holmen
[Intrinsic] Add fixed point division intrinsics.
Summary: This patch adds intrinsics and ISelDAG nodes for signed and
unsigned fixed-point division:
  llvm.sdiv.fix.*
llvm.udiv.fix.*
These intrinsics perform scaled division on two integers or vectors of
integers. They are required for the implementation of the Embedded-C
fixed-point arithmetic in Clang.
Patch by: ebevhan
Reviewers: bjope, leonardchan, efriedma, craig.topper
Reviewed By: craig.topper
Subscribers: Ka-Ka, ilya, hiraditya, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70007
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
The file was modifiedllvm/include/llvm/CodeGen/ISDOpcodes.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/include/llvm/IR/Intrinsics.td
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
The file was addedllvm/test/CodeGen/X86/sdiv_fix.ll
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was modifiedllvm/docs/LangRef.rst
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
The file was addedllvm/test/CodeGen/X86/udiv_fix.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
Commit ba129c7d0f5c7c32398ad708c88e14cb06a339ad by abpostelnicu
[clang-tidy] Disable match on `if constexpr` statements in template
instantiation for `readability-misleading-indentation` check.
Summary: Fixes fixes `readability-misleading-identation` for `if
constexpr`. This is very similar to D71980.
Reviewers: alexfh
Subscribers: xazax.hun, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72333
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/readability-misleading-indentation.cpp
The file was modifiedclang-tools-extra/clang-tidy/readability/MisleadingIndentationCheck.cpp
Commit 3100480925df10960c1e0a077dd9875037d3fe29 by simon.tatham
[ARM,MVE] Intrinsics for partial-overwrite imm shifts.
This batch of intrinsics covers two sets of immediate shift
instructions, which have in common that they only overwrite part of
their output register and so they need an extra input giving its
previous value.
The VSLI and VSRI instructions shift each lane of the input vector left
or right just as if they were normal immediate VSHL/VSHR, but then they
only overwrite the output bits that correspond to actual shifted bits of
the input. So VSLI will leave the low n bits of each output lane
unchanged, and VSRI the same with the top n bits.
The V[Q][R]SHR[U]N family are all narrowing shifts: they take an input
vector of 2n-bit integers, shift each lane right by a constant, and then
narrowing the shifted result to only n bits. So they only overwrite half
of the n-bit lanes in the output register, and the B/T suffix indicates
whether it's the bottom or top half of each 2n-bit lane.
I've implemented the whole of the latter family using a single IR
intrinsic `vshrn`, which takes a lot of i32 parameters indicating which
instruction it expands to (by specifying signedness of the input and
output types, whether it saturates and/or rounds, etc).
Reviewers: dmgreen, MarkMurrayARM, miyuki, ostannard
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D72328
The file was addedllvm/test/CodeGen/Thumb2/mve-intrinsics/vector-shift-imm-dyadic.ll
The file was modifiedclang/include/clang/Basic/arm_mve.td
The file was modifiedclang/include/clang/Basic/arm_mve_defs.td
The file was addedclang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
The file was modifiedclang/utils/TableGen/MveEmitter.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsARM.td
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
Commit dac7b23cc3efbb4ccb6a9ea101f367f866f334e2 by simon.tatham
[ARM,MVE] Intrinsics for variable shift instructions.
This batch of intrinsics fills in all the shift instructions that take a
variable shift distance in a register, instead of an immediate. Some of
these instructions take a single shift distance in a scalar register and
apply it to all lanes; others take a vector of per-lane distances.
These instructions are all basically one family, varying in whether they
saturate out-of-range values, and whether they round when bits are
shifted off the bottom. I've implemented them at the IR level by a much
smaller family of IR intrinsics, which take flag parameters to indicate
saturating and/or rounding (along with the usual one to specify
signed/unsigned integers).
An oddity is that all of them are //left// shift instructions – but if
you pass a negative shift count, they'll shift right. So the vector
shift distances are always vectors of //signed// integers, regardless of
whether you're considering the other input vector to be of signed or
unsigned. Also, even the simplest `vshlq` instruction in this family
(neither saturating nor rounding) has to be implemented as an IR
intrinsic, because the ordinary LLVM IR `shl` operation would consider
an out-of-range shift count to be undefined behavior.
Reviewers: dmgreen, MarkMurrayARM, miyuki, ostannard
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D72329
The file was modifiedllvm/include/llvm/IR/IntrinsicsARM.td
The file was modifiedclang/include/clang/Basic/arm_mve.td
The file was modifiedclang/include/clang/Basic/arm_mve_defs.td
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was addedllvm/test/CodeGen/Thumb2/mve-intrinsics/vector-shift-var.ll
The file was addedclang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
Commit ead815924e6ebeaf02c31c37ebf7a560b5fdf67b by kazu
[JumpThreading] Thread jumps through two basic blocks
Summary: This patch teaches JumpThreading.cpp to thread through two
basic blocks like:
  bb3:
   %var = phi i32* [ null, %bb1 ], [ @a, %bb2 ]
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %bb4, label ...
  bb4:
   %cmp = icmp eq i32* %var, null
   br i1 %cmp, label bb5, label bb6
by duplicating basic blocks like bb3 above.  Once we duplicate bb3 as
bb3.dup and redirect edge bb2->bb3 to bb2->bb3.dup, we have:
  bb3:
   %var = phi i32* [ @a, %bb2 ]
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %bb4, label ...
  bb3.dup:
   %var = phi i32* [ null, %bb1 ]
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %bb4, label ...
  bb4:
   %cmp = icmp eq i32* %var, null
   br i1 %cmp, label bb5, label bb6
Then the existing code in JumpThreading.cpp can thread edge bb3.dup->bb4
through bb4 and eventually create bb3.dup->bb5.
Reviewers: wmi
Subscribers: hiraditya, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70247
The file was addedllvm/test/Transforms/JumpThreading/thread-two-bbs1.ll
The file was addedllvm/test/Transforms/JumpThreading/thread-two-bbs2.ll
The file was modifiedllvm/include/llvm/Transforms/Scalar/JumpThreading.h
The file was modifiedllvm/lib/Transforms/Scalar/JumpThreading.cpp
Commit c74a8adda3bc4fc5714aef14cdcfda944d3038a0 by a.bataev
[OPENMP]Allow comma in combiner expression.
Use ParseExpression() instead of ParseAssignmentExpression() to allow
commas in combiner expressions.
The file was modifiedclang/lib/Parse/ParseOpenMP.cpp
The file was modifiedclang/test/OpenMP/declare_reduction_ast_print.cpp
Commit 780ba1f22b53116918cf12decccaed7ba2292bd5 by spatel
[DAGCombiner] clean up extract-of-concat fold; NFC
This hopes to improve readability and adds an assert. The functional
change noted by the TODO comment is proposed in: D72361
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 5dfd52398f5c1b67024106febdc68e6b12f8ad37 by spatel
[InstCombine] Adding testcase for Z / (1.0 / Y) => (Y * Z); NFC
The added testcase shows the current transformation for the operation Z
/ (1.0 / Y), which remains unchanged. This will be updated to align with
the transformed code (Y * Z) with D72319.
The existing transformation Z / (X / Y) => (Y * Z) / X is not handling
this case as there are multiple uses for (1.0 / Y) in this testcase.
Patch by: @raghesh (Raghesh Aloor)
Differential Revision: https://reviews.llvm.org/D72388
The file was modifiedllvm/test/Transforms/InstCombine/fdiv.ll
Commit 108279948de31eba4f212b2a4715030b9d471c9e by llvm-dev
[SelectionDAG] Use llvm::Optional<APInt> for FoldValue.
Use llvm::Optional<APInt> instead of std::pair<APInt, bool> with the
bool second being used to report success/failure of fold.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit 07a569a0539a12700401b8f4221af0a58f28a654 by michael.hliao
[amdgpu] Remove unused header. NFC.
The file was modifiedllvm/lib/Target/AMDGPU/SIFoldOperands.cpp
Commit bbbbf8a1065e9420e3cc7c958897683e84023075 by Jonas Devlieghere
[lldb/CMake] Use LLDB's autodetection logic for libxml2
Libxml2 is already an optional dependency. It should use the same
infrastructure as the other dependencies.
Differential revision: https://reviews.llvm.org/D72290
The file was modifiedlldb/cmake/modules/LLDBConfig.cmake
The file was modifiedlldb/docs/resources/build.rst
Commit 5936717fa6537812257990143e2384bb78486ef9 by llvm-dev
Fix "pointer is null" static analyzer warning. NFCI.
Use castAs<> instead of getAs<> since we know that the pointer will be
valid (and is dereferenced immediately below).
The file was modifiedclang/lib/CodeGen/CGOpenCLRuntime.cpp
Commit 19bfb6d8df6c23c8c8d19af9221d12bf08244b51 by llvm-dev
Fix "pointer is null" static analyzer warning. NFCI.
Use cast<> instead of dyn_cast<> since we know that the pointer should
be valid (and is dereferenced immediately below in the getSignature
call).
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
Commit 46e2f89364ce24a06953d08c78218fb5548a9fa3 by llvm-dev
[MC] writeFragment - assert MCFragment::FT_Fill length is legal.
Silence (clang/MSVC) static analyzer warnings that the fragment data may
either write out of bounds of the local array or reference uninitialized
data.
The file was modifiedllvm/lib/MC/MCAssembler.cpp
Commit 96e2376d02f0840e82b96314108660ecabe63c7f by maskray
[ELF] Don't special case weak symbols for pie with no shared objects
D59275 added the following clause to Symbol::includeInDynsym()
  if (isUndefWeak() && Config->Pie && SharedFiles.empty())
   return false;
D59549 explored the possibility to generalize it for -no-pie.
GNU ld's rules are architecture dependent and partly controlled by -z
{,no-}dynamic-undefined-weak. Our attempts to mimic its rules are
actually half-baked and don't provide perceivable benefits (it can save
a few more weak undefined symbols in .dynsym in a -static-pie
executable). Let's just delete the rule for simplicity. We will expect
cosmetic inconsistencies with ld.bfd in certain -static-pie scenarios.
This permits a simplification in D71795.
Reviewed By: peter.smith
Differential Revision: https://reviews.llvm.org/D71794
The file was removedlld/test/ELF/weak-undef-no-shared-libs.s
The file was modifiedlld/ELF/Symbols.cpp
The file was modifiedlld/test/ELF/ppc32-weak-undef-call.s
Commit b841e119d77ed0502e3a2e710f26a899bef28b3c by maskray
[ELF] Delete an unused special rule from isStaticLinkTimeConstant. NFC
Weak undefined symbols are preemptible after D71794.
  if (sym.isPreemptible)
   return false;
if (!config->isPic)
   return true;
// isPic means includeInDynsym is true after D71794.
  ...
  // We can delete this if because it can never be true.
if (sym.isUndefWeak)
   return true;
Differential Revision: https://reviews.llvm.org/D71795
The file was modifiedlld/ELF/Relocations.cpp
Commit 29ccb12e2c12b6a50a1451ffdbf70fef29efda0e by listmail
[BranchAlign] Compiler support for suppressing branch align
As discussed heavily in the original review (D70157), there's a need for
the compiler to be able to selective suppress padding (either nop or
prefix) to respect assumptions about the meaning of labels and
instructions in generated code.
Rather than wait for syntax to be finalized - which appears to be a very
slow process - this patch focuses on the compiler use case and *only*
worries about the integrated assembler. To my knowledge, this covers all
cases mentioned to date for clang/JIT support.
For testing purposes, I wired it up so that if the integrated assembler
was using autopadding for branch alignment (e.g. enabled at command
line) then the textual assembly output would contain a comment for each
location where padding was enabled or disabled. This seemed like the
least painful choice overall.
Note that the result of this patch effective disables the jcc errata
mitigation for many constructs (statepoints, implicit null checks, xray,
etc...) which is non ideal. It is at least *correct* and should allow us
to enable the mitigation for the compiler. Once that's done, and a few
other items are worked through, we probably want to come back to this an
explore a bundling based approach instead so that we can pad
instructions while keeping labels in the right place.
Differential Revision: https://reviews.llvm.org/D72303
The file was modifiedllvm/lib/Target/X86/X86MCInstLower.cpp
The file was modifiedllvm/lib/MC/MCAsmStreamer.cpp
The file was modifiedllvm/include/llvm/MC/MCAsmBackend.h
The file was addedllvm/test/CodeGen/X86/align-branch-boundary-suppressions.ll
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
The file was addedllvm/test/CodeGen/X86/align-branch-boundary-noautopadding.ll
The file was modifiedllvm/include/llvm/MC/MCStreamer.h
The file was modifiedllvm/lib/MC/MCObjectStreamer.cpp
Commit d60b3b4817cb9346b682bb75371c41642c273b13 by craig.topper
[X86] Add isel patterns for bitcasting between v32i1/v64i1 and
float/double.
We have to do an intermediate jump to a GPR to make the cast.
Fixes PR43750.
The file was modifiedllvm/test/CodeGen/X86/avx512bw-mask-op.ll
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td
Commit 3811417f39a7d0a370fac2923060f5ef8dacd8d7 by craig.topper
[X86] Custom type legalize v4i64->v4f32 uint_to_fp on sse4.1 targets in
64-bit mode
For v4i64->v4f32 uint_to_fp on pre-avx targets where v4i64 isn't legal
we create to v2i64->v2f32 uint_to_fp that need to be shuffled together.
Our codegen for v2i64->v2f32 involves detecting if the number is larger
than (2^31 - 1), if so we do a special divison by 2 so we can do a
signed conversion which we need to scalarize, then do a multiply by 2 at
the end if we divided earlier.
When v4i64 isn't legal we need to split the checking for a larger number
and dividing by 2 into two v2i64 vectors. The scalar part can extract
the 4 i64 values from those 4 splits. But we can reassemble the 4 scalar
f32 results directly into a single v432 vector. Then we just need to
combine the fixup indications from the 2 halves and we can do the final
multiply by 2 fixup on all 4 values if needed at once using a single
v4f32 blend and v4f32 fadd.
Differential Revision: https://reviews.llvm.org/D72368
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vec_int_to_fp.ll
Commit 766ce87e9bed89bc3b5c2c904f1eb2d10be0d3be by ntv
[mlir][Linalg] Lower linalg.reshape to LLVM for the static case
Summary: This diff adds lowering of the linalg.reshape op to LLVM.
A new descriptor is created with fields initialized as follows: 1.
allocatedPTr, alignedPtr and offset are copied from the source
descriptor 2. sizes are copied from the static destination shape 3.
strides are copied from the static strides collected with
`getStridesAndOffset`
Only the static case in which the target view conforms to strided memref
semantics is supported. Other cases are left for future work and will be
added on a per-need basis.
Reviewers: ftynse, mravishankar
Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen,
antiagainst, arpith-jacob, mgester, lucyrfox, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72316
The file was modifiedmlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp
The file was modifiedmlir/test/Dialect/Linalg/llvm.mlir
Commit 659f7d463b3d677823fdcfddc37eea481078c514 by riverriddle
[mlir] NFC: Move the state for managing aliases out of ModuleState and
into a new class AliasState.
Summary: This reduces the complexity of ModuleState and simplifies the
code. A future revision will mold ModuleState into something that can be
used by users for caching of printer state, as well as for implementing
printAsOperand style methods.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D72292
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
Commit 0a01ec972d2e24c721f46e55210d42391ae52b70 by abpostelnicu
[clang-tidy] Remove broken test on Windows for
`readability-misleading-indentation`. Because Windows build uses by
default `fdelayed-template-parsing` we cannot have a test where we don't
instantiate the template. Please see D72333.
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/readability-misleading-indentation.cpp
Commit 48b14e58abc57cfea7bcdc0d7165686f135a2ebd by stilis
[MLIR] Fix ML IR build on Windows with Visual Studio
Summary: Right now the path for each lib in whole_archive_link when MSVC
is used as the compiler is not a full path - and it's not even the
correct path when VS is used to build. This patch sets the lib path to a
full path using CMAKE_CFG_INTDIR which means the path will be correct
regardless of whether ninja, make or VS is used and it will always be a
full path.
Reviewers: denis13, jpienaar
Reviewed By: jpienaar
Subscribers: mgorny, mehdi_amini, rriddle, jpienaar, burmako, shauheen,
antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox,
llvm-commits, asmith
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72403
The file was modifiedmlir/CMakeLists.txt
Commit ba181d0063e43fb56938555112ab859f48aee287 by listmail
[X86] Keep cl::opts at top of file [NFC]
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
Commit b675a7628ce6a21b1e4a71c079a67badfb8b073d by eugenis
Merge memtag instructions with adjacent stack slots.
Summary: Detect a run of memory tagging instructions for adjacent stack
frame slots, and replace them with a shorter instruction sequence
* replace STG + STG with ST2G
* replace STGloop + STGloop with STGloop
This code needs to run when stack slot offsets are already known, but
before FrameIndex operands in STG instructions are eliminated; that's
the reason for the new hook in PrologueEpilogue.
This change modifies STGloop and STZGloop pseudos to take the size as an
immediate integer operand, and base address as a FI operand when
possible. This is needed to simplify recognizing an STGloop instruction
as operating on a stack slot post-regalloc.
This improves memtag code size by ~0.25%, and it looks like an
additional ~0.1% is possible by rearranging the stack frame such that
consecutive STG instructions reference adjacent slots (patch pending).
Reviewers: pcc, ostannard
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70286
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
The file was modifiedllvm/test/CodeGen/AArch64/stack-tagging-unchecked-ld-st.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.h
The file was modifiedllvm/test/CodeGen/AArch64/settag.ll
The file was addedllvm/test/CodeGen/AArch64/settag-merge.ll
The file was modifiedllvm/lib/CodeGen/PrologEpilogInserter.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
The file was addedllvm/test/CodeGen/AArch64/settag-merge.mir
The file was modifiedllvm/include/llvm/CodeGen/TargetFrameLowering.h
Commit 2823e91d55891e33a7a8b9a4016db4ec9e2765ae by aaron
Add a new AST matcher 'optionally'.
This matcher matches any node and at the same time executes all its
inner matchers to produce any possbile result bindings.
This is useful when a user wants certain supplementary information
that's not always present along with the main match result.
The file was modifiedclang/lib/ASTMatchers/ASTMatchersInternal.cpp
The file was modifiedclang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp
The file was modifiedclang/docs/LibASTMatchersReference.html
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchers.h
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchersInternal.h
The file was modifiedclang/lib/ASTMatchers/Dynamic/Registry.cpp
Commit 43f938eddc8a5c8e12c116ca5f31df5a6fead24e by tejohnson
LTOVisibility.rst: fix up syntax in example
Summary: Pretty self-evident. This example was missing an lparen. Added
it, and fixed up the ASCII art.
Patch by Nick Black <dankamongmen@gmail.com>
Reviewers: pcc
Reviewed By: pcc
Subscribers: tejohnson, mehdi_amini, inglorion, hiraditya, steven_wu,
dexonsmith, cfe-commits
Tags: #llvm, #clang
Differential Revision: https://reviews.llvm.org/D70765
The file was modifiedclang/docs/LTOVisibility.rst
Commit 31992a69b808f30a46a4ddb6da0d073d528bc72e by spatel
[x86] add test for concat-extract corner case; NFC
See D72361 for discussion.
The file was modifiedllvm/test/CodeGen/X86/extract-concat.ll
Commit 1e25109f93ffe5b28b28a2359e69143b7fb4aa5f by ataei
Canonicalize static alloc followed by memref_cast and std.view
Summary: Rewrite alloc, memref_cast, std.view into allo, std.view by
droping memref_cast.
Reviewers: nicolasvasilache
Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen,
antiagainst, arpith-jacob, mgester, lucyrfox, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72379
The file was modifiedmlir/lib/Dialect/StandardOps/Ops.cpp
The file was modifiedmlir/test/Transforms/canonicalize.mlir
Commit 78ce19b7e1dc521fa8ac8300823d52d619d4e93e by martin
[LLD] [COFF] Fix post-commit suggestions for absolute symbol equality
Differential Revision: https://reviews.llvm.org/D72252
The file was modifiedlld/COFF/SymbolTable.cpp
The file was modifiedlld/COFF/Symbols.h
The file was modifiedlld/test/COFF/duplicate-absolute-same.s
Commit 0b8ce37d64747ba7d8908626256e2b5e58f7b396 by spatel
[InstSimplify] add tests for select of true/false; NFC
The file was modifiedllvm/test/Transforms/InstSimplify/select.ll
Commit 0341c11e08504acef8c16ab07210bc253dadf2d9 by Jonas Devlieghere
[lldb/SWIG] Refactor extensions to be non Python-specific
The current SWIG extensions for the string conversion operator is Python
specific because it uses the PythonObjects. This means that the code
cannot be reused for other SWIG supported languages such as Lua.
This reimplements the extensions in a more generic way that can be
reused.
Differential revision: https://reviews.llvm.org/D72377
The file was modifiedlldb/scripts/Python/python-extensions.swig
The file was modifiedlldb/scripts/lldb.swig
The file was modifiedlldb/scripts/interface/SBTarget.i
The file was modifiedlldb/scripts/lldb_lua.swig
Commit 2d258ed931cdf47a7d1dcf08ad963b5452a8670f by kazu
Revert "[JumpThreading] Thread jumps through two basic blocks"
It looks like my patch breaks the sanitizer-windows build:
http://lab.llvm.org:8011/builders/sanitizer-windows/builds/56324
This reverts commit ead815924e6ebeaf02c31c37ebf7a560b5fdf67b.
The file was removedllvm/test/Transforms/JumpThreading/thread-two-bbs1.ll
The file was modifiedllvm/include/llvm/Transforms/Scalar/JumpThreading.h
The file was modifiedllvm/lib/Transforms/Scalar/JumpThreading.cpp
The file was removedllvm/test/Transforms/JumpThreading/thread-two-bbs2.ll
Commit edadb818e5be005fa4397b7e4bd5e397ddb4f5d6 by Jonas Devlieghere
[lldb/CMake] Only auto-enable Lua when SWIG is found
Just like Python, Lua should only be auto-enabled if SWIG is found as
well. This moves the logic of finding SWIG and Lua as a whole into a new
CMake package.
The file was addedlldb/cmake/modules/FindLuaAndSwig.cmake
The file was modifiedlldb/cmake/modules/LLDBConfig.cmake
Commit 28b9cdd26073c79be36c79476a9bacceca3d116f by Adrian Prantl
Delete dead code.
https://reviews.llvm.org/D58856
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
Commit 58deb20dd2dfbfbfff8097ce80137d12a57a3607 by eugenis
Revert "Merge memtag instructions with adjacent stack slots."
*** Bad machine code: Tied use must be a register ***
- function:    stg_alloca17
- basic block: %bb.0 entry (0x20076710580)
- instruction: early-clobber %0:gpr64common, early-clobber %1:gpr64sp =
STGloop 272, %stack.0.a :: (store 272 into %ir.a, align 16)
- operand 3:   %stack.0.a
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/21481/steps/test-check-all/logs/stdio
This reverts commit b675a7628ce6a21b1e4a71c079a67badfb8b073d.
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.h
The file was modifiedllvm/include/llvm/CodeGen/TargetFrameLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
The file was modifiedllvm/test/CodeGen/AArch64/settag.ll
The file was modifiedllvm/test/CodeGen/AArch64/stack-tagging-unchecked-ld-st.ll
The file was removedllvm/test/CodeGen/AArch64/settag-merge.mir
The file was modifiedllvm/lib/CodeGen/PrologEpilogInserter.cpp
The file was removedllvm/test/CodeGen/AArch64/settag-merge.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
Commit f84d3200528a4aa1e8c7f2d3a9567f63f855b165 by ataei
[MLIR] Don't use SSA names directly for std.view canonicalization test
Reviewers: rriddle, nicolasvasilache
Subscribers: mehdi_amini, jpienaar, burmako, shauheen, antiagainst,
arpith-jacob, mgester, lucyrfox, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72408
The file was modifiedmlir/test/Transforms/canonicalize.mlir
Commit 7f1026a7520eb3d7e99da77f6738deb72de17980 by maskray
[cfi][test] cross-dso/stats.cpp: don't assume the order of static
constructors
__sanitizer_stat_init is called for the executable first, then the
shared object. In WriterModuleReport(), the information for the shared
object will be recorded first. It'd be nice to get rid of the order
requirement of static constructors. (This should make .ctors platforms
work.)
The file was modifiedcompiler-rt/test/cfi/cross-dso/stats.cpp
Commit ae47a3d8107856c84c104f3c2e43a553f4e36748 by Jonas Devlieghere
[lldb/SWIG] Refactor extensions to be non Python-specific (2/2)
The current SWIG extensions for the string conversion operator is Python
specific because it uses the PythonObjects. This means that the code
cannot be reused for other SWIG supported languages such as Lua.
This reimplements the extensions in a more generic way that can be
reused. It uses a SWIG macro to reduce code duplication.
Differential revision: https://reviews.llvm.org/D72377
The file was modifiedlldb/scripts/interface/SBMemoryRegionInfo.i
The file was modifiedlldb/scripts/interface/SBData.i
The file was modifiedlldb/scripts/interface/SBCompileUnit.i
The file was modifiedlldb/scripts/interface/SBFunction.i
The file was modifiedlldb/scripts/interface/SBModule.i
The file was modifiedlldb/scripts/interface/SBBreakpointName.i
The file was modifiedlldb/scripts/interface/SBTarget.i
The file was modifiedlldb/scripts/interface/SBInstruction.i
The file was modifiedlldb/scripts/lldb.swig
The file was modifiedlldb/scripts/interface/SBAddress.i
The file was modifiedlldb/scripts/interface/SBBlock.i
The file was modifiedlldb/scripts/interface/SBLineEntry.i
The file was modifiedlldb/scripts/Python/python-extensions.swig
The file was modifiedlldb/scripts/interface/SBInstructionList.i
The file was modifiedlldb/scripts/interface/SBFrame.i
The file was modifiedlldb/scripts/interface/SBBreakpointLocation.i
The file was modifiedlldb/scripts/interface/SBDebugger.i
The file was modifiedlldb/scripts/lldb_lua.swig
The file was modifiedlldb/scripts/interface/SBDeclaration.i
The file was modifiedlldb/scripts/interface/SBCommandReturnObject.i
The file was modifiedlldb/scripts/interface/SBBreakpoint.i
The file was modifiedlldb/scripts/interface/SBFileSpec.i
The file was addedlldb/scripts/macros.swig
The file was modifiedlldb/scripts/interface/SBError.i
The file was modifiedlldb/scripts/interface/SBModuleSpec.i
Commit ee57469a5128a5cd4f8b13945c873d3421a4b3d0 by paulsson
[X86]  Remove EFLAGS from live-in lists in X86FlagsCopyLowering.
When EFLAGS is no longer live into a basic block, remove it from the
live-in list.
Fixes https://bugs.llvm.org/show_bug.cgi?id=44462.
Review: Craig Topper
Differential Revision: https://reviews.llvm.org/D71375
The file was addedllvm/test/CodeGen/X86/copy-eflags-liveinlists.mir
The file was modifiedllvm/lib/Target/X86/X86FlagsCopyLowering.cpp
Commit b2fb6a7ba118f651cc76580ecb48eb5f877920aa by xazax
[NFC] Whitespace fixes
The file was modifiedclang/include/clang/Basic/AttrDocs.td
The file was modifiedclang/include/clang/Basic/Attr.td
Commit 85ee4ff4e474788abc7abdc939114281c2a68ec1 by bion
[libcxx] [test] Disable refwrap/weak_result.pass.cpp in C++20 mode
(broken by P0357R3)
The file was modifiedlibcxx/test/std/utilities/function.objects/refwrap/weak_result.pass.cpp
Commit 659efa21f1b3eded304b7239b356eecf1f5034ae by paulsson
Recommit "[MachineVerifier] Improve verification of live-in lists."
MachineVerifier::visitMachineFunctionAfter() is extended to check the
live-through case for live-in lists. This is only done for registers
without aliases and that are neither allocatable or reserved, such as
the SystemZ::CC register.
The MachineVerifier earlier only catched the case of a live-in use
without an entry in the live-in list (as "using an undefined physical
register").
A comment in LivePhysRegs.h has been added stating a guarantee that
addLiveOuts() can be trusted for a full register both before and after
register allocation.
Review: Quentin Colombet
Differential Revision: https://reviews.llvm.org/D68267
The file was addedllvm/test/MachineVerifier/live-ins-02.mir
The file was modifiedllvm/include/llvm/CodeGen/LivePhysRegs.h
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp
The file was addedllvm/test/MachineVerifier/live-ins-03.mir
The file was addedllvm/test/MachineVerifier/live-ins-01.mir
Commit ff0311c4b3b9dce9d25d08e38aa163682b155513 by chmeeedalf
[PowerPC]: Add powerpcspe target triple subarch component
Summary: This allows the use of '-target powerpcspe-unknown-linux-gnu'
or
'powerpcspe-unknown-freebsd' to be used, instead of
'-target powerpc-unknown-linux-gnu -mspe'.
Reviewed By: dim Differential Revision: https://reviews.llvm.org/D72014
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.cpp
The file was modifiedllvm/lib/Support/Triple.cpp
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
The file was modifiedclang/test/Preprocessor/init.c
The file was modifiedclang/lib/Basic/Targets/PPC.h
The file was modifiedllvm/include/llvm/ADT/Triple.h
The file was modifiedllvm/unittests/ADT/TripleTest.cpp
Commit 76aab66d34446ccf764cf8127b73e1517df75fb4 by mtrofin
[NFC][InlineCost] Factor cost modeling out of CallAnalyzer traversal.
Summary: The goal is to simplify experimentation on the cost model.
Today, CallAnalyzer decides 2 things: legality, and benefit. The
refactoring keeps legality assessment in CallAnalyzer, and factors
benefit evaluation out, as an extension.
Reviewers: davidxl, eraman
Subscribers: kamleshbhalui, fedor.sergeev, hiraditya,
baloghadamsoftware, haicheng, a.sidorin, Szelethus, donat.nagy, dkrupp,
llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71733
The file was modifiedllvm/lib/Analysis/InlineCost.cpp
Commit 1e46eb74be6527377e47090bbe0fc9298f7de2c5 by johannes
[Attributor][FIX] Avoid dangling value pointers during code modification
When we replace instructions with unreachable we delete instructions. We
now avoid dangling pointers to those deleted instructions in the
`ToBeChangedToUnreachableInsts` set. Other modification collections
might need to be updated in the future as well.
The file was modifiedllvm/include/llvm/IR/ValueHandle.h
The file was modifiedllvm/test/Transforms/Attributor/undefined_behavior.ll
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
Commit a4088c75cc1034307400076d29b35905d0ae58b2 by johannes
[Attributor][FIX] Carefully change invokes to calls (after manifest)
Before we manually inserted unreachable early but that could lead to
broken PHI nodes. Now we use the existing late modification
functionality.
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
The file was modifiedllvm/test/Transforms/Attributor/IPConstantProp/recursion.ll
The file was modifiedllvm/test/Transforms/Attributor/IPConstantProp/return-constant.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/nonzero-address-spaces.ll
The file was modifiedllvm/test/Transforms/Attributor/noreturn_async.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead.ll
The file was modifiedllvm/test/Transforms/Attributor/liveness.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/crash.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h
Commit 338a601612ca36e112b14f622eb310985b93192a by mtrofin
Revert "[NFC][InlineCost] Factor cost modeling out of CallAnalyzer
traversal."
This reverts commit 76aab66d34446ccf764cf8127b73e1517df75fb4.
Failure:
http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/20562,
will investigate and resubmit.
The file was modifiedllvm/lib/Analysis/InlineCost.cpp
Commit 26ba160d47220a0bce75b1f491bf6e262edf69fa by czhengsz
[PowerPC] when folding rlwinm+rlwinm. to andi., we should use first
rlwinm input reg.
%2:gprc = RLWINM %1:gprc, 27, 5, 10
%3:gprc = RLWINM_rec %2:gprc, 8, 5, 10, implicit-def $cr0
==>
%3:gprc = ANDI_rec %1, 0, implicit-def $cr0
we should use %1 instead of %2 as ANDI_rec input.
Reviewed By: steven.zhang
Differential Revision: https://reviews.llvm.org/D71885
The file was modifiedllvm/test/CodeGen/PowerPC/fold-rlwinm.mir
The file was modifiedllvm/lib/Target/PowerPC/PPCMIPeephole.cpp
Commit a63af915288ad9d1049d486833fcd085b620dc6d by apl
[lldb] Remove various dead Compare functions
The file was modifiedlldb/source/Core/Section.cpp
The file was modifiedlldb/source/Symbol/Function.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.cpp
The file was modifiedlldb/source/Symbol/Type.cpp
Commit be841f89d0014b1e0246a4feae941b2f74abd908 by daniel_l_sanders
[MIR] Target specific MIR formating and parsing
Summary: Added MIRFormatter for target specific MIR formating and
parsing with immediate and custom pseudo source values. Target machine
can subclass MIRFormatter and implement custom logic for printing and
parsing immediate and custom pseudo source values for better
readability.
* Target specific immediate mnemonic need to start with "." follows by
identifier string. When MIR parser sees immediate it will call target
specific parsing function.
* Custom pseudo source value need to start with custom follows by
double-quoted string. MIR parser will pass the quoted string to target
specific PSV parsing function.
* MIRFormatter have 2 helper functions to facilitate LLVM value printing
and parsing for custom PSV if they refers LLVM values.
Reviewers: dsanders, arsenm
Reviewed By: dsanders
Subscribers: wdng, jvesely, nhaehnle, hiraditya, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69836
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/lib/CodeGen/MIRParser/MIParser.cpp
The file was modifiedllvm/lib/CodeGen/MachineOperand.cpp
The file was modifiedllvm/include/llvm/Target/TargetMachine.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
The file was modifiedllvm/lib/CodeGen/MachineInstr.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
The file was modifiedllvm/include/llvm/CodeGen/MachineOperand.h
The file was addedllvm/include/llvm/CodeGen/MIRFormatter.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
The file was modifiedllvm/include/llvm/CodeGen/MIRParser/MIParser.h
The file was modifiedllvm/lib/CodeGen/MIRParser/MILexer.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
The file was modifiedllvm/include/llvm/CodeGen/PseudoSourceValue.h
The file was modifiedllvm/lib/CodeGen/MIRPrinter.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineMemOperand.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
The file was modifiedllvm/lib/Target/TargetMachine.cpp
The file was modifiedllvm/lib/CodeGen/MIRParser/MILexer.cpp
The file was modifiedllvm/unittests/CodeGen/MachineOperandTest.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
Commit d44a0743175fc781aa2a23d638d683ded6eb10b8 by Jason Molenda
Save more descriptive error msg from FBS/BKS, relay it up to lldb.
When lldb requests an app launch through FrontBoard/BackBoard, we get
back an NSError object if there was a problem with an integer error code
and a descriptive text string.  debugserver would log the descriptive
text string to the console, but it would only save the error code value,
ask for the much-less-specific name of that error code, and send that
very generic error word back to lldb.
This patch saves the longer description of the failure when available,
and sends that to lldb.  If unavailable, it falls back to sending up the
generic description of the error code as it was doing before.
This only impacts the iOS on-device debugserver.
<rdar://problem/49953304>
The file was modifiedlldb/tools/debugserver/source/MacOSX/MachProcess.mm
Commit 5ab6fa7b7011b00e8955168c5bbcb46e9712afa9 by daniel_l_sanders
Revert "[MIR] Target specific MIR formating and parsing"
Forgot to credit Peng in the commit message.
This reverts commit be841f89d0014b1e0246a4feae941b2f74abd908.
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
The file was modifiedllvm/include/llvm/CodeGen/PseudoSourceValue.h
The file was modifiedllvm/include/llvm/CodeGen/MachineMemOperand.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
The file was modifiedllvm/include/llvm/Target/TargetMachine.h
The file was modifiedllvm/lib/CodeGen/MIRPrinter.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
The file was modifiedllvm/unittests/CodeGen/MachineOperandTest.cpp
The file was removedllvm/include/llvm/CodeGen/MIRFormatter.h
The file was modifiedllvm/lib/CodeGen/MachineOperand.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
The file was modifiedllvm/lib/Target/TargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
The file was modifiedllvm/include/llvm/CodeGen/MachineOperand.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
The file was modifiedllvm/lib/CodeGen/MIRParser/MIParser.cpp
The file was modifiedllvm/lib/CodeGen/MachineInstr.cpp
The file was modifiedllvm/lib/CodeGen/MIRParser/MILexer.h
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
The file was modifiedllvm/lib/CodeGen/MIRParser/MILexer.cpp
The file was modifiedllvm/include/llvm/CodeGen/MIRParser/MIParser.h
Commit 3ef05d85be8c3666ebfa3ad986eb334da5195a47 by daniel_l_sanders
[MIR] Target specific MIR formating and parsing
Summary: Added MIRFormatter for target specific MIR formating and
parsing with immediate and custom pseudo source values. Target machine
can subclass MIRFormatter and implement custom logic for printing and
parsing immediate and custom pseudo source values for better
readability.
* Target specific immediate mnemonic need to start with "." follows by
identifier string. When MIR parser sees immediate it will call target
specific parsing function.
* Custom pseudo source value need to start with custom follows by
double-quoted string. MIR parser will pass the quoted string to target
specific PSV parsing function.
* MIRFormatter have 2 helper functions to facilitate LLVM value printing
and parsing for custom PSV if they refers LLVM values.
Patch by Peng Guo
Reviewers: dsanders, arsenm
Reviewed By: dsanders
Subscribers: wdng, jvesely, nhaehnle, hiraditya, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69836
The file was modifiedllvm/lib/CodeGen/MachineInstr.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
The file was modifiedllvm/lib/CodeGen/MIRParser/MIParser.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
The file was addedllvm/include/llvm/CodeGen/MIRFormatter.h
The file was modifiedllvm/include/llvm/CodeGen/MachineOperand.h
The file was modifiedllvm/include/llvm/CodeGen/PseudoSourceValue.h
The file was modifiedllvm/lib/CodeGen/MIRParser/MILexer.h
The file was modifiedllvm/lib/CodeGen/MIRParser/MILexer.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
The file was modifiedllvm/lib/CodeGen/MIRPrinter.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
The file was modifiedllvm/include/llvm/CodeGen/MIRParser/MIParser.h
The file was modifiedllvm/unittests/CodeGen/MachineOperandTest.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
The file was modifiedllvm/include/llvm/CodeGen/MachineMemOperand.h
The file was modifiedllvm/lib/CodeGen/MachineOperand.cpp
The file was modifiedllvm/include/llvm/Target/TargetMachine.h
The file was modifiedllvm/lib/Target/TargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
Commit 71d64f72f934631aa2f12b9542c23f74f256f494 by thakis
Revert "[MIR] Target specific MIR formating and parsing"
This reverts commit 3ef05d85be8c3666ebfa3ad986eb334da5195a47. It broke
check-llvm on many bots, see comments on D69836.
The file was modifiedllvm/lib/CodeGen/MachineOperand.cpp
The file was modifiedllvm/unittests/CodeGen/MachineOperandTest.cpp
The file was modifiedllvm/include/llvm/CodeGen/PseudoSourceValue.h
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
The file was modifiedllvm/lib/Target/TargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
The file was modifiedllvm/lib/CodeGen/MIRParser/MILexer.h
The file was modifiedllvm/include/llvm/Target/TargetMachine.h
The file was modifiedllvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
The file was removedllvm/include/llvm/CodeGen/MIRFormatter.h
The file was modifiedllvm/lib/CodeGen/MIRPrinter.cpp
The file was modifiedllvm/lib/CodeGen/MachineInstr.cpp
The file was modifiedllvm/lib/CodeGen/MIRParser/MIParser.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
The file was modifiedllvm/include/llvm/CodeGen/MachineOperand.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
The file was modifiedllvm/include/llvm/CodeGen/MIRParser/MIParser.h
The file was modifiedllvm/include/llvm/CodeGen/MachineMemOperand.h
The file was modifiedllvm/lib/CodeGen/MIRParser/MILexer.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
Commit de3d0ee023cb14c06d5be01369ef8db4cbfa16b4 by daniel_l_sanders
Revert "Revert "[MIR] Target specific MIR formating and parsing""
There was an unguarded dereference of MF in a function that permitted
nullptr. Fixed
This reverts commit 71d64f72f934631aa2f12b9542c23f74f256f494.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
The file was modifiedllvm/lib/Target/TargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
The file was addedllvm/include/llvm/CodeGen/MIRFormatter.h
The file was modifiedllvm/lib/CodeGen/MIRPrinter.cpp
The file was modifiedllvm/unittests/CodeGen/MachineOperandTest.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
The file was modifiedllvm/lib/CodeGen/MachineOperand.cpp
The file was modifiedllvm/include/llvm/CodeGen/MIRParser/MIParser.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
The file was modifiedllvm/include/llvm/CodeGen/MachineOperand.h
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
The file was modifiedllvm/lib/CodeGen/MIRParser/MILexer.h
The file was modifiedllvm/lib/CodeGen/MIRParser/MILexer.cpp
The file was modifiedllvm/include/llvm/CodeGen/PseudoSourceValue.h
The file was modifiedllvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
The file was modifiedllvm/include/llvm/CodeGen/MachineMemOperand.h
The file was modifiedllvm/include/llvm/Target/TargetMachine.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
The file was modifiedllvm/lib/CodeGen/MachineInstr.cpp
The file was modifiedllvm/lib/CodeGen/MIRParser/MIParser.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
Commit d48ac7d54d8a096677c84cfb2928400e05b918ea by qshanz
[DAGCombine] Fold the (fma -x, y, -z) to -(fma x, y, z)
This is a positive combination as long as the NEG is NOT free, as we are
reducing the number of NEG from two to one.
Differential Revision: https://reviews.llvm.org/D72312
The file was modifiedllvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fma-combine.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/recipest.ll
The file was modifiedllvm/test/CodeGen/PowerPC/combine-fneg.ll
The file was modifiedllvm/test/CodeGen/PowerPC/qpx-recipest.ll
Commit 51bdd98b8a52d07004bcaddff26caf376a1c32bf by Jonas Devlieghere
[lldb/SWIG] Refactor extensions to be non Python-specific (3/3)
The current SWIG extensions for the string conversion operator is Python
specific because it uses the PythonObjects. This means that the code
cannot be reused for other SWIG supported languages such as Lua.
This reimplements the extensions in a more generic way that can be
reused. It uses a SWIG macro to reduce code duplication.
Differential revision: https://reviews.llvm.org/D72377
The file was modifiedlldb/scripts/interface/SBSymbolContext.i
The file was modifiedlldb/scripts/interface/SBTypeNameSpecifier.i
The file was modifiedlldb/scripts/interface/SBTypeSummary.i
The file was modifiedlldb/scripts/interface/SBTypeFormat.i
The file was modifiedlldb/scripts/interface/SBSymbolContextList.i
The file was modifiedlldb/scripts/interface/SBTypeFilter.i
The file was modifiedlldb/scripts/interface/SBValueList.i
The file was modifiedlldb/scripts/Python/python-extensions.swig
The file was modifiedlldb/scripts/interface/SBSymbol.i
The file was modifiedlldb/scripts/interface/SBThread.i
The file was modifiedlldb/scripts/interface/SBTypeCategory.i
The file was modifiedlldb/scripts/interface/SBProcess.i
The file was modifiedlldb/scripts/interface/SBSection.i
The file was modifiedlldb/scripts/interface/SBValue.i
The file was modifiedlldb/scripts/interface/SBWatchpoint.i
The file was modifiedlldb/scripts/interface/SBType.i
The file was modifiedlldb/scripts/interface/SBTypeSynthetic.i
The file was modifiedlldb/scripts/interface/SBTypeEnumMember.i
Commit 4ebb589629b0d3de0827cab179338836ebb3a8b6 by czhengsz
[SCEV] [NFC] add testcase for constant range for addrecexpr with nsw
flag
The file was modifiedllvm/test/Analysis/ScalarEvolution/range_nw_flag.ll
Commit 24b326cc610dfdccdd50bc78505ec228d96c8e7a by ehudkatz
[APFloat] Fix checked error assert failures
`APFLoat::convertFromString` returns `Expected` result, which must be
"checked" if the LLVM_ENABLE_ABI_BREAKING_CHECKS preprocessor flag is
set. To mark an `Expected` result as "checked" we must consume the
`Error` within. In many cases, we are only interested in knowing if an
error occured, without the need to examine the error info. This is
achieved, easily, with the `errorToBool()` API.
The file was modifiedllvm/lib/Support/StringRef.cpp
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
The file was modifiedclang-tools-extra/clang-tidy/readability/MagicNumbersCheck.cpp
The file was modifiedllvm/unittests/ADT/APFloatTest.cpp
The file was modifiedclang/lib/Lex/LiteralSupport.cpp
The file was modifiedllvm/include/llvm/ADT/StringRef.h
The file was modifiedllvm/lib/Support/APFloat.cpp
The file was modifiedllvm/lib/MC/MCParser/AsmParser.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
Commit 65678d938431c90408afa8d255cbed3d8ed8273f by ntv
[mlir][VectorOps] Implement strided_slice conversion
Summary: This diff implements the progressive lowering of strided_slice
to either:
1. extractelement + insertelement for the 1-D case
2. extract + optional strided_slice + insert for the n-D case.
This combines properly with the other conversion patterns to lower all
the way to LLVM.
Appropriate tests are added.
Reviewers: ftynse, rriddle, AlexEichenberger, andydavis1, tetuante
Reviewed By: andydavis1
Subscribers: merge_guards_bot, mehdi_amini, jpienaar, burmako, shauheen,
antiagainst, arpith-jacob, mgester, lucyrfox, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72310
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
The file was modifiedmlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
The file was modifiedmlir/include/mlir/IR/Attributes.h
Commit 2d515e49d89c0738ccef8f1733d5f9afe00ee979 by ntv
[mlir][VectorOps] Implement insert_strided_slice conversion
Summary: This diff implements the progressive lowering of
insert_strided_slice. Two cases appear: 1. when the source and dest
vectors have different ranks, extract the dest subvector at the proper
offset and reduce to case 2. 2. when they have the same rank N:
a. if the source and dest type are the same, the insertion is trivial:
    just forward the source
b. otherwise, iterate over all N-1 D subvectors and create an
    extract/insert_strided_slice/insert replacement, reducing the
problem
    to vecotrs of the same N-1 rank.
This combines properly with the other conversion patterns to lower all
the way to LLVM.
Reviewers: ftynse, rriddle, AlexEichenberger, andydavis1, tetuante,
nicolasvasilache
Reviewed By: andydavis1
Subscribers: merge_guards_bot, mehdi_amini, jpienaar, burmako, shauheen,
antiagainst, arpith-jacob, mgester, lucyrfox, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72317
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
The file was modifiedmlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
Commit e93e0d413f3afa1df5c5f88df546bebcd1183155 by sam.parker
[ARM][LowOverheadLoops] Update liveness info
After expanding the pseudo instructions, update the liveness info. We do
this in a post-order traversal of the loop, including its exit blocks
and preheader(s).
Differential Revision: https://reviews.llvm.org/D72131
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update3.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir
The file was modifiedllvm/lib/CodeGen/LivePhysRegs.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir
Commit 08778d8c4fd8a6519c7f27bfa6b09c47262cb844 by zinenko
[mlir][GPU] introduce utilities for promotion to workgroup memory
Introduce a set of function that promote a memref argument of a
`gpu.func` to workgroup memory using memory attribution. The promotion
boils down to additional loops performing the copy from the original
argument to the attributed memory in the beginning of the function, and
back at the end of the function using all available threads. The loop
bounds are specified so as to adapt to any size of the workgroup. These
utilities are intended to compose with other existing utilities (loop
coalescing and tiling) in cases where the distribution of work across
threads is uneven, e.g. copying a 2D memref with only the threads along
the "x" dimension. Similarly, specialization of the kernel to specific
launch sizes should be implemented as a separate pass combining constant
propagation and canonicalization.
Introduce a simple attribute-driven pass to test the promotion
transformation since we don't have a heuristic at the moment.
Differential revision: https://reviews.llvm.org/D71904
The file was addedmlir/lib/Dialect/GPU/Transforms/MemoryPromotion.cpp
The file was modifiedmlir/lib/IR/Block.cpp
The file was modifiedmlir/test/lib/Transforms/CMakeLists.txt
The file was addedmlir/test/lib/Transforms/TestGpuMemoryPromotion.cpp
The file was modifiedmlir/include/mlir/Dialect/GPU/GPUOps.td
The file was addedmlir/test/Dialect/GPU/promotion.mlir
The file was modifiedmlir/lib/Dialect/GPU/CMakeLists.txt
The file was modifiedmlir/lib/Dialect/GPU/IR/GPUDialect.cpp
The file was addedmlir/include/mlir/Dialect/GPU/MemoryPromotion.h
The file was modifiedmlir/include/mlir/IR/Block.h
The file was modifiedmlir/include/mlir/Dialect/GPU/GPUDialect.h
Commit 8f1887456ab4ba24a62ccb19d0d04b08972a0289 by sjoerd.meijer
[LV] Still vectorise when tail-folding can't find a primary inducation
variable
This addresses a vectorisation regression for tail-folded loops that are
counting down, e.g. loops as simple as this:
  void foo(char *A, char *B, char *C, uint32_t N) {
   while (N > 0) {
     *C++ = *A++ + *B++;
      N--;
   }
}
These are loops that can be vectorised, but when tail-folding is
requested, it can't find a primary induction variable which we do need
for predicating the loop. As a result, the loop isn't vectorised at all,
which it is able to do when tail-folding is not attempted. So, this adds
a check for the primary induction variable where we decide how to lower
the scalar epilogue. I.e., when there isn't a primary induction
variable, a scalar epilogue loop is allowed
(i.e. don't request tail-folding) so that vectorisation could still be
triggered.
Having this check for the primary induction variable make sense anyway,
and in addition, in a follow-up of this I will look into discovering
earlier the primary induction variable for counting down loops, so that
this can also be tail-folded.
Differential revision: https://reviews.llvm.org/D72324
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was addedllvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll
The file was addedllvm/test/Transforms/LoopVectorize/tail-folding-counting-down.ll
Commit 0541a9d4e7f85c1f08f27fe0c0cae293bbb3903a by pavel
[DWARFDebugLoc] Tweak error message when resolving offset pairs with no
base address
The previous message mentioned DW_LLE_offset_pair, but this is
incorrect/confusing because we can get this message even with DWARF4
(which does not use DW_LLE encodings). This happens because DWARF<=4
location entries are "upgraded" to DWARF v5 during parsing.
The new error message refrains from referencing specific constants.
Fixes pr44482.
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp
Commit 1cba2612399eaf5ad67f173ab69db0b1b0328fcb by sam.parker
Revert "[ARM][LowOverheadLoops] Update liveness info"
This reverts commit e93e0d413f3afa1df5c5f88df546bebcd1183155.
There's some ordering problems on some on the buildbots which needs
investigating.
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update3.mir
The file was modifiedllvm/lib/CodeGen/LivePhysRegs.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir
Commit 459ad8e97e07c823181cd457f2c2ac08f3896e37 by flo
[Matrix] Implement back-propagation of shape information.
This patch extends the shape propagation for matrix operations to also
propagate the shape of instructions to their operands.
Reviewers: anemet, Gerolf, reames, hfinkel, andrew.w.kaylor
Reviewed By: anemet
Differential Revision: https://reviews.llvm.org/D70899
The file was addedllvm/test/Transforms/LowerMatrixIntrinsics/propagate-backwards-unsupported.ll
The file was modifiedllvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
The file was addedllvm/test/Transforms/LowerMatrixIntrinsics/propagate-backward.ll
Commit f0abe820eebf47a3e9b9d0daf9f995d65db186bc by evgueni.brevnov
[LoopUtils][NFC] Minor refactoring in getLoopEstimatedTripCount.
The file was modifiedllvm/lib/Transforms/Utils/LoopUtils.cpp
The file was modifiedllvm/include/llvm/Support/MathExtras.h
Commit 00c6e98409f98c3093aab4b1bfbc25c5b54731d0 by simon.moll
[VE] Target stub for NEC SX-Aurora
Summary: This patch registers the 've' target: the NEC SX-Aurora TSUBASA
Vector Engine.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D69103
The file was modifiedllvm/CODE_OWNERS.TXT
The file was addedllvm/lib/Target/VE/MCTargetDesc/LLVMBuild.txt
The file was addedllvm/lib/Target/VE/CMakeLists.txt
The file was modifiedllvm/include/llvm/ADT/Triple.h
The file was addedllvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.h
The file was addedllvm/lib/Target/VE/MCTargetDesc/CMakeLists.txt
The file was addedllvm/test/CodeGen/VE/target_support.ll
The file was modifiedllvm/lib/Support/Triple.cpp
The file was addedllvm/lib/Target/VE/LLVMBuild.txt
The file was addedllvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp
The file was addedllvm/lib/Target/VE/TargetInfo/VETargetInfo.cpp
The file was modifiedllvm/unittests/ADT/TripleTest.cpp
The file was addedllvm/lib/Target/VE/VE.h
The file was modifiedllvm/lib/Target/LLVMBuild.txt
The file was addedllvm/lib/Target/VE/VETargetMachine.cpp
The file was addedllvm/lib/Target/VE/VETargetMachine.h
The file was addedllvm/test/CodeGen/VE/lit.local.cfg
The file was addedllvm/lib/Target/VE/TargetInfo/LLVMBuild.txt
The file was addedllvm/lib/Target/VE/TargetInfo/CMakeLists.txt
Commit 7adf6644f50a60a25f81c976b0f3a08320a63665 by flo
[Matrix] Propagate and use shape information for loads.
This patch extends to shape propagation to also include load
instructions and implements shape aware lowering for vector loads.
Reviewers: anemet, Gerolf, reames, hfinkel, andrew.w.kaylor
Reviewed By: anemet
Differential Revision: https://reviews.llvm.org/D70900
The file was modifiedllvm/test/Transforms/LowerMatrixIntrinsics/bigger-expressions-double.ll
The file was modifiedllvm/test/Transforms/LowerMatrixIntrinsics/propagate-backward.ll
The file was modifiedllvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
Commit 287a874d1c460302677a1530a75d94bae4d4a348 by kadircet
[clangd] Refurbish HoverInfo::present
Summary: Improves basic hover presentation logic to include more info.
Reviewers: sammccall
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, usaxena95,
cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D71555
The file was modifiedclang-tools-extra/clangd/unittests/HoverTests.cpp
The file was modifiedclang-tools-extra/clangd/Hover.cpp
The file was modifiedclang-tools-extra/clangd/test/hover.test
Commit ccf24225e3f2356ebf0e73bb114a831bf1721222 by flo
[Matrix] Update shape propagation to iterate until done.
This patch updates the shape propagation to iterate until no new shape
information is discovered.
As initial seed for the forward propagation, we use the matrix intrinsic
instructions. Both propagateShapeForward and propagateShapeBackward
return new work lists, with the instructions to be used for the next
iteration. When propagating forward, we record all instructions we added
new shape information for. When propagating backward, we record all
users of instructions we added new shape information for.
Reviewers: anemet, Gerolf, reames, hfinkel, andrew.w.kaylor
Reviewed By: anemet
Differential Revision: https://reviews.llvm.org/D70901
The file was addedllvm/test/Transforms/LowerMatrixIntrinsics/propagate-multiple-iterations.ll
The file was modifiedllvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
Commit 782ad91cc423bf602718e2bf9ffc59e55350463f by Raphael Isemann
[lldb] Fix that TestNoSuchArch.py was passing for the wrong reason
The command here failed due to the type in 'create' but the expect did
not actually check for the error message. This fixes the typo and adds a
check for the actuall error message we should see.
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/target/create-no-such-arch/TestNoSuchArch.py
Commit 0d5407987a36445f21f122656edccbb0d9234f62 by llvm-dev
Fix MSVC unhandled enum warning. NFCI.
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntime.cpp
Commit 795c38eb4df636d434a9821efecbfeb41ecba843 by abpostelnicu
[clang-tidy] For checker `readability-misleading-indentation` update
tests.
Summary: In D72333 we've introduced support for `if constexpr` but the
test for uninstantiated template was not ready to land on windows
platform since this target uses `-fdelayed-template-parsing` by default.
This patch addresses this by passing `-fno-delayed-template-parsing` to
the test.
Reviewers: JonasToth
Subscribers: xazax.hun, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72438
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/readability-misleading-indentation.cpp
Commit 15c7fa4d11eeb50095ae571c645427b9a267bdee by sam.parker
[ARM][MVE] Don't unroll intrinsic loops.
We don't unroll vector loops for MVE targets, but we miss the case when
loops only contain intrinsic calls. So just move the logic a bit to
catch this case.
Differential Revision: https://reviews.llvm.org/D72440
The file was modifiedllvm/test/Transforms/LoopUnroll/ARM/mve-nounroll.ll
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
Commit e3e72a2619ccec9654ef9ad45e1e926841fbaa58 by llvm-dev
Fix "pointer is null" static analyzer warnings. NFCI.
Assert that the pointers are non-null before dereferencing them.
The file was modifiedclang/lib/CodeGen/CGObjCGNU.cpp
Commit e315ce2bd3a5347ab58d50fab2d449e8a4e60e00 by llvm-dev
Fix "pointer is null" static analyzer warnings. NFCI.
Use castAs<> instead of getAs<> since the pointer is dereferenced
immediately below and castAs will perform the null assertion for us.
The file was modifiedclang/lib/Sema/SemaCoroutine.cpp
Commit 9bb01efa49ca7f069bc7acba7e4c9bf64d972e79 by pavel
[lldb/DWARF] Add is_dwo member to DWARFUnit
Summary: A skeleton unit can easily be detected by checking the
m_dwo_symbol_file member, but we cannot tell a split unit from a normal
unit from the
"inside", which is sometimes useful.
This patch adds a m_is_dwo member to enable this, and align the code
with llvm::DWARFUnit. Right now it's only used to avoid creating a split
unit inside another split unit (which removes one override from
SymbolFileDWARFDwo and brings us a step closer to deleting it), but my
main motivation is fixing the handling of location lists in mixed v4&v5
files. This comes in a separate patch.
Reviewers: JDevlieghere, aprantl, clayborg
Subscribers: dblaikie, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D71750
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFTypeUnit.h
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFCompileUnit.h
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFContext.h
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h
Commit cd5da94d80b2b0f2bdb2d0157e24705a4cbd2a4e by pavel
[lldb/DWARF] Fix mixed v4+v5 location lists
Summary: Our code was expecting that a single (symbol) file contains
only one kind of location lists. This is not correct (on non-apple
platforms, at least) as a file can compile units with different dwarf
versions.
This patch moves the deteremination of location list flavour down to the
compile unit level, fixing this problem. I have also tried to rougly
align the code with the llvm DWARFUnit. Fully matching the API is not
possible because of how lldb's DWARFExpression lives separately from the
rest of the DWARF code, but this is at least a step in the right
direction.
Reviewers: JDevlieghere, aprantl, clayborg
Subscribers: dblaikie, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D71751
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
The file was addedlldb/test/Shell/SymbolFile/DWARF/debug_loc_and_loclists.s
The file was modifiedlldb/include/lldb/Expression/DWARFExpression.h
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfoEntry.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
The file was modifiedlldb/source/Expression/DWARFExpression.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h
Commit d462185e8daa49889c31c8f5568749e379a5ddf9 by llvm-dev
Fix "pointer is null" static analyzer warning. NFCI.
Use cast<> instead of dyn_cast<> since we know that the pointer should
be valid (and is dereferenced immediately below).
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp
Commit 25dd99fab205619ef90d0da23bcfba3c9f762e5e by llvm-dev
Fix "pointer is null" static analyzer warning. NFCI.
Use cast<> instead of dyn_cast<> since we know that the pointer should
be valid (and is dereferenced immediately).
The file was modifiedllvm/lib/IR/Verifier.cpp
Commit 9c91d79dadc660cb6a0ec736389341debd8cd118 by sam.parker
[NFC][ARM] LowOverheadLoop comments
Add a comment describing the dependencies of the pass.
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
Commit b65b1f322bd88513586a4539d2b5f18aeb698f3f by saar
[Concepts] Function trailing requires clauses
Function trailing requires clauses now parsed, supported in overload
resolution and when calling, referencing and taking the address of
functions or function templates.
Differential Revision: https://reviews.llvm.org/D43357
The file was addedclang/test/CXX/over/over.over/p4-2a.cpp
The file was modifiedclang/test/CXX/temp/temp.constr/temp.constr.decl/func-template-decl.cpp
The file was addedclang/test/CXX/expr/expr.prim/expr.prim.id/mixed-constraints.cpp
The file was modifiedclang/test/CXX/temp/temp.constr/temp.constr.order/class-template-partial-specializations.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticParseKinds.td
The file was modifiedclang/lib/Sema/SemaConcept.cpp
The file was modifiedclang/lib/Sema/SemaTemplateInstantiate.cpp
The file was modifiedclang/include/clang/AST/Decl.h
The file was modifiedclang/include/clang/AST/DeclCXX.h
The file was modifiedclang/lib/Sema/SemaOverload.cpp
The file was modifiedclang/lib/AST/DeclPrinter.cpp
The file was modifiedclang/test/CXX/temp/temp.constr/temp.constr.constr/function-templates.cpp
The file was modifiedclang/lib/Serialization/ASTWriterDecl.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/CXX/temp/temp.constr/temp.constr.constr/partial-specializations.cpp
The file was addedclang/test/CXX/over/over.match/over.match.best/p1-2a.cpp
The file was modifiedclang/test/CXX/temp/temp.constr/temp.constr.order/function-templates.cpp
The file was modifiedclang/include/clang/Sema/Overload.h
The file was modifiedclang/lib/Parse/ParseDeclCXX.cpp
The file was modifiedclang/test/Parser/cxx-concepts-requires-clause.cpp
The file was modifiedclang/lib/Parse/ParseTemplate.cpp
The file was modifiedclang/lib/Sema/SemaTemplate.cpp
The file was modifiedclang/lib/Sema/SemaTemplateDeduction.cpp
The file was addedclang/test/CXX/class.derived/class.virtual/p6.cpp
The file was addedclang/test/CXX/expr/expr.prim/expr.prim.id/p4.cpp
The file was addedclang/test/CXX/expr/expr.prim/expr.prim.lambda/expr.prim.lambda.closure/p3.cpp
The file was modifiedclang/test/CXX/temp/temp.constr/temp.constr.order/var-template-partial-specializations.cpp
The file was addedclang/test/CXX/temp/temp.explicit/p8.cpp
The file was modifiedclang/lib/Parse/ParseDecl.cpp
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
The file was modifiedclang/include/clang/Sema/DeclSpec.h
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp
The file was modifiedclang/lib/Serialization/ASTReaderDecl.cpp
The file was addedclang/test/SemaTemplate/instantiate-requires-clause.cpp
The file was modifiedclang/lib/Parse/ParseExprCXX.cpp
The file was modifiedclang/test/CXX/temp/temp.constr/temp.constr.decl/class-template-decl.cpp
The file was modifiedclang/lib/Sema/TreeTransform.h
The file was addedclang/include/clang/Sema/SemaConcept.h
The file was addedclang/test/CXX/dcl/dcl.decl/p3.cpp
The file was modifiedclang/lib/Sema/SemaLambda.cpp
The file was modifiedclang/include/clang/AST/ASTNodeTraverser.h
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/include/clang/AST/ASTLambda.h
The file was modifiedclang/include/clang/AST/RecursiveASTVisitor.h
The file was modifiedclang/lib/AST/Decl.cpp
The file was modifiedclang/lib/Parse/ParseExpr.cpp
The file was modifiedclang/test/CXX/temp/temp.constr/temp.constr.decl/var-template-decl.cpp
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/test/Parser/cxx-concepts-ambig-constraint-expr.cpp
The file was modifiedclang/include/clang/Parse/Parser.h
The file was modifiedclang/lib/AST/DeclTemplate.cpp
The file was modifiedclang/lib/Sema/SemaTemplateVariadic.cpp
The file was modifiedclang/lib/Parse/ParseOpenMP.cpp
The file was modifiedclang/lib/AST/DeclCXX.cpp
The file was modifiedclang/lib/Sema/SemaCast.cpp
The file was modifiedclang/lib/Sema/SemaDeclCXX.cpp
The file was modifiedclang/lib/Parse/ParseTentative.cpp
The file was modifiedclang/test/CXX/temp/temp.constr/temp.constr.constr/non-function-templates.cpp
The file was addedclang/test/CXX/over/over.match/over.match.viable/p3.cpp
The file was modifiedclang/lib/AST/ASTImporter.cpp
The file was modifiedclang/lib/Sema/SemaDecl.cpp
Commit 4a83f1e171b73b819bcdb486e363b409d25fc629 by inouehrs
[mlir] fix test failure in EDSC/builder-api-test
This patch fixes a test failure on a non-intel (PowerPC64) box. The two
affine.load are independent and hence llvm may reorder them. The CHECK
lines are modified for supporting reordered case.
Differential Revision: https://reviews.llvm.org/D72435
The file was modifiedmlir/test/EDSC/builder-api-test.cpp
Commit 5c4661b7784115cb330996b3a6461c5927339aef by pavel
[lldb] Modernize OptionValue::SetValueChangedCallback
instead of a function pointer + void*, take a std::function. This
removes a bunch of repetitive, unsafe void* casts.
The file was modifiedlldb/include/lldb/Target/Process.h
The file was modifiedlldb/source/Target/Process.cpp
The file was modifiedlldb/include/lldb/Interpreter/OptionValueProperties.h
The file was modifiedlldb/include/lldb/Target/Target.h
The file was modifiedlldb/include/lldb/Interpreter/OptionValue.h
The file was modifiedlldb/source/Interpreter/Property.cpp
The file was modifiedlldb/source/Target/Target.cpp
The file was modifiedlldb/include/lldb/Interpreter/Property.h
The file was modifiedlldb/source/Interpreter/OptionValueProperties.cpp
The file was modifiedlldb/include/lldb/lldb-private-interfaces.h
Commit 032a9393a739a1ef8c30979e2493971207c3c397 by spatel
[InstCombine] Use minimal FMF in testcase for Z / (1.0 / Y) => (Y * Z);
NFC
Patch by: @raghesh (Raghesh Aloor)
Differential Revision: https://reviews.llvm.org/D72431
The file was modifiedllvm/test/Transforms/InstCombine/fdiv.ll
Commit 173b711e83d7b61a46f55eb44f03ea98f69a1dd6 by momchil.velikov
[ARM][MVE] MVE-I should not be disabled by -mfpu=none
Architecturally, it's allowed to have MVE-I without an FPU, thus
-mfpu=none should not disable MVE-I, or moves to/from FP-registers.
This patch removes `+/-fpregs` from features unconditionally added to
target feature list, depending on FPU and moves the logic to Clang
driver, where the negative form (`-fpregs`) is conditionally added to
the target features list for the cases of `-mfloat-abi=soft`, or
`-mfpu=none` without either `+mve` or `+mve.fp`. Only the negative form
is added by the driver, the positive one is derived from other features
in the backend.
Differential Revision: https://reviews.llvm.org/D71843
The file was modifiedllvm/test/CodeGen/ARM/softfp-constant-comparison.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/mve-vldn.ll
The file was modifiedclang/test/Driver/arm-mfpu.c
The file was modifiedllvm/lib/Support/ARMTargetParser.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update3.mir
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll
The file was modifiedclang/lib/Driver/ToolChains/Arch/ARM.cpp
The file was modifiedclang/test/CodeGen/arm-target-features.c
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
Commit f53b38d12a7b9c6754d5bc91483efab935b5c012 by spatel
[InstSimplify] select Cond, true, false --> Cond
This is step 1 of damage control assuming that we need to remove several
over-reaching folds for select-of-booleans because they can cause
miscompiles as shown in D72396.
The scalar case seems obviously safe: https://rise4fun.com/Alive/jSj
And I don't think there's any danger for vectors either - if the
condition is poisoned, then the select must be poisoned too, so undef
elements don't make any difference.
Differential Revision: https://reviews.llvm.org/D72412
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
The file was modifiedllvm/test/Transforms/InstSimplify/select.ll
Commit 84ce46269cfda8800346706251ac3587b2d1c9f5 by saar
[Concepts] Fix failing test on Windows
Fix test failed by D43357 on Windows.
The file was modifiedclang/test/CXX/over/over.match/over.match.best/p1-2a.cpp
Commit cb5612e2df893728887bedd41aa2293f454c7845 by spatel
[DAGCombiner] reduce extract subvector of concat
If we are extracting a chunk of a vector that's a fraction of an operand
of the concatenated vector operand, we can extract directly from one of
those original operands.
This is another suggestion from PR42024:
https://bugs.llvm.org/show_bug.cgi?id=42024#c2
But I'm not sure yet if it will make any difference on those patterns.
It seems to help a few existing AVX512 tests though.
Differential Revision: https://reviews.llvm.org/D72361
The file was modifiedllvm/test/CodeGen/X86/pr34657.ll
The file was modifiedllvm/test/CodeGen/X86/avg.ll
The file was modifiedllvm/test/CodeGen/X86/x86-interleaved-access.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 4c11703b3d9d936214b8ced70bd6475974c317d8 by a.bataev
[OPENMP]Remove unused code, NFC.
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntime.cpp
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntime.h
Commit 667e1f71b83c48b635b13b64bbff28b95e68265c by Tim Northover
IR: remove "else" after "return". NFCI.
The file was modifiedllvm/lib/IR/Core.cpp
Commit d857e114b5e04f5143485a5aea7ad9b283768692 by simon.tatham
[ARM,MVE] Fix valid immediate range for vsliq_n.
In common with most MVE immediate shift instructions, the left shift
takes an immediate in the range [0,n-1], while the right shift takes one
in the range [1,n]. I had absent-mindedly made them both the latter.
While I'm here, I've added a set of regression tests checking both ends
of the immediate range for a representative sample of the immediate
shifts.
The file was modifiedclang/test/Sema/arm-mve-immediates.c
The file was modifiedclang/include/clang/Basic/arm_mve.td
Commit 9704ba652a0062c53ec66b068766df5c0cd5c620 by simon.tatham
[ARM,MVE] Add missing IntrNoMem flag on IR intrinsics.
A lot of the IR-level intrinsics we've been defining for MVE recently
accidentally had `props = []` instead of `props = [IntrNoMem]`, so that
optimization would have been overcautious about reordering them.
All the affected cases were due to instantiating the multiclasses
`MVEPredicated` and `MVEMXPredicated` without filling in the `props`
parameter, because I //thought// I remembered having set the defaults in
those multiclasses to `[IntrNoMem]`. In fact I hadn't done that. Now I
have.
(The IR intrinsics that //do// read and write memory are all explicitly
marked as `[IntrReadMem]` or `[IntrWriteMem]` already, so they will
override these defaults.)
The file was modifiedllvm/include/llvm/IR/IntrinsicsARM.td
Commit db7c92077963195df0807e976cc916b5c6e29a05 by arsenm2
AMDGPU: Add register class to DS_SWIZZLE_B32 pattern
Reduces diff for a future patch.
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td
Commit 0274ed9dc75a0efb2b6130122226ee45f7e57dde by arsenm2
TableGen/GlobalISel: Fix slightly wrong generated comment
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/test/TableGen/GlobalISelEmitter.td
Commit 3952748ffdf017f83faddcb1240cb36cb4bb9c5b by arsenm2
AMDGPU/GlobalISel: Fix add of neg inline constant pattern
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit d964086c62422771c1d6dbe66ee8ea06e8f834b2 by arsenm2
AMDGPU/GlobalISel: Add equiv xform for bitcast_fpimm_to_i32
Only partially fixes one pattern import.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit 79450a4ea26a0e9731eaf2629f6dd8c1ffd8f407 by arsenm2
AMDGPU/GlobalISel: Add selectVOP3Mods_nnan
This doesn't enable any new imports yet, but moves the fmed patterns
from failing on this to hitting the "complex suboperand referenced more
than once" limitation in tablegen.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
Commit e71af775684a83f0d1d05ab5225d36830d5aa87e by arsenm2
AMDGPU/GlobalISel: Add IMMPopCount xform
Partially fixes BFE pattern import.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
Commit 7d677421607cbfdd8d1e96275c613d3db8a0e51f by arsenm2
AMDGPU/GlobalISel: Fix import of zext of s16 op patterns
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/VOP2Instructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
Commit c1d4963b447c9330c2ad50bb73bb93f9a42c9641 by arsenm2
AMDGPU: Use new PatFrag system for d16 load nodes
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
Commit 3766f4baccac5cc17680ad4cefd1d5a0d3ba2870 by arsenm2
AMDGPU: Use new PatFrag system for d16 stores
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td
Commit c66b2e1c87ecde72eb37d3452ec9c1b8766ede30 by arsenm2
AMDGPU: Eliminate more legacy codepred address space PatFrags
These should now be limited to R600 code.
The file was modifiedllvm/lib/Target/AMDGPU/FLATInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/BUFInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/R600Instructions.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructions.td
Commit 9ffd0ed838191247e0da7df5e28e54a5129e76a7 by arsenm2
AMDGPU/GlobalISel: Fix import of integer med3
This isn't too useful now, since nothing is currently trying to form
min/max from cmp+select.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
Commit de08244d3da52215b8c63bc70d0a3c9e07b620a3 by arsenm2
TableGen: Remove unused code
The file was modifiedllvm/utils/TableGen/CodeGenDAGPatterns.h
Commit 0fa8f701ccf6f29544394b358f38b748e3f7ab24 by sidneym
[ELF][Hexagon] Add support for IE relocations
Differential Revision: https://reviews.llvm.org/D71143
The file was modifiedlld/ELF/Relocations.cpp
The file was modifiedlld/ELF/Arch/Hexagon.cpp
The file was addedlld/test/ELF/hexagon-tls-ie.s
Commit 6c04ef472a8739a60a7935f77edfbacd2f50eb73 by spatel
[InstCombine] Z / (1.0 / Y) => (Y * Z)
This is a special case of Z / (X / Y) => (Y * Z) / X, with X = 1.0. The
m_OneUse check is avoided because even in the case of the multiple uses
for 1.0/Y, the number of instructions remain the same and a division is
replaced by a multiplication.
Differential Revision: https://reviews.llvm.org/D72319
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
The file was modifiedllvm/test/Transforms/InstCombine/fdiv.ll
Commit fb76c7934dce2ede7e04097edb455eba58f6ebfd by jaskiewiczs
[libcxxabi] Allow tests to link with static libc++abi/libc++ even if the
shared version is present
Summary: Right now the only way to force libc++abi tests to link with
the static version of libc++abi is to set `LIBCXXABI_ENABLE_SHARED` to
`OFF`. However, this doesn't work when libc++abi is built as standalone
project because of
[this](https://github.com/llvm/llvm-project/blob/54c522420347e58aa7bae1892cf5c5672b57c875/libcxxabi/CMakeLists.txt#L503-L519).
This change allows specifying the version of the library for tests to
link with.
This is useful for remote testing, for example, with `SSHExecutor`,
where we _have_ to link with libc++abi statically.
Two new CMake options are introduced here:
`LIBCXXABI_LINK_TESTS_WITH_SHARED_LIBCXXABI` and
`LIBCXXABI_LINK_TESTS_WITH_SHARED_LIBCXX`. They can be set to `OFF` to
tell the test utility to link tests with the static libraries.
It shouldn't break anything, because the default values of these options
are set such that the test utility will behave the same way.
Reviewers: EricWF, mclow.lists, phosek, mehdi_amini, ldionne, jroelofs,
bcraig
Subscribers: mgorny, christof, ldionne, libcxx-commits
Tags: #libc
Differential Revision: https://reviews.llvm.org/D71894
The file was modifiedlibcxxabi/CMakeLists.txt
The file was modifiedlibcxxabi/test/lit.site.cfg.in
The file was modifiedlibcxxabi/test/CMakeLists.txt
Commit ea9888b8f6f20887647b77ebf5864d647fd2ea44 by davg
[clangd] Respect `--sysroot` argument if it is set
Summary:
- Since `--sysroot` is a superset of the `-isysroot` argument, we
shouldn't add the `-isysroot` if we detect a `--sysroot` flag.
Reviewers: sammccall
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet,
usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72415
The file was modifiedclang-tools-extra/clangd/CompileCommands.cpp
Commit 93a1e9c90c96a9130352bf358d7777f0379ebb48 by Jonas Devlieghere
[lldb/SWIG] Add missing '\' in macros again
Making the string conversion operator a macro unintentionally dropped
the backslash before '\n' and '\r' and was therefore incorrectly
stripping 'n' and 'r' from the object description.
The file was modifiedlldb/scripts/macros.swig
Commit 45c971f7eef18ef2b77a5f64133dbd7bd5939d5f by Jonas Devlieghere
[lldb/Lua] Make lldb.debugger et al available to Lua
The Python script interpreter makes the current debugger, target,
process, thread and frame available to interactive scripting sessions
through convenience variables. This patch does the same for Lua.
Differential revision: https://reviews.llvm.org/D71801
The file was addedlldb/test/Shell/ScriptInterpreter/Lua/Inputs/nested_sessions.in
The file was addedlldb/test/Shell/ScriptInterpreter/Lua/Inputs/independent_state.in
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp
The file was addedlldb/test/Shell/ScriptInterpreter/Lua/nested_sessions.test
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Lua/Lua.h
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Lua/Lua.cpp
The file was addedlldb/test/Shell/ScriptInterpreter/Lua/Inputs/nested_sessions_2.in
The file was addedlldb/test/Shell/ScriptInterpreter/Lua/convenience_variables.test
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.h
The file was addedlldb/test/Shell/ScriptInterpreter/Lua/independent_state.test
Commit d27a15fed79c8e8484825ce6c3ce1682daeb1547 by whitneyt
[NFCI][LoopUnrollAndJam] Changing LoopUnrollAndJamPass to a function
pass.
Summary: This patch changes LoopUnrollAndJamPass to a function pass, and
keeps the loops traversal order same as defined in
FunctionToLoopPassAdaptor LoopPassManager.h.
The next patch will change the loop traversal to outer to inner order,
so more loops can be transform.
Discussion in llvm-dev mailing list:
https://groups.google.com/forum/#!topic/llvm-dev/LF4rUjkVI2g Reviewer:
dmgreen, jdoerfert, Meinersbur, kbarton, bmahjour, etiotto Reviewed By:
dmgreen Subscribers: hiraditya, zzheng, llvm-commits Tag: LLVM
Differential Revision: https://reviews.llvm.org/D72230
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/lib/Passes/PassRegistry.def
The file was modifiedllvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll
The file was modifiedllvm/test/Transforms/LoopUnrollAndJam/disable.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp
The file was modifiedllvm/test/Transforms/LoopUnrollAndJam/dependencies.ll
The file was modifiedllvm/test/Transforms/LoopUnrollAndJam/pragma-explicit.ll
The file was modifiedllvm/include/llvm/Transforms/Scalar/LoopUnrollAndJamPass.h
Commit cee4a1c957426e9477c8579ff960c8c2bd4af9e2 by sguelton
Improve support of GNU mempcpy
- Lower to the memcpy intrinsic
- Raise warnings when size/bounds are known
Differential Revision: https://reviews.llvm.org/D71374
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was addedclang/test/CodeGen/mempcpy-libcall.c
The file was modifiedclang/lib/AST/Decl.cpp
The file was modifiedclang/include/clang/Basic/Builtins.def
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedclang/test/Analysis/bstring.c
Commit 241f335b268dc19a0dfb85686a7c82fb339421a8 by sven.vanhaastregt
[OpenCL][Docs] Rename C++ for OpenCL label
To avoid potential confusion with OpenCL C++.
The file was modifiedclang/docs/UsersManual.rst
Commit 6498aff249a1c3c6bad33137df3b90e2973722d6 by Jonas Devlieghere
[lldb/Bindings] Move bindings into their own subdirectory
All the code required to generate the language bindings for Python and
Lua lives under scripts, even though the majority of this code aren't
scripts at all, and surrounded by scripts that are totally unrelated.
I've reorganized these files and moved everything related to the
language bindings into a new top-level directory named bindings. This
makes the corresponding files self contained and much more discoverable.
Differential revision: https://reviews.llvm.org/D72437
The file was removedlldb/scripts/interface/SBMemoryRegionInfoList.i
The file was removedlldb/scripts/interface/SBWatchpoint.i
The file was addedlldb/bindings/interface/SBSymbolContext.i
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The file was addedlldb/bindings/interface/SBSourceManager.i
The file was removedlldb/scripts/Python/python-extensions.swig
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The file was addedlldb/bindings/interface/SBBreakpointName.i
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The file was addedlldb/bindings/python/python-swigsafecast.swig
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The file was removedlldb/scripts/interface/SBData.i
The file was addedlldb/bindings/python/python-wrapper.swig
Commit 189aa5b7a4584677ad628ecc2c369db61d4d2515 by kadircet
[clangd] Adjust diagnostic range to be inside main file
Summary: LSP requires diagnostics to lay inside main file. In clangd we
keep diagnostics in three different cases:
- already in main file
- adjusted to a header included in main file
- has a note covering some range in main file
In the last case, we were not adjusting the diagnostics range to be in
main file, therefore these diagnostics ended up pointing some arbitrary
locations.
This patch fixes that issue by adjusting the range of diagnostics to be
the first note inside main file when converting to LSP.
Reviewers: ilya-biryukov
Subscribers: MaskRay, jkorous, arphaman, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72458
The file was modifiedclang-tools-extra/clangd/unittests/DiagnosticsTests.cpp
The file was modifiedclang-tools-extra/clangd/Diagnostics.cpp
Commit 5e0bf6772e2ca450d3433fca8b47ce7bac5a6cc7 by Jonas Devlieghere
[lldb/SWIG] Fix capitalization for case sensitive file systems.
When moving the Python directory I renamed it to python (lowercase) but
didn't update the python.swig file.
The file was modifiedlldb/bindings/python.swig
Commit 06d07ec4a372b55e6fb77bf0b97964bde16a3184 by simon.tatham
[Clang] Handle target-specific builtins returning aggregates.
Summary: A few of the ARM MVE builtins directly return a structure type.
This causes an assertion failure at code-gen time if you try to assign
the result of the builtin to a variable, because the `RValue` created in
`EmitBuiltinExpr` from the `llvm::Value` produced by codegen is always
made by `RValue::get()`, which creates a non-aggregate `RValue` that
will fail an assertion when `AggExprEmitter::withReturnValueSlot` calls
`Src.getAggregatePointer()`. A similar failure occurs if you try to use
the struct return value directly to extract one field, e.g.
`vld2q(address).val[0]`.
The existing code-gen tests for those MVE builtins pass the returned
structure type directly to the C `return` statement, which apparently
managed to avoid that particular code path, so we didn't notice the
crash.
Now `EmitBuiltinExpr` checks the evaluation kind of the builtin's return
value, and does the necessary handling for aggregate returns. I've added
two extra test cases, both of which crashed before this change.
Reviewers: dmgreen, rjmccall
Reviewed By: rjmccall
Subscribers: kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72271
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vld24.c
Commit ed6daa2e1d32e940ac4bd8c31ae05154c5ed9bd3 by riccibrun
[Support][NFC] Add a comment about the semantics of MF_HUGE_HINT flag
The file was modifiedllvm/include/llvm/Support/Memory.h
Commit 356b33516c2e0ef241066dded16d7ecc1f7aa8cc by simon.moll
[NFC,format] Sort switch cases alphabetically
This patch brings the switch cases of `llvm/lib/Support/Triple.cpp` back
into alphabetical order. This was noted during the the review of
https://reviews.llvm.org/D69103
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D72452
The file was modifiedllvm/lib/Support/Triple.cpp
Commit 2fe45e029ddfa65880cfe5c3501db12a81cdcbd2 by riccibrun
[Support][NFC] Make some helper functions "static" in Memory.inc
The file was modifiedllvm/lib/Support/Windows/Memory.inc
The file was modifiedllvm/lib/Support/Unix/Memory.inc
Commit 7bbd4076c1984165568c978ff15b77dbfe52b6f0 by Jonas Devlieghere
[lldb/SWIG] Undo incorrect substitution
The Python directory for the script interpreter is still capitalized.
The file was modifiedlldb/bindings/python.swig
Commit b51fa8670f3d9346cad068aa7300d63eb051069d by ulrich.weigand
[SystemZ] Fix matching another pattern for nxgrk (PR44496)
SystemZDAGToDAGISel::Select will attempt to split logical instruction
with a large immediate constant.  This must not happen if the result
matches one of the z15 combined operations, so the code checks for
those.  However, one of them was missed, causing invalid code to be
generated in the test case for PR44496.
The file was modifiedllvm/test/CodeGen/SystemZ/not-01.ll
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
Commit 460cbabe170e481d4468ef77de1fb08b02a0f2a3 by spatel
[x86] add tests for 2-way splat copy; NFC
Based on code in PR42024: https://bugs.llvm.org/show_bug.cgi?id=42024
The file was modifiedllvm/test/CodeGen/X86/vector-interleave.ll
Commit 002be6cfa2b1de064d672dac6db53c01e9f150b0 by riccibrun
[Support][NFC] Add an explicit unit test for Process::getPageSize()
It turns out that it was only tested indirectly. For now test only on
Linux X86-64 and aarch64.
The file was modifiedllvm/unittests/Support/ProcessTest.cpp
Commit b705fe5686a886e200fd57410c6bc9bad5c21c0e by craig.topper
[TargetLowering][X86] TeachSimplifyDemandedBits to handle cases where
only the sign bit is demanded from a SETCC and can be passed through
If we're doing a compare that only tests the sign bit and only the sign
bit is demanded, we can just bypass the node. This removes one of the
blend dependencies in our v2i64->v2f32 uint_to_fp codegen on pre-sse4.2
targets.
Differential Revision: https://reviews.llvm.org/D72356
The file was modifiedllvm/test/CodeGen/X86/vec_int_to_fp.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit 183b5d38d7cffc10ff9f4914b8879ed5b1976e40 by erik.pilkington
[demangle] Copy back some NFC commits from LLVM
The file was modifiedlibcxxabi/src/demangle/ItaniumDemangle.h
The file was modifiedlibcxxabi/src/demangle/Utility.h
Commit 1a1dbea24df51e441f3517abb8e251df0029dad7 by sd.fertile
[PowerPC] The VK_PLT symbolref modifier is only used on 32-bit ELF.
[NFC]
Fix a conditional that guarded code for execution only on 32-bit ELF by
checking that the Subtarget was not 64-bit and not-Darwin. By adding a
new target ABI (AIX), the condition is no longer correct. This code is
dead for AIX, due to a 'report_fatal_error' for thread local storage
usage earlier in the pipeline, but needs to be modifed as part of
Darwins removal from the PowerPC backend.
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Commit 3408940f736955402b7676e3b8bab6906cc82637 by Ganesh.Gopalasubramanian
[X86] AMD Znver2 (Rome) Scheduler enablement
The patch gives out the details of the znver2 scheduler model. There are
few improvements with respect to execution units, latencies and
throughput when compared with znver1. The tests that were present for
znver1 for llvm-mca tool were replicated. The latencies, execution
units, timeline and throughput information are updated for znver2.
Reviewers: craig.topper, Simon Pilgrim
Differential Revision: https://reviews.llvm.org/D66088
The file was modifiedllvm/test/tools/llvm-mca/X86/variable-blend-read-after-ld-1.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-x87.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/read-after-ld-1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/variable-blend-read-after-ld-2.s
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.td
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-ssse3.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-mwaitx.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-fma.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-aes.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-fsgsbase.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-3.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-avx1.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-5.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-lzcnt.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-prefetchw.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-2.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-rdrand.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-bmi1.s
The file was modifiedllvm/lib/Target/X86/X86.td
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-cmpxchg.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-rdseed.s
The file was modifiedllvm/test/tools/llvm-mca/X86/bzhi-read-after-ld.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse42.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sha.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-cmov.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-6.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse41.s
The file was modifiedllvm/test/tools/llvm-mca/X86/register-file-statistics.s
The file was addedllvm/lib/Target/X86/X86ScheduleZnver2.td
The file was modifiedllvm/test/tools/llvm-mca/X86/cpus.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-adx.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse2.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse4a.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-lea.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-mmx.s
The file was modifiedllvm/test/tools/llvm-mca/X86/bextr-read-after-ld.s
The file was modifiedllvm/test/tools/llvm-mca/X86/sqrt-rsqrt-rcp-memop.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-clflushopt.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-x86_32.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Generic/resources-clzero.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-clzero.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-movbe.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-avx2.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-pclmul.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-popcnt.s
The file was modifiedllvm/test/tools/llvm-mca/X86/read-after-ld-2.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-4.s
The file was modifiedllvm/test/tools/llvm-mca/X86/fma3-read-after-ld-1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver1/resources-clzero.s
The file was modifiedllvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse3.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-x86_64.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-7.s
The file was modifiedllvm/test/MC/X86/x86_long_nop.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-f16c.s
The file was addedllvm/test/tools/llvm-mca/X86/Znver2/resources-bmi2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/fma3-read-after-ld-2.s
Commit 1c545f6dbcbb3ada2dfef2c6afbc1ca8939135cb by epastor
[ms] [X86] Use "P" modifier on all branch-target operands in inline X86
assembly.
Summary: Extend D71677 to apply to all branch-target operands, rather
than special-casing call instructions.
Also add a regression test for llvm.org/PR44272, since this finishes
fixing it.
Reviewers: thakis, rnk
Reviewed By: thakis
Subscribers: merge_guards_bot, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D72417
The file was modifiedclang/test/CodeGen/ms-inline-asm-64.c
The file was modifiedllvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h
The file was modifiedllvm/utils/TableGen/InstrInfoEmitter.cpp
The file was modifiedllvm/lib/MC/MCParser/AsmParser.cpp
The file was modifiedllvm/lib/Target/X86/AsmParser/X86Operand.h
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.td
The file was modifiedllvm/utils/TableGen/X86RecognizableInstr.cpp
The file was modifiedllvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
The file was modifiedllvm/include/llvm/MC/MCInstrDesc.h
The file was modifiedllvm/lib/Target/X86/X86InstrControl.td
Commit b35f5d4914c979282010c0618a331d11a58493ac by sguelton
[clang] Enforce triple in mempcpy test
Fixes
http://lab.llvm.org:8011/builders/llvm-clang-win-x-armv7l/builds/2597
The file was modifiedclang/test/CodeGen/mempcpy-libcall.c
Commit 9949b1a1753aa0f229c5b55ea01ec96f48164d9e by Jessica Paquette
[GlobalISel][AArch64] Import + select LDR*roW and STR*roW patterns
This adds support for selecting a large chunk of the load/store *roW
patterns.
This is pretty much a straight port of
AArch64DAGToDAGISel::SelectAddrModeWRO into GISel. The code is very
similar to the XRO code. The main difference is that in the *roW
patterns, we want to try and fold in an extend, and *possibly* a shift
along with it. A good portion of this patch is refactoring the existing
XRO code.
- Add selectAddrModeWRO
- Factor out the code from selectAddrModeShiftedExtendXReg which is used
by both
selectAddrModeXRO and selectAddrModeWRO into selectExtendedSHL.
This is similar to the function of the same name in
AArch64DAGToDAGISel.
- Add support for extends to the factored out code in selectExtendedSHL.
- Teach getExtendTypeForInst how to handle AND masks that are intended
to be
used in loads/stores (necessary for this addressing mode.)
- Make getExtendTypeForInst not static because moving it made an
annoying diff
and I wanted to have the WRO/XRO functions close to each other while I
was
writing the code.
Differential Revision: https://reviews.llvm.org/D72426
The file was modifiedllvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/load-wro-addressing-modes.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/store-wro-addressing-modes.mir
Commit 4e003aad42d985dade66cd5928d64dd09edecceb by craig.topper
[X86] Add ueq/one fp128 quiet compare tests. NFC
The ONE expansion calls OGT/OLT libcalls which will signal for QNAN. The
UEQ expansion uses unord and eq libcalls which won't signal. We should
probably use those libcalls for ONE with appropriate logic.
Quiet OGT/OLT/OLE/OGE have similar issue, but not sure how to fix those
yet.
The file was modifiedllvm/test/CodeGen/X86/fp128-libcalls-strict.ll
The file was modifiedllvm/test/CodeGen/X86/fp128-compare.ll
Commit 1444e6e2e6f6b76cc9d5aab8b1877926aa6d5597 by Alexander.Richardson
Re-apply "[ELF] Allow getErrPlace() to work before Out::bufferStart is
set"
This time with a fix for the UBSAN failure.
Differential Revision: https://reviews.llvm.org/D70659
The file was modifiedlld/ELF/Target.cpp
The file was modifiedlld/test/ELF/mips-jalr-non-functions.s
Commit 646ca7d7e72e8408b3fa3472018eb9d1c2643ff5 by Alexander.Richardson
MipsDelaySlotFiller: Update registers def-uses for BUNDLE instructions
Summary: In commit b91f239485fb7bb8d29be3e0b60660a2de7570a9 I updated
the MipsDelaySlotFiller to skip BUNDLE instructions. However, in
addition to not considering BUNDLE instructions for the delay slot, we
also need to ensure that the register def-use information is updated.
Not updating this information caused run-time crashes (when using the
out-of-tree CHERI backend) since later definitions could be overwritten
with earlier register values.
Reviewers: atanasyan Reviewed By: atanasyan Differential Revision:
https://reviews.llvm.org/D72254
The file was modifiedllvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
The file was addedllvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts-def-use.mir
Commit fc3367dd5ed4698036c421b23cf4f52cf8aedcae by riverriddle
[mlir] NFC: Move the state for managing SSA value names out of
OperationPrinter and into a new class SSANameState.
Summary: This reduces the complexity of OperationPrinter and simplifies
the code by quite a bit. The SSANameState is now held by ModuleState.
This is in preparation for a future revision that molds ModuleState into
something that can be used by users for caching the printer state, as
well as for implementing printAsOperand style methods.
Depends On D72292
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D72293
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
Commit 61bd19206f61ace4b007838a2ff8884a13ec0374 by eric
[libc++] Explicitly enumerate std::string external instantiations.
The external instantiation of std::string is a problem for libc++.
   Additions and removals of inline functions in string can cause ABI
   breakages, including introducing new symbols.
    This patch aims to:
     (1) Make clear which functions are explicitly instatiated.
     (2) Prevent new functions from being accidentally instantiated.
     (3) Allow a migration path for adding or removing functions from
the
     explicit instantiation over time.
    Although this new formulation is uglier, it is preferable from a
   maintainability and readability standpoint because it explicitly
   enumerates the functions we've chosen to expose in our ABI. Changing
   this list is non-trivial and requires thought and planning.
    (3) is achieved by making it possible to control the extern template
declaration
   separately from it's definition. Meaning we could add a new
definition to
   the dylib, wait for it to roll out, then add the extern template
   declaration to the header. Similarly, we could remove existing extern
   template declarations while still keeping the definition to prevent
ABI
   breakages.
The file was modifiedlibcxx/include/__config
The file was modifiedlibcxx/include/__string
The file was modifiedlibcxx/src/string.cpp
The file was modifiedlibcxx/include/string
Commit c348a2674b5753afde6842d5a6ee75db111167e3 by sledru
[clang-tidy] Refresh the add_new_check.py now that we use a table +
autofix
Reviewers: alexfh
Reviewed By: alexfh
Subscribers: njames93, xazax.hun, mgorny, cfe-commits
Tags: #clang, #clang-tools-extra
Differential Revision: https://reviews.llvm.org/D72421
The file was modifiedclang-tools-extra/clang-tidy/add_new_check.py
Commit 6a69d3c6b3da3d4e7709d11fd52b8e5540265280 by zeratul976
[clangd] Handle DeducedTemplateSpecializationType in TargetFinder
Summary: This is a workaround for
https://bugs.llvm.org/show_bug.cgi?id=42914. Once that is fixed, the
handling in VisitDeducedTyped() should be sufficient.
Fixes https://github.com/clangd/clangd/issues/242
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet,
usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72119
The file was modifiedclang-tools-extra/clangd/unittests/FindTargetTests.cpp
The file was modifiedclang-tools-extra/clangd/FindTarget.cpp
Commit 004ae200a5a818ea87d71e4e686939dec4a8d757 by sledru
phab doc: remove the svn section
The file was modifiedllvm/docs/Phabricator.rst
Commit dbfc516d1f1685b4d11910bceab6625ada4399a2 by sledru
phab doc: also document 'arc land'
The file was modifiedllvm/docs/Phabricator.rst
Commit 0c195ef7c62db1234e3854f8798e1ef413808b18 by sledru
phab doc: Replace or remove references to svn
The file was modifiedllvm/docs/Phabricator.rst
Commit 35ad66fae811c36823b2b91368f142c9d35b8414 by arsenm2
AMDGPU/GlobalISel: Widen 16-bit shift amount sources
This should be legal, but will require future selection work. 16-bit
shift amounts were already removed from being legal, but this didn't
adjust the transformation rules.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
Commit 767aa507a464e46b9a5aaed8cfec0a621f8fc599 by arsenm2
AMDGPU/GlobalISel: Fix argument lowering for vectors of pointers
When these arguments are broken down by the EVT based callbacks, the
pointer information is lost. Hack around this by coercing the register
types to be the expected pointer element type when building the remerge
operations.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
Commit fba1fbb9c7367990a0561a36dbf600fc51847246 by arsenm2
GlobalISel: Don't assert on MoreElements creating vectors
If the original type was a scalar, it should be valid to add elements to
turn it into a vector.
Tests included with following legalization change.
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
Commit f937b43fdb30b67facf616ad394976b08001ee89 by arsenm2
TableGen/GlobalISel: Address fixme
Don't call computeAvailableFunctionFeatures for every instruction.
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
The file was modifiedllvm/test/TableGen/GlobalISelEmitter.td
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
Commit 595ac8c46ea54c6d5dc96e2f35a5759988a657be by arsenm2
GlobalISel: Move getLLTForMVT/getMVTForLLT
As an intermediate step, some TLI functions can be converted to using
LLT instead of MVT. Move this somewhere out of GlobalISel so DAG
functions can use these.
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/Utils.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/Utils.cpp
The file was modifiedllvm/include/llvm/CodeGen/LowLevelType.h
The file was modifiedllvm/lib/CodeGen/LowLevelType.cpp
Commit 0f5f28d000f73b4d0282c579477a4e31402a863e by csigg
Add gdb pretty printer for MutableArrayRef, remove ConstArrayRef.
Reviewers: dblaikie
Reviewed By: dblaikie
Subscribers: merge_guards_bot, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72136
The file was modifiedllvm/utils/gdb-scripts/prettyprinters.py
Commit 8c387cbea76b169f1f8ecc7693797e96567ed896 by Alexander.Richardson
Add builtins for aligning and checking alignment of pointers and
integers
This change introduces three new builtins (which work on both pointers
and integers) that can be used instead of common bitwise arithmetic:
__builtin_align_up(x, alignment), __builtin_align_down(x, alignment) and
__builtin_is_aligned(x, alignment).
I originally added these builtins to the CHERI fork of LLVM a few years
ago to handle the slightly different C semantics that we use for CHERI
[1]. Until recently these builtins (or sequences of other builtins) were
required to generate correct code. I have since made changes to the
default C semantics so that they are no longer strictly necessary (but
using them does generate slightly more efficient code). However, based
on our experience using them in various projects over the past few
years, I believe that adding these builtins to clang would be useful.
These builtins have the following benefit over bit-manipulation and
casts via uintptr_t:
- The named builtins clearly convey the semantics of the operation.
While
checking alignment using __builtin_is_aligned(x, 16) versus
((x & 15) == 0) is probably not a huge win in readably, I personally
find
__builtin_align_up(x, N) a lot easier to read than (x+(N-1))&~(N-1).
- They preserve the type of the argument (including const qualifiers).
When
using casts via uintptr_t, it is easy to cast to the wrong type or
strip
qualifiers such as const.
- If the alignment argument is a constant value, clang can check that it
is
a power-of-two and within the range of the type. Since the semantics of
these builtins is well defined compared to arbitrary bit-manipulation,
it is possible to add a UBSAN checker that the run-time value is a
valid
power-of-two. I intend to add this as a follow-up to this change.
- The builtins avoids int-to-pointer casts both in C and LLVM IR.
In the future (i.e. once most optimizations handle it), we could use
the new
llvm.ptrmask intrinsic to avoid the ptrtoint instruction that would
normally
be generated.
- They can be used to round up/down to the next aligned value for both
integers and pointers without requiring two separate macros.
- In many projects the alignment operations are already wrapped in
macros (e.g.
roundup2 and rounddown2 in FreeBSD), so by replacing the macro
implementation
with a builtin call, we get improved diagnostics for many call-sites
while
only having to change a few lines.
- Finally, the builtins also emit assume_aligned metadata when used on
pointers.
This can improve code generation compared to the uintptr_t casts.
[1] In our CHERI compiler we have compilation mode where all pointers
are implemented as capabilities (essentially unforgeable 128-bit fat
pointers). In our original model, casts from uintptr_t (which is a
128-bit capability) to an integer value returned the "offset" of the
capability (i.e. the difference between the virtual address and the base
of the allocation). This causes problems for cases such as checking the
alignment: for example, the expression `if ((uintptr_t)ptr & 63) == 0`
is generally used to check if the pointer is aligned to a multiple of 64
bytes. The problem with offsets is that any pointer to the beginning of
an allocation will have an offset of zero, so this check always succeeds
in that case (even if the address is not correctly aligned). The same
issues also exist when aligning up or down. Using the alignment builtins
ensures that the address is used instead of the offset. While I have
since changed the default C semantics to return the address instead of
the offset when casting, this offset compilation mode can still be used
by passing a command-line flag.
Reviewers: rsmith, aaron.ballman, theraven, fhahn, lebedev.ri, nlopes,
aqjune Reviewed By: aaron.ballman, lebedev.ri Differential Revision:
https://reviews.llvm.org/D71499
The file was modifiedclang/include/clang/Basic/Builtins.def
The file was modifiedclang/include/clang/Basic/DiagnosticASTKinds.td
The file was addedclang/test/CodeGen/builtin-align-array.c
The file was addedclang/test/CodeGen/builtin-align.c
The file was addedclang/test/Sema/builtin-align.c
The file was modifiedclang/lib/AST/ExprConstant.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was addedclang/test/SemaCXX/builtin-align-cxx.cpp
The file was modifiedclang/lib/CodeGen/CodeGenFunction.h
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was addedclang/test/CodeGen/builtin-align-assumption.c
The file was modifiedclang/docs/LanguageExtensions.rst
Commit ea67737b166fc6cb5fd98874fbd2b4639b2d7ecd by zinenko
[mlir] mlir-cpu-runner test's cblas_interface should export functions on
Windows
This change fixes the build on Windows, so that cblas_interface.dll
exports functions correctly and an implib is created and installed
correctly.
Currently, LLVM cannot be consumed on Windows after it has been
installed in a location because cblas_interface.lib is not
created/installed, thus failing the import check in `LLVMExports.cmake`.
Differential Revision: https://reviews.llvm.org/D72384
The file was modifiedmlir/test/mlir-cpu-runner/include/mlir_runner_utils.h
The file was addedmlir/test/mlir-cpu-runner/include/cblas_interface.h
The file was modifiedmlir/test/mlir-cpu-runner/include/cblas.h
The file was modifiedmlir/test/mlir-cpu-runner/CMakeLists.txt
The file was modifiedmlir/test/mlir-cpu-runner/cblas_interface.cpp
Commit 016bf03ef6fcd9dce43b0c17971f76323f07a684 by zinenko
[mlir] add a missing dependency for Linalg conversion
We were seeing some occasional build failures that would come and go. It
appeared to be this missing dependence.
Differential Revision: https://reviews.llvm.org/D72419
The file was modifiedmlir/lib/Conversion/LinalgToLLVM/CMakeLists.txt
Commit cc95bb1f57c674c0efdfc134eab8ed8c50f2a6e3 by Amara Emerson
[AArch64][GlobalISel] Implement selection of <2 x float> vector splat.
Also requires making G_IMPLICIT_DEF of v2s32 legal.
Differential Revision: https://reviews.llvm.org/D72422
The file was modifiedllvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/opt-shuffle-splat.mir
The file was modifiedllvm/test/CodeGen/AArch64/arm64-rev.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
Commit 255cc5a7603fef251192daab2a3336acbcd9aa1c by arsenm2
CodeGen: Use LLT instead of EVT in getRegisterByName
Only PPC seems to be using it, and only checks some simple cases and
doesn't distinguish between FP. Just switch to using LLT to simplify use
from GlobalISel.
The file was modifiedllvm/lib/Target/Lanai/LanaiISelLowering.h
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.h
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.h
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/Target/Lanai/LanaiISelLowering.cpp
The file was modifiedllvm/lib/Target/Sparc/SparcISelLowering.cpp
The file was modifiedllvm/lib/Target/Mips/MipsISelLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.h
The file was modifiedllvm/lib/Target/Mips/MipsISelLowering.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.cpp
The file was modifiedllvm/lib/Target/Sparc/SparcISelLowering.h
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.h
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit ac53a5f1dc21916f1072031703e0e1833e963454 by arsenm2
GlobalISel: Fix else after return
The file was modifiedllvm/lib/CodeGen/LowLevelType.cpp
Commit f33f3d98e9e6322846c3b997260faf3e1165e0dd by arsenm2
DAG: Don't use unchecked dyn_cast
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Commit 0ea3c7291fb8d463d9c7ae6aaec7a432ef366a51 by arsenm2
GlobalISel: Handle llvm.read_register
Compared to the attempt in bdcc6d3d2638b3a2c99ab3b9bfaa9c02e584993a,
this uses intermediate generic instructions.
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
The file was modifiedllvm/include/llvm/Target/GenericOpcodes.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/read_register.ll
The file was modifiedllvm/include/llvm/Support/TargetOpcodes.def
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit b4a647449fa01bd4e29bce5afef51770cddec664 by arsenm2
TableGen/GlobalISel: Add way for SDNodeXForm to work on timm
The current implementation assumes there is an instruction associated
with the transform, but this is not the case for
timm/TargetConstant/immarg values. These transforms should directly
operate on a specific MachineOperand in the source instruction. TableGen
would assert if you attempted to define an equivalent GISDNodeXFormEquiv
using timm when it failed to find the instruction matcher.
Specially recognize SDNodeXForms on timm, and pass the operand index to
the render function.
Ideally this would be a separate render function type that looks like
void renderFoo(MachineInstrBuilder, const MachineOperand&), but this
proved to be somewhat mechanically painful. Add an optional operand
index which will only be passed if the transform should only look at the
one source operand.
Theoretically it would also be possible to only ever pass the
MachineOperand, and the existing renderers would check the parent. I
think that would be somewhat ugly for the standard usage which may want
to inspect other operands, and I also think MachineOperand should
eventually not carry a pointer to the parent instruction.
Use it in one sample pattern. This isn't a great example, since the
transform exists to satisfy DAG type constraints. This could also be
avoided by just changing the MachineInstr's arbitrary choice of operand
type from i16 to i32. Other patterns have nontrivial uses, but this
serves as the simplest example.
One flaw this still has is if you try to use an SDNodeXForm defined for
imm, but the source pattern uses timm, you still see the "Failed to
lookup instruction" assert. However, there is now a way to avoid it.
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ds.swizzle.mir
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
The file was addedllvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td
The file was modifiedllvm/lib/Target/ARM/ARMInstructionSelector.cpp
The file was modifiedllvm/test/TableGen/GlobalISelEmitter.td
The file was modifiedllvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/include/llvm/Target/GlobalISel/Target.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
Commit 10edb1d0d4a15812a71f8953bba96a4f1fc9d0af by arsenm2
TableGen/GlobalISel: Fix pattern matching of immarg literals
For arguments that are not expected to be materialized with G_CONSTANT,
this was emitting predicates which could never match. It was first
adding a meaningless LLT check, which would always fail due to the
operand not being a register.
Infer the cases where a literal should check for an immediate operand,
instead of a register This avoids needing to invent a special way of
representing timm literal values.
Also handle immediate arguments in GIM_CheckLiteralInt. The comments
stated it handled isImm() and isCImm(), but that wasn't really true.
This unblocks work on the selection of all of the complicated AMDGPU
intrinsics in future commits.
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
The file was modifiedllvm/utils/TableGen/CodeGenInstruction.cpp
The file was modifiedllvm/utils/TableGen/CodeGenIntrinsics.h
The file was modifiedllvm/utils/TableGen/CodeGenTarget.cpp
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/test/TableGen/Common/GlobalISelEmitterCommon.td
The file was addedllvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td
The file was modifiedllvm/utils/TableGen/CodeGenInstruction.h
Commit 58b3dec6c108eb9ae4af2cde5c831743d5605c79 by Jonas Devlieghere
[lldb/Lua] Add lua typemaps for INOUT params
The file was modifiedlldb/bindings/lua.swig
The file was addedlldb/bindings/lua/lua-typemaps.swig
Commit 68c8b6c4cd117cc962155298f0e1d45056ecc001 by riverriddle
[mlir] Use getDenseElementBitwidth instead of
Type::getElementTypeBitWidth.
Summary: Some data values have a different storage width than the
corresponding MLIR type, e.g. bfloat is currently stored as a double.
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D72478
The file was modifiedmlir/lib/IR/Attributes.cpp
The file was modifiedmlir/unittests/IR/AttributeTest.cpp
Commit 25195541349b1d6dfc03bf7511483110bda69b29 by richard
When diagnosing the lack of a viable conversion function, also list
explicit functions that are not candidates.
It's not always obvious that the reason a conversion was not possible is
because the function you wanted to call is 'explicit', so explicitly say
if that's the case.
It would be nice to rank the explicit candidates higher in the
diagnostic if an implicit conversion sequence exists for their
arguments, but unfortunately we can't determine that without potentially
triggering non-immediate-context errors that we're not permitted to
produce.
The file was modifiedclang/test/CXX/dcl.decl/dcl.init/p14-0x.cpp
The file was modifiedclang/test/PCH/cxx-explicit-specifier.cpp
The file was modifiedclang/test/CXX/expr/expr.prim/expr.prim.lambda/p11-1y.cpp
The file was modifiedclang/test/CXX/over/over.match/over.match.funcs/over.match.copy/p1.cpp
The file was modifiedclang/test/CXX/basic/basic.lookup/basic.lookup.qual/namespace.qual/p2.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/SemaCXX/converting-constructor.cpp
The file was modifiedclang/test/SemaCXX/default1.cpp
The file was modifiedclang/test/CXX/drs/dr1xx.cpp
The file was modifiedclang/include/clang/Sema/Overload.h
The file was modifiedclang/lib/Sema/SemaOverload.cpp
The file was modifiedclang/lib/Sema/SemaInit.cpp
The file was modifiedclang/test/SemaCXX/copy-initialization.cpp
The file was modifiedclang/test/SemaCXX/cxx2a-explicit-bool.cpp
The file was modifiedclang/test/CXX/dcl.decl/dcl.init/dcl.init.ref/p5.cpp
The file was modifiedclang/test/CXX/drs/dr15xx.cpp
The file was modifiedclang/test/CXX/special/class.inhctor/p3.cpp
The file was modifiedclang/test/SemaCXX/convert-to-bool.cpp
The file was modifiedclang/include/clang/AST/DeclCXX.h
The file was modifiedclang/test/SemaCXX/conversion-function.cpp
The file was modifiedclang/test/SemaCXX/explicit.cpp
Commit 5fe4679cc9cfb4941b766db07bf3cd928075d204 by arsenm2
AVR: Update for getRegisterByName change
The file was modifiedllvm/lib/Target/AVR/AVRISelLowering.cpp
The file was modifiedllvm/lib/Target/AVR/AVRISelLowering.h
Commit b81c8c6976b987a25fc54fa2bf3524919759a898 by Jonas Devlieghere
[lldb] Remove spurious file
The file was removedlldb/lldb/cmake/modules/FindPythonInterpAndLibs.cmake
Commit cd69e4c74c174101817c9f6b7c02374ac6a7476f by Stanislav.Mekhanoshin
[AMDGPU] Fix bundle scheduling
Bundles coming to scheduler considered free, i.e. zero latency. Fixed.
Differential Revision: https://reviews.llvm.org/D72487
The file was modifiedllvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/scratch-simple.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sub.i16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sint_to_fp.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/misched-killflags.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/min.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/selectcc-opt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uint_to_fp.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/zero_extend.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/setcc-opt.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/packed-op-sel.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/wave32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
Commit 02113918ed6b5e514afd7d1e007131d36ac13f1d by Jason Molenda
When reading Aux file in chunks, read consecutive byte ranges
qemu has a very small maximum packet size (4096) and it actually only
uses half of that buffer for some implementation reason, so when lldb
asks for the register target definitions, the x86_64 definition is
larger than 4096/2 and we need to fetch it in two parts.
This patch and test is fixing a bug in
GDBRemoteCommunicationClient::ReadExtFeature when reading a target file
in multiple parts.  lldb was assuming that it would always get back the
maximum packet size response (4096) instead of using the actual size
received and asking for the next group of bytes.
We now have two tests in gdb_remote_client for unique features of qemu -
TestNestedRegDefinitions.py would test the ability of lldb to follow
multiple levels of xml includes; I opted to create a separate
TestRegDefinitionInParts.py test to test this wrinkle in qemu's gdb
remote serial protocol stub implementation. Instead of combining both
tests into a single test file.
<rdar://problem/49537922>
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
The file was addedlldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/TestRegDefinitionInParts.py
Commit 375371cc8bff7ba02d0a2203f80de5e640fcadf1 by maskray
[ELF] Fix includeInDynsym() when an undefined weak is merged with a lazy
definition
An undefined weak does not fetch the lazy definition. A lazy weak symbol
should be considered undefined, and thus preemptible if .dynsym exists.
D71795 is not quite an NFC. It errors on an R_X86_64_PLT32 referencing
an undefined weak symbol. isPreemptible is false (incorrect) => R_PLT_PC
is optimized to R_PC => in isStaticLinkTimeConstant, an error is emitted
when an R_PC is applied on an undefined weak (considered absolute).
The file was modifiedlld/ELF/Symbols.cpp
The file was modifiedlld/test/ELF/weak-undef-lib.s
Commit 5cabb8357aeb3bbecaef4825c3a594f86ef94c8d by arsenm2
AMDGPU/GlobalISel: Fix G_EXTRACT_VECTOR_ELT mapping for s-v case
If an SGPR vector is indexed with a VGPR, the actual indexing will be
done on the SGPR and produce an SGPR. A copy needs to be inserted inside
the waterwall loop to the VGPR result.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
Commit 35c3d101aee240f6c034f25ff6800fda22a89987 by arsenm2
AMDGPU/GlobalISel: Select G_EXTRACT_VECTOR_ELT
Doesn't try to do the fold into the base register of an add of a
constant in the index like the DAG path does.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
Commit 3727ca313783e23696caeae53c688409555ab0fc by douglas.yung
Relax opcode checks in test for G_READCYCLECOUNTER to check for only a
number instead of a specific number.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
Commit f041e9ad706aee7987c5299427c33424fcabbd0d by richard
CWG2352: Allow qualification conversions during reference binding.
The language wording change forgot to update overload resolution to rank
implicit conversion sequences based on qualification conversions in
reference bindings. The anticipated resolution for that oversight is
implemented here -- we order candidates based on qualification
conversion, not only on top-level cv-qualifiers, including ranking
reference bindings against non-reference bindings if they differ in
non-top-level qualification conversions.
For OpenCL/C++, this allows reference binding between pointers with
differing (nested) address spaces. This makes the behavior of reference
binding consistent with that of implicit pointer conversions, as is the
purpose of this change, but that pre-existing behavior for pointer
conversions is itself probably not correct. In any case, it's now
consistently the same behavior and implemented in only one place.
This reinstates commit de21704ba96fa80d3e9402f12c6505917a3885f4,
reverted in commit d8018233d1ea4234de68d5b4593abd773db79484, with
workarounds for some overload resolution ordering problems introduced by
CWG2352.
The file was modifiedclang/test/CXX/drs/dr23xx.cpp
The file was modifiedclang/lib/Sema/SemaOverload.cpp
The file was modifiedclang/test/SemaObjCXX/arc-overloading.mm
The file was modifiedclang/www/make_cxx_dr_status
The file was modifiedclang/www/cxx_dr_status.html
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Sema/SemaExprCXX.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/SemaOpenCL/address-spaces-conversions-cl2.0.cl
The file was modifiedclang/lib/Sema/SemaInit.cpp
The file was modifiedclang/test/CXX/drs/dr4xx.cpp
The file was modifiedclang/test/SemaCXX/ref-init-ambiguous.cpp
Commit 02c5983310dcd627aecb521e03a16122f42e8a01 by shengchen.kan
[NFC] Style cleanup
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
Commit efabe427b27643839849ebb61fe2e5db37dff0de by thakis
fix a few typos to cycle the bots
The file was modifiedlld/docs/NewLLD.rst
The file was modifiedlld/docs/ld.lld.1
The file was modifiedlld/docs/WebAssembly.rst
The file was modifiedlld/docs/conf.py
Commit 01662aeb5d1fcef4f067caec633d0c85bb3062a7 by thakis
fix another typo to cycle bots
The file was modifiedmlir/docs/Dialects/SPIR-V.md
Commit 21a4710c67a97838dd75cf60ed24da11280800f8 by wmi
[ThinLTO] Pass CodeGenOpts like UnrollLoops/VectorizeLoop/VectorizeSLP
down to pass builder in ltobackend.
Currently CodeGenOpts like UnrollLoops/VectorizeLoop/VectorizeSLP in
clang are not passed down to pass builder in ltobackend when new pass
manager is used. This is inconsistent with the behavior when new pass
manager is used and thinlto is not used. Such inconsistency causes slp
vectorization pass not being enabled in ltobackend for O3 + thinlto
right now. This patch fixes that.
Differential Revision: https://reviews.llvm.org/D72386
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/tools/llvm-lto2/llvm-lto2.cpp
The file was addedlld/test/ELF/lto/slp-vectorize-pm.ll
The file was addedllvm/test/tools/llvm-lto2/X86/slp-vectorize-pm.ll
The file was modifiedllvm/tools/gold/gold-plugin.cpp
The file was modifiedllvm/test/Other/new-pm-defaults.ll
The file was modifiedlld/ELF/CMakeLists.txt
The file was modifiedllvm/include/llvm/LTO/Config.h
The file was modifiedlld/wasm/CMakeLists.txt
The file was modifiedllvm/test/Other/new-pm-thinlto-defaults.ll
The file was modifiedllvm/lib/LTO/LTOBackend.cpp
The file was addedclang/test/CodeGen/thinlto-slp-vectorize-pm.c
The file was modifiedllvm/tools/llvm-lto2/CMakeLists.txt
The file was modifiedclang/lib/CodeGen/BackendUtil.cpp
The file was modifiedlld/COFF/CMakeLists.txt
The file was modifiedlld/ELF/LTO.cpp
The file was addedllvm/test/tools/gold/X86/slp-vectorize-pm.ll
Commit 995c18fc5051850782b1c096233867b8e56e0dea by smeenai
[xray] Remove cl::sub from alias options
Currently running the xray tools generates a number of errors:
$ ./bin/llvm-xray
: for the   -k option: cl::alias must not have cl::sub(), aliased
option's cl::sub() will be used!
: for the   -d option: cl::alias must not have cl::sub(), aliased
option's cl::sub() will be used!
: for the   -o option: cl::alias must not have cl::sub(), aliased
option's cl::sub() will be used!
: for the   -f option: cl::alias must not have cl::sub(), aliased
option's cl::sub() will be used!
: for the   -s option: cl::alias must not have cl::sub(), aliased
option's cl::sub() will be used!
: for the   -r option: cl::alias must not have cl::sub(), aliased
option's cl::sub() will be used!
: for the   -p option: cl::alias must not have cl::sub(), aliased
option's cl::sub() will be used!
: for the   -m option: cl::alias must not have cl::sub(), aliased
option's cl::sub() will be used!
<snip>
Patch by Ryan Mansfield.
Differential Revision: https://reviews.llvm.org/D69386
The file was modifiedllvm/tools/llvm-xray/xray-extract.cpp
The file was modifiedllvm/tools/llvm-xray/xray-converter.cpp
The file was modifiedllvm/tools/llvm-xray/xray-account.cpp
The file was modifiedllvm/tools/llvm-xray/xray-graph-diff.cpp
The file was modifiedllvm/tools/llvm-xray/xray-graph.cpp
The file was modifiedllvm/tools/llvm-xray/xray-stacks.cpp
Commit b38d0d5bdb353f8496a0fc38b9bbee419b41a321 by sylvestre
clang-tidy doc - remove the widths
The file was modifiedclang-tools-extra/docs/clang-tidy/checks/list.rst
Commit 759c90456d418ffe69e1a2b4bcea2792491a6b5a by ibiryukov
[Syntax] Update comment, remove stale FIXME. NFC
The file was modifiedclang/include/clang/Tooling/Syntax/Tokens.h
Commit 8647a72c4a52e0386c0397ce3fbd38121c18b873 by gil.rapaport
[LV] VPValues for memory operation pointers (NFCI)
Memory instruction widening recipes use the pointer operand of their
load/store ingredient for generating the needed GEPs, making it
difficult to feed these recipes with pointers based on other ingredients
or none at all. This patch modifies these recipes to use a VPValue for
the pointer instead, in order to reduce ingredient def-use usage by ILV
as a step towards full VPlan-based def-use relations. The recipes are
constructed with VPValues bound to these ingredients, maintaining
current behavior.
Differential revision: https://reviews.llvm.org/D70865
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
Commit 164da673009ba6c100ce45b6fa9a5dfd3b0b8e38 by hans
Restore order in clang-tidy section of release notes
Major changes are introduction of subsubsections to prevent people
putting new entries in wrong places. I also polished line length and
highlighting.
Patch by Eugene Zelenko!
The file was modifiedclang-tools-extra/docs/ReleaseNotes.rst
Commit 921f871ac438175ca8fcfcafdfcfac4d7ddf3905 by sguelton
Allow system header to provide their own implementation of some builtin
If a system header provides an (inline) implementation of some of their
function, clang still matches on the function name and generate the
appropriate llvm builtin, e.g. memcpy. This behavior is in line with
glibc recommendation « users may not provide their own version of
symbols » but doesn't account for the fact that glibc itself can provide
inline version of some functions.
It is the case for the memcpy function when -D_FORTIFY_SOURCE=1 is on.
In that case an inline version of memcpy calls __memcpy_chk, a function
that performs extra runtime checks. Clang currently ignores the inline
version and thus provides no runtime check.
This code fixes the issue by detecting functions whose name is a builtin
name but also have an inline implementation.
Differential Revision: https://reviews.llvm.org/D71082
The file was addedclang/test/CodeGen/memcpy-nobuiltin.inc
The file was modifiedclang/lib/AST/Decl.cpp
The file was modifiedclang/include/clang/AST/Decl.h
The file was modifiedclang/lib/CodeGen/CGExpr.cpp
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was addedclang/test/CodeGen/memcpy-nobuiltin.c
Commit 45c4b08d8228f64b02b8a4df069aa37d5fa70829 by qiucofan
[NFC] [PowerPC] Add isPredicable for basic instrs
PowerPC uses a dedicated method to check if the machine instr is
predicable by opcode. However, there's a bit `isPredicable` in instr
definition. This patch removes the method and set the bit only to
opcodes referenced in it.
Differential Revision: https://reviews.llvm.org/D71921
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCInstr64Bit.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
Commit ffd0f116754c36146bb21a01b047782ce8a01e2e by kadircet
[clangd] Improve type printing in hover
Summary: Do not include tag keywords when printing types for symbol
names, as it will come from SymbolKind. Also suppress them while
printing definitions to prevent them occuring in template arguments.
Make use of `getAsString`, instead of `print` in all places to have a
consistent style across the file.
Reviewers: sammccall
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, usaxena95,
cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72450
The file was modifiedclang-tools-extra/clangd/unittests/HoverTests.cpp
The file was modifiedclang-tools-extra/clangd/Hover.cpp
Commit abfa27e4f04dd84774bcfe15783942e21be391a5 by kadircet
[clangd] Fix markdown rendering in VSCode
Summary: Eventough it is OK to have a new line without any preceding
spaces in some markdown specifications, VSCode requires two spaces
before a new line to break a line inside a paragraph.
Reviewers: sammccall, ilya-biryukov
Subscribers: MaskRay, jkorous, arphaman, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72462
The file was modifiedclang-tools-extra/clangd/unittests/FormattedStringTests.cpp
The file was modifiedclang-tools-extra/clangd/FormattedString.cpp
Commit 346de9b67228f42eb9b55fa3b426b5dedfdb1d40 by sguelton
Fix several issues with compiler extensions
- Update documentation now that the move to monorepo has been made
- Do not tie compiler extension testing to LLVM_BUILD_EXAMPLES
- No need to specify LLVM libraries for plugins
- Add NO_MODULE option to match Polly specific requirements (i.e.
building the
module *and* linking it statically)
- Issue a warning when building the compiler extension with
LLVM_BYE_LINK_INTO_TOOLS=ON, as it modifies the behavior of clang,
which only
makes sense for testing purpose.
Still mark llvm/test/Feature/load_extension.ll as XFAIL because of a
ManagedStatic dependency that's going to be fixed in a seperate commit.
Differential Revision: https://reviews.llvm.org/D72327
The file was modifiedllvm/test/lit.cfg.py
The file was modifiedllvm/examples/Bye/CMakeLists.txt
The file was modifiedllvm/cmake/modules/AddLLVM.cmake
The file was modifiedpolly/lib/CMakeLists.txt
Commit 67bf9a6154d4b82c6c01aad01141bf08c1bbd0f6 by sjoerd.meijer
[SVEV] Recognise hardware-loop intrinsic loop.decrement.reg
Teach SCEV about the @loop.decrement.reg intrinsic, which has exactly
the same semantics as a sub expression. This allows us to query
hardware-loops, which contain this @loop.decrement.reg intrinsic, so
that we can calculate iteration counts, exit values, etc. of
hardwareloops.
This "int_loop_decrement_reg" intrinsic is defined as "IntrNoDuplicate".
Thus, while hardware-loops and tripcounts now become analysable by SCEV,
this prevents the usual loop transformations from applying
transformations on hardware-loops, which is what we want at this point,
for which I have added test cases for loopunrolling and IndVarSimplify
and LFTR.
Differential Revision: https://reviews.llvm.org/D71563
The file was modifiedllvm/test/Transforms/IndVarSimplify/lftr.ll
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was addedllvm/test/Transforms/LoopUnroll/ARM/dont-unroll-loopdec.ll
The file was modifiedllvm/unittests/Analysis/ScalarEvolutionTest.cpp
Commit 356685a1d8972180f472c1333e8e89dbcc704c1d by sjoerd.meijer
Follow up of 67bf9a6154d4b82c, minor fix in test case, removed duplicate
option
The file was modifiedllvm/test/Transforms/LoopUnroll/ARM/dont-unroll-loopdec.ll
Commit 41f4dfd63ea0fe995ddfba1838aa5ed972cc1377 by jaskiewiczs
[libcxx] Force-cache LIBCXX_CXX_ABI_LIBRARY_PATH
Summary: The `LIBCXX_CXX_ABI_LIBRARY_PATH` CMake variable is cached once
in libcxx/cmake/Modules/HandleLibCXXABI.cmake in the `setup_abi_lib`
macro, and then cached again in libcxx/test/CMakeLists.txt. There, if it
is not set to a value, it is by default set to `LIBCXX_LIBRARY_DIR`.
However, this new value is not actually cached, because the old (empty)
value has been already cached. Use the `FORCE` CMake flag so that it is
saved to the cache.
This should not break anything, because the code changed here previously
had no effect, when it should have.
Reviewers: jroelofs, bcraig, ldionne, EricWF, mclow.lists, vvereschaka,
eastig
Reviewed By: vvereschaka
Subscribers: mgorny, christof, dexonsmith, libcxx-commits
Tags: #libc
Differential Revision: https://reviews.llvm.org/D69169
The file was modifiedlibcxx/test/CMakeLists.txt
Commit e44dedd3631c20bc4a1e62b68919a11168d39354 by jaskiewiczs
[CMake] Support running libc++abi tests in CrossWinToARMLinux cache file
Summary: Now that D71894 has landed, we're able to run libc++abi tests
remotely.
For that we can use the same CMake command as before. The tests can be
run using `ninja check-cxxabi`.
Reviewers: andreil99, vvereschaka, aorlov
Reviewed By: vvereschaka, aorlov
Subscribers: mgorny, kristof.beyls, ldionne, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72459
The file was modifiedclang/cmake/caches/CrossWinToARMLinux.cmake
Commit a1cc19b581443c84fff4c6e6d4e341351ef3203c by sguelton
XFAIL load_extension.ll test on macOS only
Other setup have been fixed by 346de9b67228f42eb9b55fa3b426b5dedfdb1d40
The file was modifiedllvm/test/Feature/load_extension.ll
Commit cfd849840134c4632c2f4fa498dfb93c47825b24 by benny.kra
[MIR] Fix cyclic dependency of MIR formatter
Summary: Move MIR formatter pointer from TargetMachine to
TargetInstrInfo to avoid cyclic dependency between target & codegen.
Reviewers: dsanders, bkramer, arsenm
Subscribers: wdng, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72485
The file was modifiedllvm/include/llvm/Target/TargetMachine.h
The file was modifiedllvm/include/llvm/CodeGen/MachineMemOperand.h
The file was modifiedllvm/lib/CodeGen/MachineOperand.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/lib/CodeGen/MachineInstr.cpp
The file was modifiedllvm/lib/Target/TargetMachine.cpp
The file was modifiedllvm/lib/CodeGen/MIRParser/MIParser.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
The file was modifiedllvm/lib/CodeGen/MIRPrinter.cpp
Commit 498856fca5b9306f545554aeec93c7c058f03eb3 by benny.kra
[LV] Silence unused variable warning in Release builds. NFC.
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 2e66405d8d8ed818cb9310b6c33419bd8d803d96 by llvm-dev
Don't use dyn_cast_or_null if we know the pointer is nonnull.
Fix clang static analyzer null dereference warning by using dyn_cast
instead.
The file was modifiedllvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
Commit 3804ac63d5d8443d0b6826b566e9cbb84d8898f3 by llvm-dev
[X86][AVX] Add tests for v8f32/v8i32 089abcde and 0189abcd shuffles
Mentioned in D66004
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
Commit b2cd273416f82b6c5efeb6138276d9e6b6f8256e by llvm-dev
Fix Wdocumentation warning. NFCI.
The file was modifiedllvm/lib/CodeGen/MachineOutliner.cpp
Commit f3849f739e52510871d11361125f0ef239f11603 by llvm-dev
Fix Wdocumentation warning. NFCI.
The file was modifiedclang/lib/Parse/ParseExpr.cpp
Commit 902974277d507a149e33487d32e4ba58c41451b6 by Raphael Isemann
Data formatters: Look through array element typedefs
Summary: Motivation: When formatting an array of typedefed chars, we
would like to display the array as a string.
The string formatter currently does not trigger because the formatter
lookup does not resolve typedefs for array elements (this behavior is
inconsistent with pointers, for those we do look through pointee
typedefs). This patch tries to make the array formatter lookup somewhat
consistent with the pointer formatter lookup.
Reviewers: teemperor, clayborg
Reviewed By: teemperor, clayborg
Subscribers: clayborg, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D72133
The file was modifiedlldb/source/Symbol/ClangASTContext.cpp
The file was modifiedlldb/source/API/SBType.cpp
The file was modifiedlldb/source/DataFormatters/FormatManager.cpp
The file was addedlldb/packages/Python/lldbsuite/test/functionalities/data-formatter/array_typedef/TestArrayTypedef.py
The file was addedlldb/packages/Python/lldbsuite/test/functionalities/data-formatter/array_typedef/main.cpp
The file was addedlldb/packages/Python/lldbsuite/test/functionalities/data-formatter/array_typedef/Makefile
Commit 870f6917936fdb8050be3ca3c67d9259390c4326 by llvm-dev
Fix "pointer is null" static analyzer warnings. NFCI.
Assert that the pointers are non-null before dereferencing them.
The file was modifiedllvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
Commit 1ccee0e86386762bd742fd067391b6c4be089806 by simon.tatham
[ARM,MVE] Make `vqrshrun` generate the right instruction.
Summary: A copy-paste error in `arm_mve.td` meant that the MVE
`vqrshrun` intrinsic family was generating the `vqshrun` machine
instruction, because in the IR intrinsic call, the rounding flag
argument was set to 0 rather than 1.
Reviewers: dmgreen, MarkMurrayARM, miyuki, ostannard
Reviewed By: dmgreen
Subscribers: kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72496
The file was modifiedclang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
The file was modifiedclang/include/clang/Basic/arm_mve.td
Commit 8c12769f3046029e2a9b4e48e1645b1a77d28650 by diogo.sampaio
[ARM][Thumb2] Fix ADD/SUB invalid writes to SP
Summary: This patch fixes pr23772  [ARM] r226200 can emit illegal thumb2
instruction: "sub sp, r12, #80". The violation was that SUB and ADD
(reg, immediate) instructions can only write to SP if the source
register is also SP. So the above instructions was unpredictable. To
enforce that the instruction t2(ADD|SUB)ri does not write to SP we now
enforce the destination register to be rGPR (That exclude PC and SP).
Different than the ARM specification, that defines one instruction that
can read from SP, and one that can't, here we inserted one that can't
write to SP, and other that can only write to SP as to reuse most of the
hard-coded size optimizations. When performing this change, it uncovered
that emitting Thumb2 Reg plus Immediate could not emit all variants of
ADD SP, SP #imm instructions before so it was refactored to be able to.
(see test/CodeGen/Thumb2/mve-stacksplot.mir where we use a subw sp, sp,
Imm12 variant ) It also uncovered a disassembly issue of adr.w
instructions, that were only written as SUBW instructions (see
llvm/test/MC/Disassembler/ARM/thumb2.txt).
Reviewers: eli.friedman, dmgreen, carwil, olista01, efriedma
Reviewed By: efriedma
Subscribers: john.brawn, efriedma, ostannard, kristof.beyls, hiraditya,
dmgreen, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70680
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/test/MC/ARM/invalid-addsub.s
The file was modifiedllvm/lib/Target/ARM/ARMAsmPrinter.cpp
The file was modifiedllvm/test/MC/ARM/negative-immediates.s
The file was modifiedllvm/test/MC/ARM/register-token-source-loc.s
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir
The file was modifiedllvm/test/CodeGen/Thumb2/peephole-addsub.mir
The file was modifiedllvm/test/MC/Disassembler/ARM/thumb-tests.txt
The file was modifiedllvm/test/MC/Disassembler/ARM/thumb2-v8.txt
The file was modifiedllvm/test/CodeGen/Thumb2/peephole-cmp.mir
The file was modifiedllvm/test/MC/ARM/thumb-diagnostics.s
The file was modifiedllvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
The file was modifiedllvm/lib/Target/ARM/Thumb2InstrInfo.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-stacksplot.mir
The file was modifiedllvm/test/MC/ARM/basic-thumb2-instructions.s
The file was modifiedllvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/fp16-stacksplot.mir
The file was modifiedllvm/test/MC/Disassembler/ARM/thumb2.txt
The file was modifiedllvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
The file was addedllvm/test/CodeGen/Thumb2/bug-subw.ll
The file was modifiedllvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
The file was modifiedllvm/test/MC/Disassembler/ARM/invalid-thumbv7.txt
The file was modifiedllvm/lib/Target/ARM/ARMInstrThumb2.td
Commit 5b7612792aeb5b161fdd69997db2a64b08f075b6 by pavel
[lldb/lua] Make convenience_variables.test compatible with lua-5.1
The file was modifiedlldb/test/Shell/ScriptInterpreter/Lua/convenience_variables.test
Commit e65282deca8455d1cc6d83b7016af9aa374f9f89 by pavel
[lldb/DWARF] Don't automatically search dwo unit attributes
This patch removes the code (deep inside DWARFDebugInfoEntry) which
automagically returned the attributes of the dwo unit DIE when asking
for the attributes of the skeleton unit.  This is fairly hacky, and not
consistent with how llvm DWARF parser operates.
Instead, I change the code the explicitly request (via
GetNonSkeletonUnit) the right unit to search (there were just two places
that needed this). If it turns out we need this more often, we can
create a utility function (external to DWARFUnit) for doing this.
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfoEntry.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
Commit 57a51b689e7b99c694a028104b0b5a69b80fd002 by ibiryukov
[CodeComplete] Suggest 'return nullptr' in functions returning pointers
Reviewers: kadircet
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72497
The file was modifiedclang/lib/Sema/SemaCodeComplete.cpp
The file was modifiedclang/test/CodeCompletion/patterns.cpp
Commit c88e298b69409e35e35ab601592197f5a2bc1c30 by pavel
[lldb] Surpress "bitfield too small" gcc warning
Gcc produces this (technically correct) warning when storing an
explicitly-sized enum in a bitfield. Surpress that by changing the type
of the bitfield to an integer. The same approach is used elsewhere in
llvm (e.g. 56b5eab12).
The file was modifiedlldb/include/lldb/Symbol/DebugMacros.h
Commit 564481aebe18a723c9cfe9ea9ca5808771f7e9d8 by andrew.ng
[Support] ThreadPoolExecutor fixes for Windows/MinGW
Changed ThreadPoolExecutor to no longer use detached threads and instead
to join threads on destruction. This is to prevent intermittent crashing
on Windows when doing a normal full exit, e.g. via exit().
Changed ThreadPoolExecutor to be a ManagedStatic so that it can be
stopped on llvm_shutdown(). Without this, it would only be stopped in
the destructor when doing a full exit. This is required to avoid
intermittent crashing on Windows due to a race condition between the
ThreadPoolExecutor starting up threads and the process doing a fast
exit, e.g. via _exit().
The Windows crashes appear to only occur with the MSVC static runtimes
and are more frequent with the debug static runtime.
These changes also prevent intermittent deadlocks on exit with the MinGW
runtime.
Differential Revision: https://reviews.llvm.org/D70447
The file was modifiedllvm/lib/Support/Parallel.cpp
The file was modifiedlld/Common/ErrorHandler.cpp
Commit e4d672971030fe26dbb8237038038c3ff9ae7541 by Tatyana Krasnukha
[lldb][tests] Take into account all parent's categories when traverse
folders upwards
This is needed to not re-write parent's categories by categories of a
nested folder, e.g. commands/expression/completion specify "cmdline"
category, however it still belongs to parent's "expression" category.
The sentinel ".categories" in the test-suite root directory is no longer
needed.
Differential Revision: https://reviews.llvm.org/D71905
The file was modifiedlldb/packages/Python/lldbsuite/test/test_result.py
The file was removedlldb/packages/Python/lldbsuite/test/.categories
Commit 9ba151274869c377921a09ba0bd635412da755ef by Tatyana Krasnukha
[lldb][test] NFC, re-use _getTestPath() function
The file was modifiedlldb/packages/Python/lldbsuite/test/test_result.py
Commit 76e9c2a9870e36415eb343d28942a42296f85597 by ulrich.weigand
[FPEnv] Generate constrained FP comparisons from clang
Update the IRBuilder to generate constrained FP comparisons in
CreateFCmp when IsFPConstrained is true, similar to the other places in
the IRBuilder.
Also, add a new CreateFCmpS to emit signaling FP comparisons, and use it
in clang where comparisons are supposed to be signaling
(currently, only when emitting code for the <, <=, >, >= operators).
Note that there is currently no way to add fast-math flags to a
constrained FP comparison, since this is implemented as an intrinsic
call that returns a boolean type, and FMF are only allowed for calls
returning a floating-point type. However, given the discussion around
https://bugs.llvm.org/show_bug.cgi?id=42179, it seems that FCmp itself
really shouldn't have any FMF either, so this is probably OK.
Reviewed by: craig.topper
Differential Revision: https://reviews.llvm.org/D71467
The file was addedclang/test/CodeGen/fpconstrained-cmp-float.c
The file was modifiedllvm/include/llvm/IR/IRBuilder.h
The file was modifiedclang/lib/CodeGen/CGExprScalar.cpp
The file was addedclang/test/CodeGen/fpconstrained-cmp-double.c
Commit b3af8ab7f83c2a825c584ddedf5cc9207ca66b44 by Tatyana Krasnukha
[lldb][tests] Cleanup '.categories'
The file was removedlldb/packages/Python/lldbsuite/test/commands/command/script_alias/.categories
The file was modifiedlldb/packages/Python/lldbsuite/test/functionalities/data-formatter/data-formatter-objc/.categories
The file was removedlldb/packages/Python/lldbsuite/test/commands/command/history/.categories
The file was removedlldb/packages/Python/lldbsuite/test/commands/expression/no-deadlock/.categories
The file was removedlldb/packages/Python/lldbsuite/test/commands/command/source/.categories
The file was addedlldb/packages/Python/lldbsuite/test/commands/command/.categories
The file was removedlldb/packages/Python/lldbsuite/test/commands/command/script/.categories
Commit b1bb5ce96d349689085eab38121c85737de1fcaa by diogo.sampaio
Reverting, broke some bots. Need further investigation.
Summary: This reverts commit 8c12769f3046029e2a9b4e48e1645b1a77d28650.
Reviewers:
Subscribers:
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir
The file was modifiedllvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
The file was modifiedllvm/lib/Target/ARM/Thumb2InstrInfo.cpp
The file was modifiedllvm/test/MC/ARM/thumb-diagnostics.s
The file was removedllvm/test/CodeGen/Thumb2/bug-subw.ll
The file was modifiedllvm/test/MC/Disassembler/ARM/invalid-thumbv7.txt
The file was modifiedllvm/test/MC/Disassembler/ARM/thumb-tests.txt
The file was modifiedllvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
The file was modifiedllvm/test/MC/ARM/invalid-addsub.s
The file was modifiedllvm/test/MC/ARM/basic-thumb2-instructions.s
The file was modifiedllvm/test/CodeGen/Thumb2/peephole-addsub.mir
The file was modifiedllvm/test/CodeGen/Thumb2/fp16-stacksplot.mir
The file was modifiedllvm/test/MC/Disassembler/ARM/thumb2.txt
The file was modifiedllvm/lib/Target/ARM/ARMAsmPrinter.cpp
The file was modifiedllvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
The file was modifiedllvm/test/MC/ARM/register-token-source-loc.s
The file was modifiedllvm/test/MC/Disassembler/ARM/thumb2-v8.txt
The file was modifiedllvm/test/CodeGen/Thumb2/peephole-cmp.mir
The file was modifiedllvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-stacksplot.mir
The file was modifiedllvm/test/MC/ARM/negative-immediates.s
The file was modifiedllvm/lib/Target/ARM/ARMInstrThumb2.td
Commit e49c3c8f2ef97bdf256ca76f3d001eeb79361d56 by benny.kra
Sprinkle some constexpr on default ctors so the compiler can diagnose
unused instances. NFCI.
The file was modifiedmlir/lib/Dialect/VectorOps/VectorOps.cpp
The file was modifiedmlir/include/mlir/IR/Value.h
The file was modifiedmlir/include/mlir/IR/Attributes.h
The file was modifiedmlir/include/mlir/IR/Types.h
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVOps.cpp
Commit 4569f63ae1cb520ce28f08f4800dfbcd5f255eed by sjoerd.meijer
ARMLowOverheadLoops: a few more dbg msgs to better trace rejected TP
loops. NFC.
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
Commit 2f2f41e12c5201b600d887d22ce5cb4afd2ff594 by jan.kratochvil
RangeDataVector: Support custom sorting for D63540
As suggested by @labath extended RangeDataVector so that user can
provide custom sorting of the Entry's `data' field for D63540.
       https://reviews.llvm.org/D63540
RangeData functions were used just by RangeDataVector (=after I removed
them LLDB still builds fine) which no longer uses them so I removed
them.
Differential revision: https://reviews.llvm.org/D72460
The file was modifiedlldb/include/lldb/Utility/RangeMap.h
The file was modifiedlldb/unittests/Utility/RangeMapTest.cpp
Commit 3772ea9dd9368cfdc73595854c143bc3f16a5ade by sam.parker
[ARM][MVE] Tail predicate VMAX,VMAXA,VMIN,VMINA
Add the MVE min and max instructions to our tail predication whitelist.
Differential Revision: https://reviews.llvm.org/D72502
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was modifiedllvm/unittests/Target/ARM/MachineInstrTest.cpp
Commit f0fd11df7d5488e2747f26a3bfcf62459fee54ad by ulrich.weigand
[FPEnv] Invert sense of MIFlag::FPExcept flag
In D71841 we inverted the sense of the SDNode-level flag to ensure all
nodes default to potentially raising FP exceptions unless otherwise
specified -- i.e. if we forget to propagate the flag somewhere, the
effect is now only lost performance, not incorrect code.
However, the related flag at the MI level still defaults to nodes not
raising FP exceptions unless otherwise specified. To be fully on the
(conservatively) safe side, we should invert that flag as well.
This patch does so by replacing MIFlag::FPExcept with
MIFlag::NoFPExcept.
(Note that this does also introduce an incompatible change in the MIR
format.)
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D72466
The file was modifiedllvm/lib/CodeGen/MIRParser/MILexer.h
The file was modifiedllvm/lib/CodeGen/MIRParser/MILexer.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-constrained-fp-intrinsics-flags.ll
The file was modifiedllvm/lib/CodeGen/MachineInstr.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZElimCompare.cpp
The file was modifiedllvm/lib/CodeGen/MIRPrinter.cpp
The file was modifiedllvm/test/CodeGen/X86/fast-isel-select-sse.ll
The file was modifiedllvm/test/CodeGen/X86/fp-intrinsics-flags-x86_64.ll
The file was modifiedllvm/include/llvm/CodeGen/MachineInstr.h
The file was modifiedllvm/test/CodeGen/X86/fp-intrinsics-flags.ll
The file was modifiedllvm/test/CodeGen/X86/sqrt-fastmath-mir.ll
The file was modifiedllvm/lib/CodeGen/MIRParser/MIParser.cpp
Commit e20a3b9b6c028ef3fea92ddb19e98db45e3d0509 by Tatyana Krasnukha
[lldb][tests][NFC] Unify variable naming convention
The file was modifiedlldb/packages/Python/lldbsuite/test/configuration.py
The file was modifiedlldb/packages/Python/lldbsuite/test/dotest_args.py
The file was modifiedlldb/packages/Python/lldbsuite/test/lldbtest.py
The file was modifiedlldb/packages/Python/lldbsuite/test/test_result.py
The file was modifiedlldb/packages/Python/lldbsuite/test/dotest.py
Commit 3eea082535e232b35e6b2dab45dd81728b2ae7f4 by Tatyana Krasnukha
[lldb][tests] Make it possible to expect failure for a whole category
There already are decorators and "--excluded" option to mark
test-cases/files as expected to fail. However, when a new test file is
added and it which relates to a feature that a target doesn't support,
this requires either adding decorators to that file or modifying the
file provided as "--excluded" option value.
The purpose of this patch is to avoid any modifications in such cases.
E.g. if a target doesn't support "watchpoints" and passes
"--xfail-category watchpoint" to dotest, a testing job will not fail
after a new watchpoint-related test file is added.
Differential Revision: https://reviews.llvm.org/D71906
The file was modifiedlldb/packages/Python/lldbsuite/test/test_result.py
The file was modifiedlldb/packages/Python/lldbsuite/test/configuration.py
The file was modifiedlldb/packages/Python/lldbsuite/test/dotest.py
The file was modifiedlldb/packages/Python/lldbsuite/test/dotest_args.py
Commit bac995d97896c1e785d709da24c55f0e050eb899 by arsenm2
AMDGPU/GlobalISel: Clamp G_ZEXT source sizes
Also clamps G_SEXT/G_ANYEXT, but the implementation is more limited so
fewer cases actually work.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
Commit b19c0810e56b552d31247dcff081643799fd97fb by a.bataev
[LIBOMPTARGET]Ignore empty target descriptors.
Summary: If the dynamically loaded module has been compiled with
-fopenmp-targets and has no target regions, it has empty target
descriptor. It leads to a crash at the runtime if another module has at
least one target region and at least one entry in its descriptor. The
runtime library is unable to load the empty binary descriptor and
terminates the execution. Caused by a clang-offload-wrapper.
Reviewers: grokos, jdoerfert
Subscribers: caomhin, kkwli0, openmp-commits
Tags: #openmp
Differential Revision: https://reviews.llvm.org/D72472
The file was addedopenmp/libomptarget/test/offloading/dynamic_module.c
The file was modifiedopenmp/libomptarget/src/rtl.cpp
Commit 6e3ca962fafb3d2a31279c49f0cde60eb626a002 by jh7370
[DebugInfo] Improve error message text
Unlike most of our errors in the debug line parser, the "no end of
sequence" message was missing any reference to which line table it
refererred to. This change adds the offset to this message.
Reviewed by: dblaikie
Differential Revision: https://reviews.llvm.org/D72443
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
The file was modifiedlld/test/ELF/undef.s
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/debug_line_invalid.test
The file was modifiedllvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp
Commit 7e02406f6cf180a8c89ce64665660e7cc9dbc23e by jh7370
[DebugInfo][NFC] Remove unused variable/fix variable naming
Reviewed by: MaskRay
Differential Revision: https://reviews.llvm.org/D72159
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
Commit cdd05f2aea3b950a4e2c496175117e6b47b2a050 by development
[NFC] format unittest for ExprMutAnalyzer
This formatting is a preparation for review in
https://reviews.llvm.org/D54943 to separate pure formatting changes from
actual testing changes.
The file was modifiedclang/unittests/Analysis/ExprMutationAnalyzerTest.cpp
Commit d864d93496c5fd0cc473953ab825f07e3d4c4e86 by nemanja.i.ibm
[PowerPC] Handle constant zero bits in BitPermutationSelector
We currently crash when analyzing an AssertZExt node that has some bits
that are constant zeros (i.e. as a result of an and with a constant).
This issue was reported in https://bugs.llvm.org/show_bug.cgi?id=41088
and this patch fixes that.
Differential revision: https://reviews.llvm.org/D72038
The file was addedllvm/test/CodeGen/PowerPC/pr41088.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Commit bdd88b7ed3956534a0a71b1ea2bc88c69d48f9b7 by David.Chisnall
Add support for __declspec(guard(nocf))
Summary: Avoid using the `nocf_check` attribute with Control Flow Guard.
Instead, use a new `"guard_nocf"` function attribute to indicate that
checks should not be added on indirect calls within that function. Add
support for
`__declspec(guard(nocf))` following the same syntax as MSVC.
Reviewers: rnk, dmajor, pcc, hans, aaron.ballman
Reviewed By: aaron.ballman
Subscribers: aaron.ballman, tomrittervg, hiraditya, cfe-commits,
llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D72167
The file was modifiedclang/include/clang/Basic/Attr.td
The file was modifiedclang/lib/CodeGen/CGCall.cpp
The file was addedclang/test/Sema/attr-guard_nocf.c
The file was addedclang/test/CodeGen/guard_nocf.c
The file was addedclang/test/CodeGenCXX/guard_nocf.cpp
The file was modifiedclang/include/clang/Basic/AttrDocs.td
The file was modifiedllvm/test/CodeGen/ARM/cfguard-checks.ll
The file was modifiedllvm/lib/Transforms/CFGuard/CFGuard.cpp
The file was modifiedllvm/test/CodeGen/AArch64/cfguard-checks.ll
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
The file was modifiedllvm/test/CodeGen/X86/cfguard-checks.ll
Commit e9331a56fead1823d528d6412828fb9e16fd62ff by Adrian Prantl
Add missing nullptr checks.
GetPersistentExpressionStateForLanguage() can return a nullptr if it
cannot construct a typesystem. This patch adds missing nullptr checks at
all uses.
Inspired by rdar://problem/58317195
Differential Revision: https://reviews.llvm.org/D72413
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangExpressionSourceCode.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangUserExpression.cpp
The file was modifiedlldb/source/Target/ABI.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ASTResultSynthesizer.cpp
The file was modifiedlldb/source/Expression/REPL.cpp
The file was modifiedlldb/source/Expression/UserExpression.cpp
Commit 5e7beb0a4146267f1d65c57543e67ca158aca4aa by gabor.marton
[analyzer] Add PlacementNewChecker
Summary: This checker verifies if default placement new is provided with
pointers to sufficient storage capacity.
Noncompliant Code Example:
#include <new>
void f() {
   short s;
   long *lp = ::new (&s) long;
}
Based on SEI CERT rule MEM54-CPP
https://wiki.sei.cmu.edu/confluence/display/cplusplus/MEM54-CPP.+Provide+placement+new+with+properly+aligned+pointe
This patch does not implement checking of the alignment.
Reviewers: NoQ, xazax.hun
Subscribers: mgorny, whisperity, xazax.hun, baloghadamsoftware, szepet,
rnkovacs, a.sidorin, mikhail.ramalho, donat
Tags: #clang
Differential Revision: https://reviews.llvm.org/D71612
The file was modifiedclang/docs/analyzer/checkers.rst
The file was modifiedclang/include/clang/StaticAnalyzer/Checkers/Checkers.td
The file was addedclang/test/Analysis/placement-new.cpp
The file was modifiedclang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
The file was addedclang/lib/StaticAnalyzer/Checkers/CheckPlacementNew.cpp
The file was addedclang/test/Analysis/placement-new-user-defined.cpp
Commit 0b032d7ba7157b62cd0d39f8d2dc0b0efa57a710 by antiagainst
[mlir][spirv] Fix typos related to (de)serialization.
Fix typos related to (de)serialization of spv.selection.
Differential Revision: https://reviews.llvm.org/D72503
The file was modifiedmlir/lib/Dialect/SPIRV/Serialization/Serializer.cpp
The file was modifiedmlir/lib/Dialect/SPIRV/Serialization/Deserializer.cpp
Commit 26cdaeb1f05ba140011a43ef1ea8a37d3cf416d9 by spatel
[InstCombine] add tests for fsub; NFC
Conflicting/missing canonicalizations are visible in PR44509:
https://bugs.llvm.org/show_bug.cgi?id=44509
The file was modifiedllvm/test/Transforms/InstCombine/fsub.ll
Commit fbb64aa69835c8e3e9efe0afc8a73058b5a0fb3c by yhs
[BPF] extend BTF_KIND_FUNC to cover global, static and extern funcs
Previously extern function is added as BTF_KIND_VAR. This does not work
well with existing BTF infrastructure as function expected to use
BTF_KIND_FUNC and BTF_KIND_FUNC_PROTO.
This patch added extern function to BTF_KIND_FUNC. The two bits 0:1 of
btf_type.info are used to indicate what kind of function it is:
0: static
1: global
2: extern
Differential Revision: https://reviews.llvm.org/D71638
The file was modifiedllvm/test/CodeGen/BPF/BTF/extern-var-func.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/static-var-readonly-sec.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/static-var.ll
The file was modifiedllvm/lib/Target/BPF/BTFDebug.h
The file was modifiedllvm/test/CodeGen/BPF/BTF/func-source.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/extern-global-var.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/static-var-derived-type.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/func-void.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/local-var.ll
The file was modifiedllvm/test/CodeGen/BPF/CORE/offset-reloc-union.ll
The file was modifiedllvm/lib/Target/BPF/BTF.h
The file was modifiedllvm/test/CodeGen/BPF/BTF/extern-var-struct-weak.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/extern-var-struct.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/func-func-ptr.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/func-typedef.ll
The file was addedllvm/test/CodeGen/BPF/BTF/static-func.ll
The file was modifiedllvm/test/CodeGen/BPF/CORE/offset-reloc-basic.ll
The file was modifiedllvm/lib/Target/BPF/BTFDebug.cpp
The file was modifiedllvm/test/CodeGen/BPF/BTF/static-var-inited-sec.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/func-non-void.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/extern-var-func-weak.ll
The file was modifiedllvm/test/CodeGen/BPF/CORE/offset-reloc-multilevel.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/static-var-zerolen-array.ll
The file was addedllvm/test/CodeGen/BPF/BTF/extern-func-arg.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/static-var-inited.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/static-var-sec.ll
The file was modifiedllvm/test/CodeGen/BPF/CORE/offset-reloc-struct-array.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/filename.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/extern-var-section.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/static-var-readonly.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/extern-var-weak-section.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/binary-format.ll
The file was addedllvm/test/CodeGen/BPF/BTF/extern-builtin.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/extern-var-func-weak-section.ll
The file was modifiedllvm/test/CodeGen/BPF/CORE/offset-reloc-struct-anonymous.ll
The file was modifiedllvm/test/CodeGen/BPF/BTF/func-unused-arg.ll
Commit 4c5a4514d14537cae5459e03d1fea422664b3bc2 by sam.mccall
[clangd] Fix targetDecl() on certain usage of ObjC properties.
Summary: In particular there's a common chain:

OpaqueValueExpr->PseudoObjectExpr->ObjCPropertyRefExpr->ObjCPropertyDecl
and we weren't handling the first two edges
Reviewers: dgoldman, kadircet
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, jfb, usaxena95,
cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72494
The file was modifiedclang-tools-extra/clangd/FindTarget.cpp
The file was modifiedclang-tools-extra/clangd/unittests/FindTargetTests.cpp
Commit 504b3fe5bfed7ea24c7c74f563ef6a8214e24223 by llvmgnsyncbot
[gn build] Port 5e7beb0a414
The file was modifiedllvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn
Commit a5bdada09defc15d2b009314306f4fcb8fa8458d by llvm-dev
[X86][AVX] lowerShuffleAsLanePermuteAndShuffle - consistently normalize
multi-input shuffle elements
We only use lowerShuffleAsLanePermuteAndShuffle for unary shuffles at
the moment, but we should consistently handle lane index calculations
for multiple inputs in both the AVX1 and AVX2 paths.
Minor (almost NFC) tidyup as I'm hoping to use
lowerShuffleAsLanePermuteAndShuffle for binary shuffles soon.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit cdc9592bf1acb6d8012a4867d2a22458945dcceb by llvm-dev
Fix "pointer is null" static analyzer warning. NFCI.
Use cast<> instead of dyn_cast<> since we know that the pointer should
be valid (and is dereferenced immediately).
The file was modifiedclang/lib/ARCMigrate/ObjCMT.cpp
Commit cce4676d6d78ba56e929bd37d65c2667390b68c7 by llvm-dev
Fix "pointer is null" static analyzer warning. NFCI.
Use castAs<> instead of getAs<> since the pointer is dereferenced
immediately below and castAs will perform the null assertion for us.
The file was modifiedclang/lib/ARCMigrate/ObjCMT.cpp
Commit ff92e469caefff9f86e5e812c08b9bba582be5d3 by inouehrs
[examples] Add missing dependency in llvm examples
To fix build failure with BUILD_SHARED_LIBS=ON
The file was modifiedllvm/examples/Kaleidoscope/BuildingAJIT/Chapter5/Server/CMakeLists.txt
The file was modifiedllvm/examples/Kaleidoscope/BuildingAJIT/Chapter5/CMakeLists.txt
The file was modifiedllvm/examples/LLJITExamples/LLJITWithCustomObjectLinkingLayer/CMakeLists.txt
Commit dfed052fb3ecef53bf01612ec3fc7df73c2134b7 by jasonliu
[AIX] Allow vararg calls when all arguments reside in registers
Summary: This patch pushes the AIX vararg unimplemented error diagnostic
later and allows vararg calls so long as all the arguments can be passed
in register. This patch extends the AIX calling convention
implementation to initialize GPR(s) for vararg float arguments. On AIX,
both GPR(s) and FPR are allocated for floating point arguments. The
GPR(s) are only initialized for vararg calls, otherwise the callee is
expected to retrieve the float argument in the FPR.
f64 in AIX PPC32 requires special handling in order to allocated and
initialize 2 GPRs. This is performed with bitcast, SRL, truncation to
initialize one GPR for the MSW and bitcast, truncations to initialize
the other GPR for the LSW.
A future patch will follow to add support for arguments passed on the
stack.
Patch provided by: cebowleratibm
Reviewers: sfertile, ZarkoCA, hubert.reinterpretcast
Differential Revision: https://reviews.llvm.org/D71013
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was addedllvm/test/CodeGen/PowerPC/aix-cc-altivec.ll
The file was removedllvm/test/CodeGen/PowerPC/aix_cc_abi.ll
The file was addedllvm/test/CodeGen/PowerPC/aix-cc-abi.ll
Commit fd8ded99fe6e9fcae2c98ccad25d6562c5fa8a14 by llvm-dev
Fix "pointer is null" static analyzer warning. NFCI.
Use castAs<> instead of getAs<> since the pointer is dereferenced
immediately below and castAs will perform the null assertion for us.
The file was modifiedclang/lib/CodeGen/CGVTables.cpp
Commit 4d1e23e3b3cd7c72a8b24dc5acb7e13c58a8de37 by maskray
[AArch64] Add function attribute "patchable-function-entry" to add NOPs
at function entry
The Linux kernel uses -fpatchable-function-entry to implement
DYNAMIC_FTRACE_WITH_REGS for arm64 and parisc. GCC 8 implemented
-fpatchable-function-entry, which can be seen as a generalized form of
-mnop-mcount. The N,M form (function entry points before the Mth NOP) is
currently only used by parisc.
This patch adds N,0 support to AArch64 codegen. N is represented as the
function attribute "patchable-function-entry". We will use a different
function attribute for M, if we decide to implement it.
The patch reuses the existing patchable-function pass, and
TargetOpcode::PATCHABLE_FUNCTION_ENTER which is currently used by XRay.
When the integrated assembler is used, __patchable_function_entries will
be created for each text section with the SHF_LINK_ORDER flag to prevent
--gc-sections (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93197) and
COMDAT (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93195) issues.
Retrospectively, __patchable_function_entries should use a PC-relative
relocation type to avoid the SHF_WRITE flag and dynamic relocations.
"patchable-function-entry"'s interaction with Branch Target
Identification is still unclear (see
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92424 for GCC discussions).
Reviewed By: peter.smith
Differential Revision: https://reviews.llvm.org/D72215
The file was modifiedllvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
The file was modifiedllvm/include/llvm/CodeGen/AsmPrinter.h
The file was addedllvm/test/Verifier/invalid-patchable-function-entry.ll
The file was modifiedllvm/lib/CodeGen/PatchableFunction.cpp
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was addedllvm/test/CodeGen/AArch64/patchable-function-entry.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
Commit a8fbdc576990653e92ce1d766659005678fd8514 by maskray
[X86] Support function attribute "patchable-function-entry"
For x86-64, we diverge from GCC -fpatchable-function-entry in that we
emit multi-byte NOPs.
Differential Revision: https://reviews.llvm.org/D72220
The file was addedllvm/test/CodeGen/X86/patchable-function-entry.ll
The file was modifiedllvm/lib/Target/X86/X86MCInstLower.cpp
Commit a44c434b68e515ce9f2627367c83ff6b22328261 by maskray
Support function attribute patchable_function_entry
This feature is generic. Make it applicable for AArch64 and X86 because
the backend has only implemented NOP insertion for AArch64 and X86.
Reviewed By: nickdesaulniers, aaron.ballman
Differential Revision: https://reviews.llvm.org/D72221
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
The file was addedclang/test/Sema/patchable-function-entry-attr.c
The file was modifiedclang/include/clang/Basic/Attr.td
The file was modifiedclang/include/clang/Basic/AttrDocs.td
The file was addedclang/test/Sema/patchable-function-entry-attr.cpp
The file was modifiedclang/test/Misc/pragma-attribute-supported-attributes-list.test
The file was addedclang/test/CodeGen/patchable-function-entry.c
The file was modifiedclang/lib/CodeGen/CodeGenFunction.cpp
Commit f17ae668a96eeb69f0664f126cf672e1a05754d2 by maskray
[Driver][CodeGen] Add -fpatchable-function-entry=N[,0]
In the backend, this feature is implemented with the function attribute
"patchable-function-entry". Both the attribute and XRay use
TargetOpcode::PATCHABLE_FUNCTION_ENTER, so the two features are
incompatible.
Reviewed By: ostannard, MaskRay
Differential Revision: https://reviews.llvm.org/D72222
The file was modifiedclang/test/CodeGen/patchable-function-entry.c
The file was modifiedclang/include/clang/Basic/DiagnosticDriverKinds.td
The file was addedclang/test/Driver/fpatchable-function-entry.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/lib/Driver/XRayArgs.cpp
The file was modifiedclang/include/clang/Basic/CodeGenOptions.def
The file was modifiedclang/lib/CodeGen/CodeGenFunction.cpp
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
Commit 2d077d6dfa7909a21293ebdac81488367628e0fa by maskray
[ELF] Make TargetInfo::writeIgotPlt a no-op
RELA targets don't read initial .got.plt entries. REL targets (ARM,
x86-32) write the address of the IFUNC resolver to the entry
(`write32le(buf, s.getVA())`).
The default writeIgotPlt() is not meaningful. Make it a no-op. AArch64
and x86-64 will have 0 as initial .got.plt entries associated with
IFUNC.
Reviewed By: peter.smith
Differential Revision: https://reviews.llvm.org/D72474
The file was modifiedlld/ELF/Target.cpp
The file was modifiedlld/ELF/Target.h
The file was modifiedlld/test/ELF/aarch64-gnu-ifunc-plt.s
The file was modifiedlld/test/ELF/gnu-ifunc-plt.s
Commit f678fc7660b36ce0ad6ce4f05eaa28f3e9fdedb5 by craig.topper
[LegalizeVectorOps] Improve handling of multi-result operations.
This system wasn't very well designed for multi-result nodes. As a
consequence they weren't consistently registered in the LegalizedNodes
map leading to nodes being revisited for different results.
I've removed the "Result" variable from the main LegalizeOp method and
used a SDNode* instead. The result number from the incoming Op SDValue
is only used for deciding which result to return to the caller. When
LegalizeOp is called it should always register a legalized result for
all of its results. Future calls for any other result should be pulled
for the LegalizedNodes map.
Legal nodes will now register all of their results in the map instead of
just the one we were called for.
The Expand and Promote handling to use a vector of results similar to
LegalizeDAG. Each of the new results is then re-legalized and logged in
the LegalizedNodes map for all of the Results for the node being
legalized. None of the handles register their own results now. And none
call ReplaceAllUsesOfValueWith now.
Custom handling now always passes result number 0 to LowerOperation.
This matches what LegalizeDAG does. Since the introduction of STRICT
nodes, I've encountered several issues with X86's custom handling being
called with an SDValue pointing at the chain and our custom handlers
using that to get a VT instead of result 0. This should prevent us from
having any more of those issues. On return we will update the
LegalizedNodes map for all results so we shouldn't call the custom
handler again for each result number.
I want to push SDNode* further into the Expand and Promote handlers, but
I've left that for a follow to keep this patch size down. I've created a
dummy SDValue(Node, 0) to keep the handlers working.
Differential Revision: https://reviews.llvm.org/D72224
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
The file was modifiedllvm/test/CodeGen/X86/avx512-cmp.ll
Commit ef239972614cc3c67006f9c298fcfa841818dc77 by Raphael Isemann
[lldb] Remove FieldDecl stealing hack by rerouting indirect imports to
the original AST
Summary: This is a port of D67803 that was about preventing indirect
importing to our scratch context when evaluating expressions.
D67803 already has a pretty long explanation of how this works, but the
idea is that instead of importing declarations indirectly over the
expression AST (i.e., Debug info AST -> Expression AST -> scratch AST)
we instead directly import the declaration from the debug info AST to
the scratch AST.
The difference from D67803 is that here we have to do this in the
ASTImporterDelegate (which is our ASTImporter subclass we use in LLDB).
It has the same information as the ExternalASTMerger in D67803 as it can
access the ClangASTImporter (which also keeps track of where Decls
originally came from).
With this patch we can also delete the FieldDecl stealing hack in the
ClangASTSource (this was only necessary as the indirect imports caused
the creation of duplicate Record declarations but we needed the fields
in the Record decl we originally found in the scratch ASTContext).
This also fixes the current gmodules failures where we fail to find
std::vector fields after an indirect import over the expression AST
(where it seems even our FieldDecl stealing hack can't save us from).
Reviewers: shafik, aprantl
Reviewed By: shafik
Subscribers: JDevlieghere, lldb-commits, mib, labath, friss
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D72507
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangASTSource.cpp
The file was modifiedlldb/source/Symbol/ClangASTImporter.cpp
Commit 572b9f468ad6844795fec29a7e671ba64d82e8c2 by Jonas Devlieghere
[lldb/Lua] Support loading Lua modules
Implements the command script import command for Lua.
Differential revision: https://reviews.llvm.org/D71825
The file was addedlldb/test/Shell/ScriptInterpreter/Lua/command_script_import.test
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Lua/Lua.h
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Lua/Lua.cpp
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp
The file was addedlldb/test/Shell/ScriptInterpreter/Lua/Inputs/testmodule.lua
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.h
Commit a5230ac10b0dac9a1981838209b4cbc84870c08c by daniel_l_sanders
Update the attribution policy to use the 'Author' property of a git
commit
Summary: The older method of adding 'Patch by John Doe' is documented in
the
`Attribution of Changes` section to support correct attribution of
commits that pre-date the adoption of git.
Reviewers: hfinkel, aaron.ballman, mehdi_amini
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72468
The file was modifiedllvm/docs/DeveloperPolicy.rst
Commit 13ec473b9d4bd4f7a558272932b7c0806171c666 by gabor.marton
[analyzer] Move PlacementNewChecker to alpha
The file was modifiedclang/include/clang/StaticAnalyzer/Checkers/Checkers.td
The file was modifiedclang/test/Analysis/placement-new-user-defined.cpp
The file was modifiedclang/test/Analysis/placement-new.cpp
Commit b590e0fd810e4caf59ab83b04654d42e18faaafb by craig.topper
[TargetLowering][ARM][X86] Change softenSetCCOperands handling of ONE to
avoid spurious exceptions for QNANs with strict FP quiet compares
ONE is currently softened to OGT | OLT. But the libcalls for OGT and OLT
libcalls will trigger an exception for QNAN. At least for X86 with
libgcc. UEQ on the other hand uses UO | OEQ. The UO and OEQ libcalls
will not trigger an exception for QNAN.
This patch changes ONE to use the inverse of the UEQ lowering. So we now
produce O & UNE. Technically the existing behavior was correct for a
signalling ONE, but since I don't know how to generate one of those from
clang that seemed like something we can deal with later as we would need
to fix other predicates as well. Also removing spurious exceptions
seemed better than missing an exception.
There are also problems with quiet OGT/OLT/OLE/OGE, but those are harder
to fix.
Differential Revision: https://reviews.llvm.org/D72477
The file was modifiedllvm/test/CodeGen/Thumb2/float-cmp.ll
The file was modifiedllvm/test/CodeGen/X86/fp128-libcalls-strict.ll
The file was modifiedllvm/test/CodeGen/X86/fpcmp-soft-fp.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/fp128-compare.ll
Commit 9cd985815abf88bd77bb67f7b9cc80f2032cbbc7 by sbc
[lld][WebAssembly] Add libcall symbols to the link when LTO is being
used.
This code is copied almost verbatim from the equivalent change to the
ELF linker:
- https://reviews.llvm.org/D50017
- https://reviews.llvm.org/D50475
The upshot is that libraries containing libcall (such as compiler-rt and
libc) can be compiled with LTO.
Fixes PR41384
Differential Revision: https://reviews.llvm.org/D71738
The file was modifiedlld/wasm/Driver.cpp
The file was modifiedlld/wasm/Symbols.cpp
The file was addedlld/test/wasm/lto/Inputs/libcall-archive.ll
The file was addedlld/test/wasm/lto/libcall-archive.ll
The file was modifiedlld/wasm/InputFiles.h
The file was modifiedlld/wasm/Symbols.h
Commit 815a3f54331c39f2b400776f448dd29b3b03243b by Jonas Devlieghere
[CMake] Fix modules build after DWARFLinker reorganization
Create a dedicate module for the DWARFLinker and make it depend on
intrinsics gen.
The file was modifiedllvm/include/llvm/module.modulemap
The file was modifiedllvm/lib/DWARFLinker/CMakeLists.txt
Commit f28972facc1fce9589feab9803e3e8cfad01891c by Jan Korous
[clang] Fix out-of-bounds memory access in ComputeLineNumbers
Differential Revision: https://reviews.llvm.org/D72409
The file was modifiedclang/unittests/Basic/SourceManagerTest.cpp
The file was modifiedclang/lib/Basic/SourceManager.cpp
Commit ba91dffafe4d348b469d8ae2b7b1cd00754f72f1 by maskray
[Driver][PowerPC] Move powerpcspe logic from cc1 to Driver
Follow-up of D72014. It is more appropriate to use a target feature
instead of a SubTypeArch to express the difference.
Reviewed By: #powerpc, jhibbits
Differential Revision: https://reviews.llvm.org/D72433
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
The file was modifiedclang/lib/Driver/ToolChains/Arch/PPC.cpp
The file was modifiedclang/test/Preprocessor/init.c
The file was modifiedclang/test/Driver/ppc-features.cpp
Commit 55d7b22277e1c5e710bac7d4d4dc09db3a22dad8 by steveire
[ASTMatchers] Make test more clear about what it is verifying
The file was modifiedclang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
Commit 0c29d3ff2233696f663ae34a8aeda23c750ac68f by listmail
[Tests] Precommit tests showing default branch padding on skylake
A follow up patch will change the default for the compiler, but not the
assembler, just making sure we have testing for each in place.
The file was addedllvm/test/CodeGen/X86/align-branch-boundary-default.ll
The file was addedllvm/test/CodeGen/X86/align-branch-boundary-default.s
Commit 77da826edad0a7b906c734c6bee3489ef495c746 by Raphael Isemann
[lldb] Make CompleteTagDeclsScope completion order deterministic
Summary: We iterate over `m_decls_to_complete` to complete declarations.
As
`m_decls_to_complete` is a set the iteration order can be
non-deterministic. The order is currently only non-deterministic when we
have a large set of decls that need to be completed (i.e. more than 32
decls, as otherwise the SmallPtrSet is just a linear-searched list).
This doesn't really fix any specific bug or has any really observable
change in behavior as the order in which we import should not influence
any semantics. However the order we create decls/types is now always
deterministic which should make debugging easier.
Reviewers: labath, mib, shafik, davide
Reviewed By: shafik, davide
Subscribers: davide, abidh, JDevlieghere, lldb-commits, mgrang
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D72495
The file was modifiedlldb/source/Symbol/ClangASTImporter.cpp
Commit 9e13cff44d6b8b9c9c8420870132931c218707cb by Raphael Isemann
[lldb] Fix TestClangASTContext.TestFunctionTemplateInRecordConstruction
in Debug builds
Summary: In Debug builds we call VerifyDecl in
ClangASTContext::CreateFunctionDeclaration which in turn calls
`getAccess` on the created FunctionDecl. As we passed in a RecordDecl as
the DeclContext for the FunctionDecl, we end up hitting the assert in
`getAccess` that checks that we never have a Decl inside a Record
without a valid AccessSpecifier. FunctionDecls are never in RecordDecls
(that would be a CXXMethodDecl) so setting a access specifier would not
be the correct way to fix this.
Instead this patch does the same thing that
DWARFASTParserClang::ParseSubroutine is doing: We pass in the
FunctionDecl with the TranslationUnit as the DeclContext. That's not
ideal but it is how we currently do it when creating our debug info AST,
so the unit test should do the same.
Reviewers: shafik
Reviewed By: shafik
Subscribers: aprantl, JDevlieghere, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D72359
The file was modifiedlldb/unittests/Symbol/TestClangASTContext.cpp
Commit 4ffcec40acebae7161ac7426edc68290bbaca2b8 by aaron
Implement new AST matcher hasAnyCapture to match on LambdaExpr captures.
Accepts child matchers cxxThisExpr to match on capture of this and also
on varDecl.
The file was modifiedclang/docs/LibASTMatchersReference.html
The file was modifiedclang/lib/ASTMatchers/Dynamic/Registry.cpp
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchers.h
The file was modifiedclang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
Commit f3db1aad2796c62f0d188a74f2901c18e51843c2 by sylvestre
MakeUniqueCheck.cpp: explicit the fact that there is an autofix for this
checker
The file was modifiedclang-tools-extra/clang-tidy/modernize/MakeUniqueCheck.cpp
Commit faeeb71a17344171f814144213ac4fbc93be28fd by sylvestre
clang-tidy doc: Refresh the list of checkers and polish the script
The file was modifiedclang-tools-extra/docs/clang-tidy/checks/list.rst
The file was modifiedclang-tools-extra/clang-tidy/add_new_check.py
Commit 71cee218619033115f5e0c7656efc8cee93180e9 by craig.topper
[TargetLowering] Use SelectionDAG::getSetCC and remove a repeated call
to getSetCCResultType in softenSetCCOperands. NFCI
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit 68cd283f3b074e3b64b9f65e93ceb2de6807c72d by sylvestre
clang-tidy doc: unbreak the CI
The file was modifiedclang-tools-extra/docs/clang-tidy/checks/list.rst
Commit a5a6fd3f95a9ecc3ef8732192ce0fd7749135311 by eugenis
Summary: update macro for OFF_T so that sanitizer works on AARCH64.
Reviewers: vitalybuka, eugenis, MaskRay
Reviewed By: eugenis, MaskRay
Subscribers: MaskRay, kristof.beyls, #sanitizers, llvm-commits, jkz, scw
Tags: #sanitizers, #llvm
Differential Revision: https://reviews.llvm.org/D72367
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_s390.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/symbolizer/sanitizer_wrappers.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_netbsd.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_posix.h
Commit 1a8c996a8894a6ae2bf3b98780972bc7bdb6b8e6 by Jonas Devlieghere
[lldb/Scripts] Remove buildbot.py
This file is outdated and still references SVN. Buildbots are configured
through the zorg repository.
The file was removedlldb/scripts/buildbot.py
Commit e6d219122d5a94fa8642c67c391aeb47fc032c89 by Jonas Devlieghere
[lldb/Scripts] Remove remote-build.py
With Xcode gone this is no longer relevant.
The file was removedlldb/scripts/Python/remote-build.py
Commit 7c47a3719a9e587fdf993637dc09d97b5397483b by Jonas Devlieghere
[lldb/Scripts] Move android script from underneath Python dir
The scripts root directory already contains python scripts. No need to
keep this one nested under a dedicated Python directory.
The file was removedlldb/scripts/Python/android/host_art_bt.py
The file was addedlldb/scripts/android/host_art_bt.py
The file was removedlldb/scripts/Python/use_lldb_suite.py
Commit a9052b4dfc1b25bd58480668d221365495fa9101 by Vedant Kumar
[AArch64] Add isAuthenticated predicate to MCInstDesc
Add a predicate to MCInstDesc that allows tools to determine whether an
instruction authenticates a pointer. This can be used by diagnostic
tools to hint at pointer authentication failures.
Differential Revision: https://reviews.llvm.org/D70329
rdar://55089604
The file was modifiedllvm/include/llvm/MC/MCInstrDesc.h
The file was modifiedllvm/include/llvm/Target/Target.td
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was modifiedllvm/utils/TableGen/InstrDocsEmitter.cpp
The file was modifiedllvm/utils/TableGen/InstrInfoEmitter.cpp
The file was modifiedllvm/unittests/Target/AArch64/InstSizes.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/utils/TableGen/CodeGenInstruction.h
The file was modifiedllvm/utils/TableGen/CodeGenInstruction.cpp
Commit 7ce92dc0b4bcc1044052a06df3f07a94eb890823 by Jonas Devlieghere
[lldb/Test] Bypass LLDB_TEST_COMMON_ARGS for certain dotest args (NFC)
Rather than serializing every argument through LLDB_TEST_COMMON_ARGS, we
can pass some of them directly using their CMake variable. Although this
does introduce some code duplication between lit's site config and the
lldb-dotest utility, it also means that it becomes easier to override
these values (WIP).
The file was modifiedlldb/test/API/lit.cfg.py
The file was modifiedlldb/test/API/CMakeLists.txt
The file was modifiedlldb/utils/lldb-dotest/lldb-dotest.in
The file was modifiedlldb/test/API/lit.site.cfg.py.in
Commit c5adcdc5c88a89241b1150824fc44370c62c7132 by Jonas Devlieghere
[lldb/Utils] Remove vim-lldb
The vim-lldb plugin is unmaintained and doesn't work with a recent vim
installation that uses Python 3. This removes it from the LLDB
repository. The code is still available under lldb-tools on GitHub like
we did with for lldb-mi. (https://github.com/lldb-tools/vim-lldb)
Differential revision: https://reviews.llvm.org/D72541
The file was removedlldb/utils/vim-lldb/plugin/lldb.vim
The file was removedlldb/utils/vim-lldb/python-vim-lldb/lldb_controller.py
The file was removedlldb/utils/vim-lldb/python-vim-lldb/plugin.py
The file was removedlldb/utils/vim-lldb/README
The file was removedlldb/utils/vim-lldb/python-vim-lldb/vim_signs.py
The file was removedlldb/utils/vim-lldb/python-vim-lldb/vim_panes.py
The file was removedlldb/utils/vim-lldb/python-vim-lldb/vim_ui.py
The file was removedlldb/utils/vim-lldb/doc/lldb.txt
The file was removedlldb/utils/vim-lldb/python-vim-lldb/import_lldb.py
Commit 4c00dbf22d7f0ad005444b412b450ee4b4779b6a by Vedant Kumar
lldbutil: Forward ASan launch info to test inferiors
This allows an unsanitized test process which loads a sanitized DSO (the
motivating example is a Swift runtime dylib) to launch on Darwin.
rdar://57290132
Differential Revision: https://reviews.llvm.org/D71379
The file was modifiedlldb/test/API/lit.cfg.py
The file was modifiedlldb/packages/Python/lldbsuite/test/lldbutil.py
Commit 987bf8b6c14613da907fa78330415e266b97a036 by Stanislav.Mekhanoshin
Let targets adjust operand latency of bundles
This reverts the AMDGPU DAG mutation implemented in D72487 and gives a
more general way of adjusting BUNDLE operand latency.
It also replaces FixBundleLatencyMutation with adjustSchedDependency
callback in the AMDGPU, fixing not only successor latencies but
predecessors' as well.
Differential Revision: https://reviews.llvm.org/D72535
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
The file was modifiedllvm/lib/CodeGen/ScheduleDAGInstrs.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
Commit d3ba1e026dbc44e9097ce6ea1c92d065f1fe33e8 by Jonas Devlieghere
[lldb/Reproducer] Add SBReproducer::Replay overload (again)
I modified the SBAPI under the assumption that nobody was using the old
API yet. However, that turns out to be false. So instead of adding the
deafault argument I've reintroduced the old API and made the new one an
overload.
The file was modifiedlldb/include/lldb/API/SBReproducer.h
The file was modifiedlldb/source/API/SBReproducer.cpp
Commit 7a38468e34eeeb59e80b176b97213d205d8d9b41 by richard
Only destroy static locals if they have non-trivial destructors.
This fixes a regression introduced in
2b4fa5348ee157b6b1a1af44d0137ca8c7a71573 that caused us to emit
shutdown-time destruction for variables with ARC ownership, using
C++-specific functions that don't exist in C implementations.
The file was modifiedclang/lib/CodeGen/CGDecl.cpp
The file was addedclang/test/CodeGenObjC/initialize-function-static.m
Commit e05e219926f90ccab927b7b1af6d14aa6dd52571 by Vedant Kumar
[LockFileManager] Make default waitForUnlock timeout a parameter, NFC
Patch by Xi Ge!
The file was modifiedllvm/include/llvm/Support/LockFileManager.h
The file was modifiedllvm/lib/Support/LockFileManager.cpp
Commit 064087581ab98cca7254b4d0f12ecbed13da2692 by mtrofin
[NFC][InlineCost] Factor cost modeling out of CallAnalyzer traversal.
Summary: The goal is to simplify experimentation on the cost model.
Today, CallAnalyzer decides 2 things: legality, and benefit. The
refactoring keeps legality assessment in CallAnalyzer, and factors
benefit evaluation out, as an extension.
Reviewers: davidxl, eraman
Reviewed By: davidxl
Subscribers: kamleshbhalui, fedor.sergeev, hiraditya,
baloghadamsoftware, haicheng, a.sidorin, Szelethus, donat.nagy, dkrupp,
llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71733
The file was modifiedllvm/lib/Analysis/InlineCost.cpp
Commit ca4a55fabbbebef1752fd4e2913c28bb8b510621 by antiagainst
[mlir] NFC: put C++ code emission classes in their own files
This exposes thse classes so that they can be used in interfaces.
Differential Revision: https://reviews.llvm.org/D72514
The file was addedmlir/lib/TableGen/OpClass.cpp
The file was modifiedmlir/lib/TableGen/CMakeLists.txt
The file was addedmlir/include/mlir/TableGen/OpClass.h
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
Commit 397215cc309df1171a198b11cab3b241db9441db by antiagainst
[mlir][ods] Support dialect specific content emission via hooks
Thus far we can only generate the same set of methods even for
operations in different dialects. This is problematic for dialects that
want to generate additional operation class methods programmatically,
e.g., a special builder method or attribute getter method. Apparently we
cannot update the OpDefinitionsGen backend every time when such a need
arises. So this CL introduces a hook into the OpDefinitionsGen backend
to allow dialects to emit additional methods and traits to operation
classes.
Differential Revision: https://reviews.llvm.org/D72514
The file was modifiedmlir/include/mlir/TableGen/Operator.h
The file was addedmlir/include/mlir/TableGen/ODSDialectHook.h
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
Commit 1b8c84b8dd5a4a294943a6a6f0631d2d3a1f9f27 by richard
Improve precision of documentation comment.
The file was modifiedclang/include/clang/AST/Decl.h
Commit ceb801612a678bdffe7e7bf163bd0eed9c9b73a2 by Jessica Paquette
[AArch64] Don't generate libcalls for wide shifts on Darwin
Similar to cff90f07cb5cc3.
Darwin doesn't always use compiler-rt, and so we can't assume that these
functions are available (at least on arm64).
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/shift_minsize.ll
Commit f4df7f4701d80ce6a2f5674db50f87fbd2dad82f by richard
Remove redundant implicit cast creation.
FindCompositePointerType has already cast the operands to the composite
type for us in the case where it succeeds.
The file was modifiedclang/lib/Sema/SemaExpr.cpp
Commit fbf915f01d46e005146f01553a5d7c6619d19597 by richard
Add a FIXME and corresponding test coverage for some suspicious behavior
forming composite ObjC pointer types in comparisons.
The file was modifiedclang/test/SemaObjC/arc.m
The file was modifiedclang/test/SemaObjCXX/arc-ptr-comparison.mm
The file was modifiedclang/lib/Sema/SemaExpr.cpp
Commit 9a6f4d451ca7aa06b94a407015fbadb456bc09ef by richard
Clean up and slightly generalize implementation of composite pointer
type computation, in preparation for P0388R4, which adds another few
cases here.
We now properly handle forming multi-level composite pointer types
involving nested Objective-C pointer types (as is consistent with
including them as part of the notion of 'similar types' on which this
rule is based). We no longer lose non-CVR qualifiers on nested pointer
types.
The file was modifiedclang/lib/Sema/SemaExprCXX.cpp
The file was modifiedclang/test/SemaObjCXX/composite-objc-pointertype.mm
The file was addedclang/test/SemaOpenCLCXX/address-space-cond.cl
Commit 44e0daf16e6985eb44ea9a629402852dbff9cb0b by thakis
driver: Allow -fdebug-compilation-dir=foo in joined form.
All 130+ f_Group flags that take an argument allow it after a '=',
except for fdebug-complation-dir. Add a Joined<> alias so that it
behaves consistently with all the other f_Group flags.
(Keep the old Separate flag for backwards compat.)
The file was modifiedclang/test/Driver/integrated-as.s
The file was modifiedclang/test/Driver/clang_f_opts.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/test/Driver/cl-options.c
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/test/CodeGen/debug-info-compilation-dir.c
The file was modifiedclang/test/Driver/fembed-bitcode.c
Commit 1d2cd2c0b7d978e22a50e918af708ba67e87c2c1 by maskray
[Driver] Fix OptionClass of -fconvergent-functions and -fms-volatile
(Joined -> Flag)
The file was modifiedclang/include/clang/Driver/Options.td
Commit 9b23407063ca41901e9e272bacf8b33eee8251c4 by saar
[Concepts] Fix MarkUsedTemplateParameters for exprs
D41910 introduced a recursive visitor to MarkUsedTemplateParameters, but
disregarded the 'Depth' parameter, and had incorrect assertions. This
fixes the visitor and removes the assertions.
The file was modifiedclang/lib/Sema/SemaTemplateDeduction.cpp
Commit de0a2247115729eade8249267a47f96f070a7666 by alexandre.ganea
Remove umask tests
These tests were added in 18627115f4d2db5dc73207e0b5312f52536be7dd and
e08b59f81d950bd5c8b8528fcb3ac4230c7b736c for validating a refactoring.
Removing because they break on ACL-controlled folders on Ubuntu, and
their added value is low.
Differential Revision: https://reviews.llvm.org/D70854
The file was removedclang/test/Misc/permissions.cpp
The file was removedllvm/test/Other/umask.ll
Commit 7c816492197aefbaa2ea3ba0e391f7c6905956bc by Tom.Tan
[COFF] Align ARM64 range extension thunks at instruction boundary
RangeExtensionThunkARM64 is created for out-of-range branches on Windows
ARM64 because branch instructions has limited bits to encode target
address. Currently, RangeExtensionThunkARM64 is appended to its
referencing COFF section from object file at link time without any
alignment requirement, so if size of the preceding COFF section is not
aligned to instruction boundary (4 bytes), RangeExtensionThunkARM64 will
emit thunk instructions at unaligned address which is never a valid
branch target on ARM64, and usually triggers invalid instruction
exception when branching to it.
This PR fixes it by requiring such thunks to align at 4 bytes.
Differential revision: https://reviews.llvm.org/D72473
The file was modifiedlld/test/COFF/arm64-thunks.s
The file was modifiedlld/COFF/Chunks.h
Commit bb2553175ac3cc6223ff379b266ee1c23a468d66 by craig.topper
[TargetLowering][ARM][Mips][WebAssembly] Remove the ordered FP compare
from RunttimeLibcalls.def and all associated usages
Summary: This always just used the same libcall as unordered, but the
comparison predicate was different. This change appears to have been
made when targets were given the ability to override the predicates.
Before that they were hardcoded into the type legalizer. At that time we
never inverted predicates and we handled ugt/ult/uge/ule compares by
emitting an unordered check ORed with a ogt/olt/oge/ole checks. So only
ordered needed an inverted predicate. Later ugt/ult/uge/ule were
optimized to only call a single libcall and invert the compare.
This patch removes the ordered entries and just uses the inverting logic
that is now present. This removes some odd things in both the Mips and
WebAssembly code.
Reviewers: efriedma, ABataev, uweigand, cameron.mcinally, kpn
Reviewed By: efriedma
Subscribers: dschuff, sdardis, sbc100, arichardson, jgravelle-google,
kristof.beyls, hiraditya, aheejin, sunfish, atanasyan, Petar.Avramovic,
llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72536
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was modifiedllvm/lib/Target/Mips/Mips16ISelLowering.cpp
The file was modifiedllvm/include/llvm/IR/RuntimeLibcalls.def
The file was modifiedllvm/lib/Target/ARM/ARMLegalizerInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit a701be8f036accef9a3dab62fa4baa70ea330a80 by czhengsz
[SCEV] [NFC] add more test cases for range of addrecexpr with nsw flag
The file was modifiedllvm/test/Analysis/ScalarEvolution/range_nw_flag.ll
Commit 4134d706d9bc48d1634e0d95a5c1698f5fcfd06e by qiucofan
[NFC] [PowerPC] Update mi-peephole-splat test
Use script to re-generate the test case, for easier comparison with
future patches.
The file was modifiedllvm/test/CodeGen/PowerPC/mi-peephole-splat.ll
Commit 4a32cd11acd7c38f5e0b587d724935ab7a9938a6 by mjbedy
[AMDGPU] Remove unnecessary v_mov from a register to itself in WQM
lowering.
Summary:
- SI Whole Quad Mode phase is replacing WQM pseudo instructions with
v_mov instructions. While this is necessary for the special handling of
moving results out of WWM live ranges, it is not necessary for WQM live
ranges. The result is a v_mov from a register to itself after every WQM
operation. This change uses a COPY psuedo in these cases, which allows
the register allocator to coalesce the moves away.
Reviewers: tpr, dstuttard, foad, nhaehnle
Reviewed By: nhaehnle
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl,
dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71386
The file was modifiedllvm/test/CodeGen/AMDGPU/wqm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wqm.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
Commit 695804508db048fe3403f2b8bc690633a471a40b by Amara Emerson
Mark the test/Feature/load_extension.ll test as unsupported on Darwin.
With plugins and examples enabled, this XPASSes. Mark it as unsupported
until the owner investigates what's going on.
The file was modifiedllvm/test/Feature/load_extension.ll
Commit 69806808b918adc9b24bee05654b1d6dad91ef74 by craig.topper
[X86] Use ReplaceAllUsesWith instead of ReplaceAllUsesOfValueWith to
simplify some code. NFCI
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit fcad5b298c7859d7f10908fab7b82983e286bb8d by maskray
[X86][Disassembler] Simplify readPrefixes
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
Commit 5fe5c0a60f9a5f32da4316ba0d1732a1e439703b by craig.topper
[X86] Preserve fpexcept property when turning strict_fp_extend and
strict_fp_round into stack operations.
We use the stack for X87 fp_round and for moving from SSE f32/f64 to X87
f64/f80. Or from X87 f64/f80 to SSE f32/f64.
Note for the SSE<->X87 conversions the conversion always happens in the
X87 domain. The load/store ops in the X87 instructions are able to
signal exceptions.
The file was modifiedllvm/lib/Target/X86/X86InstrFPStack.td
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit c2ddfa876fa90008f1b4ff611256ad5dd4b36d96 by craig.topper
[X86] Simplify code by removing an unreachable condition. NFCI
For X87<->SSE conversions, the SSE type is always smaller than the X87
type. So we can always use the smallest type for the memory type.
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit 60346bdbd73da9c944d50ea5dcecad71a05105ac by csigg
Add test for GDB pretty printers.
Reviewers: dblaikie, aprantl, davide, JDevlieghere
Reviewed By: aprantl
Subscribers: jmorse, aprantl, merge_guards_bot, mgorny, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72321
The file was addeddebuginfo-tests/llvm-prettyprinters/gdb/lit.local.cfg
The file was addeddebuginfo-tests/llvm-prettyprinters/gdb/prettyprinters.cpp
The file was addeddebuginfo-tests/llvm-prettyprinters/gdb/prettyprinters.gdb
The file was modifieddebuginfo-tests/CMakeLists.txt
The file was modifieddebuginfo-tests/lit.cfg.py
Commit 81a3d987ced0905bef2e3055bf77ec174bb631c7 by craig.topper
[X86] Remove dead code from X86DAGToDAGISel::Select that is no longer
needed now that we don't mutate strict fp nodes. NFC
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit 0e322c8a1f20ab04ce4f6bc538846859707f2d69 by nikita.ppv
[InstCombine] Preserve nuw on sub of geps (PR44419)
Fix https://bugs.llvm.org/show_bug.cgi?id=44419 by preserving the nuw on
sub of geps. We only do this if the offset has a multiplication as the
final operation, as we can't be sure the operations is nuw in the other
cases without more thorough analysis.
Differential Revision: https://reviews.llvm.org/D72048
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineInternal.h
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
The file was modifiedllvm/test/Transforms/InstCombine/sub-gep.ll
Commit ad36d29eaed62e33eabab8ffd2006b9ff5fbd719 by nikita.ppv
[LoopSimplify] Regenerate test checks; NFC
For D72519.
The file was modifiedllvm/test/Transforms/LoopSimplify/basictest.ll
Commit 142ba7d76af4a66037fd180db371da19f35ef5f3 by nikita.ppv
[LoopRotate] Add tests for rotate with switch; NFC
For D72420.
The file was addedllvm/test/Transforms/LoopRotate/switch.ll
Commit 87407fc03c82d880cc42330a8e230e7a48174e3c by nunoplopes
DSE: fix bug where we would only check libcalls for name rather than
whole decl
The file was addedllvm/test/Transforms/DeadStoreElimination/libcalls2.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/libcalls.ll
The file was modifiedllvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
Commit 5d069f4314a0d8b124a563e61d161c3c3d3b0536 by flo
[X86] Add more complex tests for vector masks used with AND/OR/XOR.
Additional test cases for D72524.
The file was modifiedllvm/test/CodeGen/X86/v8i1-masks.ll
Commit ce35010d782cb5a69102ad7785eb747f6d747eb4 by llvm-dev
[X86][AVX] Add lowerShuffleAsLanePermuteAndSHUFP lowering
Add initial support for lowering v4f64 shuffles to SHUFPD(VPERM2F128(V1,
V2), VPERM2F128(V1, V2)), eventually this could be used for v8f32 (and
maybe v8f64/v16f32) but I'm being conservative for the initial
implementation as only v4f64 can always succeed.
This currently is only called from lowerShuffleAsLanePermuteAndShuffle
so only gets used for unary shuffles, and we limit this to cases where
we use upper elements as otherwise concating 2 xmm shuffles is probably
the better case.
Helps with poor shuffles mentioned in D66004.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
Commit 08275a52d83e623f0347fd9396c18f4d21a15c90 by llvm-dev
Fix copy+paste typo in shuffle test name
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
Commit 9c74fb402e1b7aad4a509a49ab4792154b8ba2c8 by koraq
[Sema] Improve -Wrange-loop-analysis warnings.
No longer generate a diagnostic when a small trivially copyable type is
used without a reference. Before the test looked for a POD type and had
no size restriction. Since the range-based for loop is only available in
C++11 and POD types are trivially copyable in C++11 it's not required to
test for a POD type.
Since copying a large object will be expensive its size has been
restricted. 64 bytes is a common size of a cache line and if the object
is aligned the copy will be cheap. No performance impact testing has
been done.
Differential Revision: https://reviews.llvm.org/D72212
The file was modifiedclang/test/SemaCXX/warn-range-loop-analysis.cpp
The file was modifiedclang/lib/Sema/SemaStmt.cpp
The file was addedclang/test/SemaCXX/warn-range-loop-analysis-trivially-copyable.cpp
Commit 24763734e7f45e3b60118b28987685d42e7a761f by llvm-dev
[X86] Fix outdated comment
The generic saturated math opcodes are no longer widened inside
X86TargetLowering
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit a8ed86b5c705cf1d2f3ca55b0640cf0f2fe01abc by llvm-dev
moveOperands - assert Src/Dst MachineOperands are non-null.
Fixes static-analyzer warnings.
The file was modifiedllvm/lib/CodeGen/MachineInstr.cpp
Commit 7c7ca515837305f5d14033aee1191c254b86063c by benny.kra
Remove copy ctors identical to the default one. NFC.
Those do nothing but make the type no longer trivial to the compiler.
The file was modifiedmlir/include/mlir/IR/AffineExpr.h
The file was modifiedmlir/include/mlir/IR/AffineMap.h
The file was modifiedmlir/include/mlir/IR/IntegerSet.h
Commit 2740b2d5d5f0f56c87024555bdcae4f91e595ddb by llvm-dev
Fix uninitialized value clang static analyzer warning. NFC.
The file was modifiedllvm/lib/Transforms/Utils/CodeExtractor.cpp
Commit ded237b58d56299f90ef44853ef79b039248b85e by llvm-dev
Fix "pointer is null" static analyzer warning. NFCI.
Use castAs<> instead of getAs<> since the pointer is dereferenced
immediately below and castAs will perform the null assertion for us.
The file was modifiedclang/lib/Sema/SemaDecl.cpp
Commit 16c53ffcb9d040f0396bf1ab42ca366f7e1f1e4d by llvm-dev
Fix "pointer is null" static analyzer warnings. NFCI.
Use castAs<> instead of getAs<> since the pointer is dereferenced
immediately below and castAs will perform the null assertion for us.
The file was modifiedclang/lib/CodeGen/CGExprCXX.cpp
The file was modifiedclang/lib/CodeGen/CGExpr.cpp
The file was modifiedclang/lib/CodeGen/CGExprScalar.cpp
Commit d87a76c9dae38b2a1ef63584aee82e74490dc83b by llvm-dev
Fix "pointer is null" static analyzer warning. NFCI.
Use castAs<> instead of getAs<> since the pointer is dereferenced
immediately within mangleCallingConvention and castAs will perform the
null assertion for us.
The file was modifiedclang/lib/AST/MicrosoftMangle.cpp
Commit 93431f96a7b14ff03036bae77cc0197fdc98ad52 by llvm-dev
Fix "pointer is null" static analyzer warning. NFCI.
Use cast<> instead of dyn_cast<> since we know that the pointer should
be valid (and is dereferenced immediately).
The file was modifiedclang/lib/CodeGen/CGStmtOpenMP.cpp
Commit bf03944d5d9a7e7c8105c69dfa0d7e0d345644df by llvm-dev
Fix "pointer is null" static analyzer warnings. NFCI.
Use castAs<> instead of getAs<> since the pointers are dereferenced
immediately and castAs will perform the null assertion for us.
The file was modifiedclang/lib/Sema/SemaCodeComplete.cpp
Commit fce887beb79780d0e0b19e8ab6176978a3dce9b8 by llvm-dev
GlobalModuleIndex - Fix use-after-move clang static analyzer warning.
Shadow variable names meant we were referencing the Buffer input
argument, not the GlobalModuleIndex member that its std::move()'d it.
The file was modifiedclang/lib/Serialization/GlobalModuleIndex.cpp
Commit 6cb3957730e9085bb7c37d871c790f910efdd6a7 by listmail
[X86AsmBackend] Be consistent about placing definitions out of line
[NFC]
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
Commit 563d3e344452c8923db09b043b8db471fc413b1e by listmail
[X86AsmBackend] Move static function before sole use [NFC]
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
Commit 1d641daf260308815d014d1bf1b424a1ed1e7277 by listmail
[X86] Adjust nop emission by compiler to consider target decode
limitations
The primary motivation of this change is to bring the code more closely
in sync behavior wise with the assembler's version of nop emission.  I'd
like to eventually factor them into one, but that's hard to do when one
has features the other doesn't.
The longest encodeable nop on x86 is 15 bytes, but many processors - for
instance all intel chips - can't decode the 15 byte form efficiently.
On those processors, it's better to use either a 10 byte or 11 byte
sequence depending.
The file was modifiedllvm/test/CodeGen/X86/align-branch-boundary-suppressions.ll
The file was modifiedllvm/lib/Target/X86/X86MCInstLower.cpp
The file was modifiedllvm/test/MC/X86/stackmap-nops.ll
The file was modifiedllvm/test/CodeGen/X86/stackmap-nops.ll
Commit 2bdf33cc4c733342fc83081bc7410ac5e9a24f55 by riverriddle
[mlir] NFC: Remove Value::operator* and Value::operator-> now that Value
is properly value-typed.
Summary: These were temporary methods used to simplify the transition.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D72548
The file was modifiedmlir/lib/Analysis/AffineStructures.cpp
The file was modifiedmlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp
The file was modifiedmlir/lib/IR/Value.cpp
The file was modifiedmlir/test/lib/Transforms/TestInlining.cpp
The file was modifiedmlir/lib/Analysis/Dominance.cpp
The file was modifiedmlir/include/mlir/IR/OpDefinition.h
The file was modifiedmlir/lib/Dialect/GPU/IR/GPUDialect.cpp
The file was modifiedmlir/lib/Dialect/LoopOps/LoopOps.cpp
The file was modifiedmlir/include/mlir/Dialect/AffineOps/AffineOps.td
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVOps.cpp
The file was modifiedmlir/test/lib/TestDialect/TestPatterns.cpp
The file was modifiedmlir/include/mlir/Dialect/AffineOps/AffineOps.h
The file was modifiedmlir/examples/toy/Ch4/mlir/ToyCombine.cpp
The file was modifiedmlir/lib/Dialect/QuantOps/Transforms/ConvertConst.cpp
The file was modifiedmlir/lib/Dialect/SPIRV/Serialization/Serializer.cpp
The file was modifiedmlir/test/lib/TestDialect/TestOps.td
The file was modifiedmlir/lib/EDSC/Builders.cpp
The file was modifiedmlir/lib/Transforms/Utils/Utils.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
The file was modifiedmlir/lib/Quantizer/Transforms/AddDefaultStatsTestPass.cpp
The file was modifiedmlir/lib/Transforms/Utils/InliningUtils.cpp
The file was modifiedmlir/lib/Dialect/Traits.cpp
The file was modifiedmlir/examples/toy/Ch3/mlir/Dialect.cpp
The file was modifiedmlir/docs/OpDefinitions.md
The file was modifiedmlir/include/mlir/EDSC/Builders.h
The file was modifiedmlir/include/mlir/IR/Value.h
The file was modifiedmlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp
The file was modifiedmlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
The file was modifiedmlir/examples/toy/Ch6/mlir/ToyCombine.cpp
The file was modifiedmlir/include/mlir/IR/Matchers.h
The file was modifiedmlir/lib/Analysis/LoopAnalysis.cpp
The file was modifiedmlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp
The file was modifiedmlir/lib/Dialect/SPIRV/Serialization/Deserializer.cpp
The file was modifiedmlir/lib/IR/Builders.cpp
The file was modifiedmlir/lib/Transforms/Utils/LoopUtils.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgTraits.h
The file was modifiedmlir/examples/toy/Ch7/mlir/ToyCombine.td
The file was modifiedmlir/include/mlir/Analysis/Dominance.h
The file was modifiedmlir/lib/IR/Function.cpp
The file was modifiedmlir/include/mlir/Dialect/VectorOps/VectorOps.td
The file was modifiedmlir/lib/Transforms/AffineLoopInvariantCodeMotion.cpp
The file was modifiedmlir/examples/toy/Ch7/mlir/ToyCombine.cpp
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/lib/Dialect/SPIRV/Transforms/DecorateSPIRVCompositeTypeLayoutPass.cpp
The file was modifiedmlir/lib/Analysis/Verifier.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp
The file was modifiedmlir/lib/Transforms/Utils/LoopFusionUtils.cpp
The file was modifiedmlir/include/mlir/Transforms/RegionUtils.h
The file was modifiedmlir/lib/Dialect/FxpMathOps/Transforms/UniformKernelUtils.h
The file was modifiedmlir/lib/Quantizer/Transforms/InferQuantizedTypesPass.cpp
The file was modifiedmlir/examples/toy/Ch2/mlir/Dialect.cpp
The file was modifiedmlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
The file was modifiedmlir/docs/DeclarativeRewrites.md
The file was modifiedmlir/lib/Transforms/Vectorize.cpp
The file was modifiedmlir/test/lib/TestDialect/TestDialect.cpp
The file was modifiedmlir/examples/toy/Ch5/mlir/ToyCombine.td
The file was modifiedmlir/lib/Analysis/Utils.cpp
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
The file was modifiedmlir/tools/mlir-tblgen/LLVMIRConversionGen.cpp
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
The file was modifiedmlir/examples/toy/Ch6/mlir/ToyCombine.td
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/LinalgTransformPatterns.td
The file was modifiedmlir/lib/Dialect/QuantOps/IR/QuantOps.cpp
The file was modifiedmlir/include/mlir/Dialect/QuantOps/QuantOps.td
The file was modifiedmlir/test/mlir-tblgen/op-result.td
The file was modifiedmlir/lib/Transforms/LoopTiling.cpp
The file was modifiedmlir/lib/Transforms/LoopUnrollAndJam.cpp
The file was modifiedmlir/include/mlir/Dialect/VectorOps/VectorTransformPatterns.td
The file was modifiedmlir/lib/Analysis/Liveness.cpp
The file was modifiedmlir/lib/Analysis/SliceAnalysis.cpp
The file was modifiedmlir/lib/Transforms/DialectConversion.cpp
The file was modifiedmlir/lib/IR/PatternMatch.cpp
The file was modifiedmlir/lib/Parser/Parser.cpp
The file was modifiedmlir/lib/IR/TypeUtilities.cpp
The file was modifiedmlir/examples/toy/Ch7/mlir/MLIRGen.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Promotion.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/LinalgTransforms.cpp
The file was modifiedmlir/examples/toy/Ch5/mlir/ToyCombine.cpp
The file was modifiedmlir/lib/IR/Operation.cpp
The file was modifiedmlir/include/mlir/Quantizer/Support/ConstraintAnalysisGraph.h
The file was modifiedmlir/include/mlir/IR/Operation.h
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/examples/toy/Ch4/mlir/Dialect.cpp
The file was modifiedmlir/examples/toy/Ch5/mlir/Dialect.cpp
The file was modifiedmlir/examples/toy/Ch7/mlir/Dialect.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/EDSC/Builders.h
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVDialect.cpp
The file was modifiedmlir/docs/QuickstartRewrites.md
The file was modifiedmlir/include/mlir/Dialect/StandardOps/Ops.td
The file was modifiedmlir/lib/Dialect/VectorOps/VectorOps.cpp
The file was modifiedmlir/include/mlir/EDSC/Intrinsics.h
The file was modifiedmlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp
The file was modifiedmlir/lib/Conversion/GPUToCUDA/ConvertLaunchFuncToCudaCalls.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
The file was modifiedmlir/lib/IR/Region.cpp
The file was modifiedmlir/lib/Analysis/AffineAnalysis.cpp
The file was modifiedmlir/lib/Analysis/CallGraph.cpp
The file was modifiedmlir/lib/Quantizer/Configurations/FxpMathConfig.cpp
The file was modifiedmlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
The file was modifiedmlir/lib/Transforms/LoopFusion.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Utils/Utils.h
The file was modifiedmlir/lib/Transforms/MemRefDataFlowOpt.cpp
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/LegalizeStandardForSPIRV.cpp
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp
The file was modifiedmlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
The file was modifiedmlir/lib/EDSC/Helpers.cpp
The file was modifiedmlir/docs/Tutorials/Toy/Ch-4.md
The file was modifiedmlir/lib/Dialect/AffineOps/AffineOps.cpp
The file was modifiedmlir/lib/Transforms/PipelineDataTransfer.cpp
The file was modifiedmlir/lib/Quantizer/Support/ConstraintAnalysisGraph.cpp
The file was modifiedmlir/lib/IR/Block.cpp
The file was modifiedmlir/lib/Dialect/FxpMathOps/Transforms/LowerUniformRealMath.cpp
The file was modifiedmlir/lib/Transforms/LoopInvariantCodeMotion.cpp
The file was modifiedmlir/lib/Transforms/Utils/RegionUtils.cpp
The file was modifiedmlir/lib/Dialect/StandardOps/Ops.cpp
The file was modifiedmlir/lib/Target/LLVMIR/ModuleTranslation.cpp
The file was modifiedmlir/test/lib/Transforms/TestVectorizationUtils.cpp
The file was modifiedmlir/test/mlir-tblgen/predicate.td
The file was modifiedmlir/lib/Dialect/Linalg/EDSC/Builders.cpp
The file was modifiedmlir/docs/Tutorials/Toy/Ch-3.md
The file was modifiedmlir/examples/toy/Ch4/mlir/ToyCombine.td
The file was modifiedmlir/lib/Analysis/VectorAnalysis.cpp
The file was modifiedmlir/tools/mlir-tblgen/RewriterGen.cpp
The file was modifiedmlir/examples/toy/Ch6/mlir/Dialect.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
The file was modifiedmlir/include/mlir/IR/OpImplementation.h
The file was modifiedmlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
The file was modifiedmlir/lib/Transforms/Utils/FoldUtils.cpp
The file was modifiedmlir/include/mlir/Dialect/StandardOps/Ops.h
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
The file was modifiedmlir/lib/Dialect/VectorOps/VectorTransforms.cpp
The file was modifiedmlir/test/lib/Transforms/TestMemRefStrideCalculation.cpp
The file was modifiedmlir/examples/toy/Ch3/mlir/ToyCombine.cpp
The file was modifiedmlir/examples/toy/Ch3/mlir/ToyCombine.td
Commit 4c48ea68e491cb42f1b5d43ffba89f6a7f0dadc4 by development
[ASTMatchers] extract public matchers from const-analysis into own patch
Summary: The analysis for const-ness of local variables required a view
generally useful matchers that are extracted into its own patch.
They are `decompositionDecl` and `forEachArgumentWithParamType`, that
works for calls through function pointers as well.
Reviewers: aaron.ballman
Reviewed By: aaron.ballman
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72505
The file was modifiedclang/docs/LibASTMatchersReference.html
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchers.h
The file was modifiedclang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
The file was modifiedclang/lib/ASTMatchers/Dynamic/Registry.cpp
Commit 23a799adf0abbe9a7be1494d5efd1ab3215ee4fb by development
Revert "[ASTMatchers] extract public matchers from const-analysis into
own patch"
This reverts commit 4c48ea68e491cb42f1b5d43ffba89f6a7f0dadc4. The
powerpc buildbots had an internal compiler error after this patch. This
requires some inspection.
The file was modifiedclang/docs/LibASTMatchersReference.html
The file was modifiedclang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
The file was modifiedclang/lib/ASTMatchers/Dynamic/Registry.cpp
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchers.h
Commit d2751f8fdf6c072045bab62f6035511e028f46ee by Lang Hames
[ExecutionEngine] Re-enable FastISel for non-iOS arm targets.
Patch by Nicolas Capens. Thanks Nicolas!
https://reviews.llvm.org/D65015
The file was modifiedllvm/lib/ExecutionEngine/TargetSelect.cpp
Commit dc422e968e73790178e500f506e8fb7cfa1e62ea by koraq
Add -Wrange-loop-analysis changes to ReleaseNotes
This reflects the recent changes done.
The file was modifiedclang/docs/ReleaseNotes.rst
Commit 9cc9120969fd9f7f6a99321c7d94133a32927a3a by craig.topper
[X86] Turn FP_ROUND/STRICT_FP_ROUND into
X86ISD::VFPROUND/STRICT_VFPROUND during PreprocessISelDAG to remove some
duplicate isel patterns.
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrAVX512.td
The file was modifiedllvm/lib/Target/X86/X86InstrSSE.td
Commit a5994c789a2982a770254ae1607b5b4cb641f73c by maskray
[X86][Disassembler] Simplify and optimize reader functions
llvm-objdump -d on clang is decreased from 8.2s to 7.8s.
The file was modifiedllvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
Commit 9fe6f36c1a909e381275f897b780a9c878fab94a by craig.topper
[LegalizeVectorOps] Only pass SDNode* instead SDValue to all of the
Expand* and Promote* methods.
All the Expand* and Promote* function assume they are being called with
result 0 anyway. Just hardcode result 0 into them.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
Commit 5a9954c02a7d6e60da26b2feec0837695846aeed by craig.topper
[LegalizeVectorOps] Remove some of the simpler Expand methods. Pass
Results vector to a couple. NFCI
Some of the simplest handlers just call TLI and if that fails, they fall
back to unrolling. For those just inline the TLI call and share the
unrolling call with the default case of Expand.
For ExpandFSUB and ExpandBITREVERSE so that its obvious they don't
return results sometimes and want to defer to LegalizeDAG.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
Commit 179abb091d8a1d67115d21b54001d10250756042 by maskray
[X86][Disassembler] Replace custom logger with LLVM_DEBUG
llvm-objdump -d on clang is decreased from 7.8s to 7.4s.
The improvement is likely due to the elimination of logger setup and
dbgprintf(), which has a large overhead.
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
The file was modifiedllvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
Commit a1f16998f371870ca4da8b3c00a093c607a36ddd by alexandre.ganea
[Support] Optionally call signal handlers when a function wrapped by the
the CrashRecoveryContext fails
This patch allows for handling a failure inside a CrashRecoveryContext
in the same way as the global exception/signal handler. A failure will
have the same side-effect, such as cleanup of temporarty file, printing
callstack, calling relevant signal handlers, and finally returning an
exception code. This is an optional feature, disabled by default. This
is a support patch for D69825.
Differential Revision: https://reviews.llvm.org/D70568
The file was modifiedllvm/lib/Support/CrashRecoveryContext.cpp
The file was modifiedllvm/include/llvm/Support/CrashRecoveryContext.h
The file was modifiedllvm/include/llvm/Support/Signals.h
The file was modifiedllvm/lib/Support/Unix/Signals.inc
The file was modifiedllvm/lib/Support/Windows/Signals.inc
The file was modifiedllvm/unittests/Support/CrashRecoveryTest.cpp
Commit 2cdb18afda841392002feafda21af31854c195b3 by Lang Hames
[ORC] Fix argv handling in runAsMain / lli.
This fixes an off-by-one error in the argc value computed by runAsMain,
and switches lli back to using the input bitcode (rather than the string
"lli") as the effective program name.
Thanks to Stefan Graenitz for spotting the bug.
The file was modifiedllvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
The file was addedllvm/test/ExecutionEngine/OrcLazy/printargv.ll
The file was modifiedllvm/tools/lli/lli.cpp
Commit 6fdd6a7b3f696972edc244488f59532d05136a27 by maskray
[Disassembler] Delete the VStream parameter of
MCDisassembler::getInstruction()
The argument is llvm::null() everywhere except llvm::errs() in
llvm-objdump in -DLLVM_ENABLE_ASSERTIONS=On builds. It is used by no
target but X86 in -DLLVM_ENABLE_ASSERTIONS=On builds.
If we ever have the needs to add verbose log to disassemblers, we can
record log with a member function, instead of passing it around as an
argument.
The file was modifiedllvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
The file was modifiedllvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
The file was modifiedllvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp
The file was modifiedllvm/tools/llvm-mc/Disassembler.cpp
The file was modifiedllvm/lib/MC/MCDisassembler/MCDisassembler.cpp
The file was modifiedllvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
The file was modifiedlldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
The file was modifiedllvm/include/llvm/MC/MCDisassembler/MCDisassembler.h
The file was modifiedllvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
The file was modifiedllvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
The file was modifiedllvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.h
The file was modifiedllvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
The file was modifiedllvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
The file was modifiedlldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
The file was modifiedllvm/lib/MC/MCDisassembler/Disassembler.cpp
The file was modifiedllvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp
The file was modifiedllvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp
The file was modifiedllvm/tools/sancov/sancov.cpp
The file was modifiedllvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.cpp
The file was modifiedllvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
The file was modifiedllvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
The file was modifiedllvm/tools/llvm-exegesis/lib/Analysis.cpp
The file was modifiedllvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp
The file was modifiedllvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
The file was modifiedllvm/tools/llvm-objdump/MachODump.cpp
The file was modifiedllvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.h
The file was modifiedllvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
The file was modifiedlldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
The file was modifiedllvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
The file was modifiedllvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
The file was modifiedllvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp
The file was modifiedllvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
Commit 1e8ce7492e91aa6db269334d12187c7ae854dccb by maskray
[X86][Disassembler] Optimize argument passing and immediate reading
The file was modifiedllvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
Commit f719c540bb09cb5bfe37bc6283ea68e31949b3f4 by maskray
[X86][Disassembler] Shrink X86GenDisassemblerTables.inc from 36M to 6.1M
In x86Disassembler{OneByte,TwoByte,...}Codes,
"/* EmptyTable */" is very common. Omitting it saves lots of space.
Also, there is no need to display a table entry in multiple lines.
It is also common that the whole OpcodeDecision is { MODRM_ONEENTRY, 0}.
Make use of zero-initialization.
The file was modifiedllvm/utils/TableGen/X86DisassemblerTables.cpp
Commit ddfcd82bdc219dd2dc04d6826c417cea3da65d12 by craig.topper
[LegalizeVectorOps] Expand vector MERGE_VALUES immediately.
Custom legalization can produce MERGE_VALUES to return multiple results.
We can expand them immediately instead of leaving them around for DAG
combine to clean up.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
Commit ed679804d5e34dcb1046c5087acaf5d1dbb9b582 by craig.topper
[TargetLowering][X86] Connect the chain from STRICT_FSETCC in
TargetLowering::expandFP_TO_UINT and X86TargetLowering::FP_TO_INTHelper.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit efb674ac2f2b0f06adc3f00df3134dadf1c875df by craig.topper
[LegalizeVectorOps] Parallelize the lo/hi part of STRICT_UINT_TO_FLOAT
legalization.
The lo and hi computation are independent. Give them the same input
chain and TokenFactor the results together.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
Commit 569ccfc384a5434c35c09adba8c44c46014297e6 by czhengsz
[SCEV] more accurate range for addrecexpr with nsw flag.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D72436
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was modifiedllvm/test/Analysis/ScalarEvolution/range_nw_flag.ll
Commit d692f0f6c8c12316d559b9a638a2cb9fbd0c263d by craig.topper
[X86] Don't call LowerSETCC from LowerSELECT for
STRICT_FSETCC/STRICT_FSETCCS nodes.
This causes the STRICT_FSETCC/STRICT_FSETCCS nodes to lowered early
while lowering SELECT, but the output chain doesn't get connected. Then
we visit the node again when it is its turn because we haven't replaced
the use of the chain result. In the case of the fp128 libcall lowering,
after D72341 this will cause the libcall to be emitted twice.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit f33fd43a7c91f1774a9512bbdb78c367cd23d233 by qiucofan
[NFC] Refactor memory ops cluster method
Current implementation of BaseMemOpsClusterMutation is a little bit
obscure. This patch directly uses a map from store chain ID to set of
memory instrs to make it simpler, so that future improvements are easier
to read, update and review.
Reviewed By: evandro
Differential Revision: https://reviews.llvm.org/D72070
The file was modifiedllvm/lib/CodeGen/MachineScheduler.cpp
Commit c5b94ea265133a4a28006929643155fc8fbeafe6 by maskray
[profile] Support merge pool size >= 10
The executable acquires an advisory record lock (`fcntl(fd, F_SETLKW,
*)`) on a profile file. Merge pool size >= 10 may be beneficial when the
concurrency is large.
Also fix a small problem about snprintf. It can cause the filename to be
truncated after %m.
Reviewed By: davidxl
Differential Revision: https://reviews.llvm.org/D71970
The file was modifiedcompiler-rt/test/profile/instrprof-basic.c
The file was modifiedcompiler-rt/lib/profile/InstrProfilingFile.c
Commit 51c1d7c4bec025f70679284060b82c05242759b2 by maskray
[X86][Disassembler] Simplify
The file was modifiedllvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
Commit 60cc095ecc34d72a9ac6947f39c6e2a0cdf5449f by maskray
[X86][Disassembler] Merge X86DisassemblerDecoder.cpp into
X86Disassembler.cpp and refactor
The file was modifiedllvm/lib/Target/X86/Disassembler/CMakeLists.txt
The file was removedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
The file was modifiedllvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
The file was modifiedllvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/X86/Disassembler/BUILD.gn
Commit b375f28b0ec1129a4b94770a9c55ba49222ea1dd by llvm-dev
[X86][AVX] lowerShuffleAsLanePermuteAndSHUFP - only set the demanded
elements of the lane mask.
Fixes an cyclic dependency issue with an upcoming patch where
getVectorShuffle canonicalizes masks with splat build vector sources.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp