SuccessChanges

Summary

  1. [lldb][NFC] Add some more tests for edge cases LLDB's builtin formatters (details)
  2. [SVE] Remove calls to VectorType::getNumElements from FuzzMutate (details)
  3. Fix incorrect "REQUIRE" (default_target->default_triple) introduced in 59f45a1cdb3 (details)
  4. [MLIR][LLVMDialect] Added bitreverse and ctpop intrinsics (details)
  5. [vscode] set default values for terminateDebuggee for the disconnect request (details)
  6. [ELF] Resolve relocations in .debug_* referencing (discarded symbols or ICF folded section symbols) to tombstone values (details)
  7. Change CMake so that we only look for Z3 when LLVM_ENABLE_Z3_SOLVER is enabled (details)
  8. [AMDGPU/MemOpsCluster] Implement new heuristic for computing max mem ops cluster size (details)
  9. [mlir] Avoid pontentially ambiguous class name (details)
  10. [Host] Check for TARGET_OS_EMBEDDED instead of listing architectures. (details)
  11. [ObjectFileMachO] Check for TARGET_EMBEDDED instead of listing architectures. (details)
  12. Generalize TestFormattersBoolRefPtr to work on Apple Silicon. (details)
  13. Redo of Add terminateCommands to lldb-vscode protocol (details)
  14. [LLD][PowerPC] Add support for R_PPC64_PCREL34 (details)
  15. [DSE,MSSA] Treat `store 0` after calloc as noop stores. (details)
  16. [libc][Obvious] Fix few typos in tests. (details)
  17. [IR] Remove unnecessary uint64_t casts (NFC) (details)
  18. [SVE] Remove calls to VectorType::getNumElements from Bitcode (details)
  19. [IR] Remove MSVC warning workaround (NFC) (details)
  20. fix test failure for clang/test/CodeGen/builtin-expect-with-probability.cpp (details)
  21. Add missing string conversions to fix a compile error in Local.h (details)
  22. Preserve GlobalsAA analysis result in InjectTLIMappings (details)
  23. test/msan/sigwait: Don't silently ignore assertion failures (details)
  24. [lldb/Lua] Fix typo: s/stdout/stderr/ (details)
  25. [ASan][MSan] Remove EmptyAsm and set the CallInst to nomerge to avoid from merging. (details)
  26. [ARM] Cortex-M4 integer instructions scheduler info test. NFC (details)
  27. [SVE] Remove calls to VectorType::getNumElements from AsmParser (details)
  28. [mlir] [VectorOps] Improve vector.create_mask lowering (details)
  29. When performing a substitution into a dependent alias template, mark the (details)
  30. [ARM] Mark more integer instructions as not having side effects. (details)
  31. [flang] add RTBuilder.h (details)
  32. [RISCV][NFC] Add tests for folds of ADDIs into load/stores (details)
  33. [lldb] Fix the modules build (details)
  34. [clang][driver] allow macOS 11 OS version in the driver (details)
  35. Remove clang::Codegen::EHPadEndScope as unused (details)
  36. [mlir] [integration-test] Let target check-mlir imply target check-mlir-integration too (details)
  37. [WebAssembly] Fix for use of uninitialized member in WasmObjectWriter.cpp (details)
  38. Move late-parsed class member attribute handling adjacent to all the (details)
  39. [AMDGPU] Update AMD GPU processor information (details)
  40. [ELF] Add -z start-stop-visibility= to set __start_/__stop_ symbol visibility (details)
  41. [lld][ELF][AArch64] Handle R_AARCH64_PLT32 relocation (details)
  42. [IR] Prefer scalar type for struct indexes in GEP constant expressions. (details)
  43. [AArch64][SVE] Add legalization support for i32/i64 vector srem/urem (details)
  44. [NFC] Remove outdated comment in llvm-symbolizer test case. (details)
  45. DR458: Search template parameter scopes in the right order. (details)
  46. [clang codegen] Fix alignment of "Address" for incomplete array pointer. (details)
  47. [MLIR] [NFC] Add new line and empty line before printing modified loop (details)
  48. [WebAssebmly] Fully disable 'protected' visibility (details)
  49. AMDGPU/GlobalISel: Fix fixed ABI special VGPR function arguments (details)
  50. [SimplifyCFG] Drop debug loc in SpeculativelyExecuteBB (details)
  51. Remove GlobalValue::getAlignment(). (details)
  52. [AArch64][GlobalISel] Improve codegen for some constant vectors by using constant pool loads. (details)
  53. [PowerPC] Add support for vector bool __int128 for Power10 (details)
Commit d13c3e2f88c621d43b583e3040b127924bcebb3e by Raphael Isemann
[lldb][NFC] Add some more tests for edge cases LLDB's builtin formatters

OSType with less than 8 bytes has special code that isn't tested yet.
The same for C-strings that don't have `const char *` type. Also we're now testing
escaping the ASCII escape sequence (\033).
The file was modifiedlldb/test/API/functionalities/data-formatter/builtin-formats/TestBuiltinFormats.py
Commit 4d1fd33561cf758be00bdbffab1b6a1a0e428fc0 by ctetreau
[SVE] Remove calls to VectorType::getNumElements from FuzzMutate

Reviewers: efriedma, bkramer, kmclaughlin, sdesmalen

Reviewed By: sdesmalen

Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82212
The file was modifiedllvm/lib/FuzzMutate/Operations.cpp
Commit 8b64adb0a2853f42c09bd98759eec86f51b546ba by joker.eph
Fix incorrect "REQUIRE" (default_target->default_triple) introduced in 59f45a1cdb3

Adding `default_target` fixed the build by excluding these tests... but
this excluded these tests from ever running!
The correct feature check is `default_triple`
The file was modifiedllvm/test/Examples/Kaleidoscope/Chapter4.test
The file was modifiedllvm/test/Examples/Kaleidoscope/Chapter5.test
The file was modifiedllvm/test/Examples/Kaleidoscope/Chapter6.test
The file was modifiedllvm/test/Examples/Kaleidoscope/Chapter7.test
Commit a2edbd8170bd55ea64466a0719e4adda4b08a195 by antiagainst
[MLIR][LLVMDialect] Added bitreverse and ctpop intrinsics

Introduced `llvm.intr.bitreverse` and `llvm.intr.ctpop` LLVM bit
intrinsics to LLVM dialect. These intrinsics help with SPIR-V to
LLVM conversion, allowing a direct mapping from `spv.BitReverse`
and `spv.BitCount` respectively. Tests are added to `roundtrip.mlir`
and `llvm-intrinsics.mlir`.

Differential Revision: https://reviews.llvm.org/D82285
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
The file was modifiedmlir/test/Dialect/LLVMIR/roundtrip.mlir
The file was modifiedmlir/test/Target/llvmir-intrinsics.mlir
Commit 0a9e7d0b6befad866dfd61f05b774247e0867121 by waltermelon
[vscode] set default values for terminateDebuggee for the disconnect request

Summary:
Recently I've noticed that VSCode sometimes doesn't send the terminateDebuggee flag within the disconnectRequest,
even though lldb-vscode sets the terminateDebuggee capability correctly.
This has been causing that inferiors don't die after the debug session ends, and many users have reported issues because of this.

An easy way to mitigate this is to set better default values for the terminateDebuggee field in the disconnect request.
I'm assuming that for a launch request, the default will be true, and for attach it'll be false.

Reviewers: clayborg, labath, aadsm

Subscribers: lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D81200
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-vscode/lldbvscode_testcase.py
The file was addedlldb/test/API/tools/lldb-vscode/disconnect/TestVSCode_disconnect.py
The file was addedlldb/test/API/tools/lldb-vscode/disconnect/main.cpp
The file was modifiedlldb/tools/lldb-vscode/VSCode.h
The file was modifiedlldb/tools/lldb-vscode/lldb-vscode.cpp
The file was addedlldb/test/API/tools/lldb-vscode/disconnect/Makefile
The file was modifiedlldb/tools/lldb-vscode/VSCode.cpp
Commit e618ccbf431f6730edb6d1467a127c3a52fd57f7 by i
[ELF] Resolve relocations in .debug_* referencing (discarded symbols or ICF folded section symbols) to tombstone values

See D59553, https://lists.llvm.org/pipermail/llvm-dev/2020-May/141885.html and
https://sourceware.org/pipermail/binutils/2020-May/111357.html for
extensive discussions on a tombstone value.
See http://www.dwarfstd.org/ShowIssue.php?issue=200609.1
(Reserve an address value for "not present") for a DWARF enhancement proposal.

We resolve such relocations to a tombstone value to indicate that the address is invalid.
This solves several problems (the normal behavior is to resolve the relocation to the addend):

* For an empty function in a collected section, a pair of (0,0) can
  terminate .debug_loc and .debug_ranges (as of binutils 2.34, GNU ld
  resolves such a relocation to 1 to avoid the .debug_ranges issue)
* If DW_AT_high_pc is sufficiently large, the address range can collide
  with a regular code range of low address (https://bugs.llvm.org/show_bug.cgi?id=41124 )
* If a text section is folded into another by ICF, we may leave entries
  in multiple CUs claiming ownership of the same range of code, which can
  confuse consumers.
* Debug information associated with COMDAT sections can have problems
  similar to ICF, but is more complex - thus not addressed by this patch.

For pre-DWARF-v5 .debug_loc and .debug_ranges, a pair of 0 can terminate
entries (invalidating subsequent ranges).
-1 is a reserved value with special meaning (base address selection entry) which can't be used either.
Use -2 instead.

For all other .debug_*, use UINT32_MAX for 32-bit targets and UINT64_MAX
for 64-bit targets. In the code, we intentionally use
`uint64_t tombstone = UINT64_MAX` for 32-bit targets as well: this matches
SignExtend64 as used in `relocateAlloc`. (Actually UINT32_MAX does not work for R_386_32)

Note 0, we only special case `target->symbolicRel` (R_X86_64_64, R_AARCH64_ABS64, R_PPC64_ADDR64), not
short-range absolute relocations (e.g. R_X86_64_32). Only forms like DW_FORM_addr need to be special cased.
They can hold an arbitrary address (must be 64-bit on a 64-bit target). (In theory,
producers can make use of small code model to emit 32-bit relocations. This doesn't seem to be leveraged.)

Note 1, we have to ignore the addend, because we don't want to resolve
DW_AT_low_pc (which may have a non-zero addend) to -1+addend (wrap
around to a low address):

  __attribute__((section(".text.x"))) void f1() { }
  __attribute__((section(".text.x"))) void f2() { } // DW_AT_low_pc has a non-zero addend

Note 2, if the prevailing copy does not have debugging information while
a non-prevailing copy has (partial debug build), we don't do extra work
to attach debugging information to the prevailing definition.  (clang
has a lot of debug info optimizations that are on-by-default that assume
the whole program is built with debug info).

  clang -c -ffunction-sections a.cc    # prevailing copy has no debug info
  clang -c -ffunction-sections -g b.cc

Reviewed By: dblaikie, avl, jhenderson

Differential Revision: https://reviews.llvm.org/D81784
The file was addedlld/test/ELF/debug-dead-reloc-icf.s
The file was addedlld/test/ELF/debug-dead-reloc.s
The file was addedlld/test/ELF/debug-dead-reloc-32.s
The file was modifiedlld/ELF/InputSection.cpp
Commit fb34345e363ae00e6a2f7979ef524f4a4ffae582 by mikhail.ramalho
Change CMake so that we only look for Z3 when LLVM_ENABLE_Z3_SOLVER is enabled

Reviewers: mikhail.ramalho

Reviewed By: mikhail.ramalho

Subscribers: mehdi_amini, mgorny, mikhail.ramalho, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75544
The file was modifiedllvm/CMakeLists.txt
Commit cc9d69385659be32178506a38b4f2e112ed01ad4 by mahesha.comp
[AMDGPU/MemOpsCluster] Implement new heuristic for computing max mem ops cluster size

Summary:
Make use of both the - (1) clustered bytes and (2) cluster length, to decide on
the max number of mem ops that can be clustered. On an average, when loads
are dword or smaller, consider `5` as max threshold, otherwise `4`. This
heuristic is purely based on different experimentation conducted, and there is
no analytical logic here.

Reviewers: foad, rampitec, arsenm, vpykhtin

Reviewed By: rampitec

Subscribers: llvm-commits, kerbowa, hiraditya, t-tye, Anastasia, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, thakis

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82393
The file was modifiedllvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/kernel-args.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/udivrem.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/memory_clause.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/global-saddr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/shift-i128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdhsa-trap-num-sgprs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/salu-to-valu.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/trunc-store-i64.ll
Commit 1db1a08ddae6174e0e0bf6f8a8404cef9091b68b by jean-michel.gorius
[mlir] Avoid pontentially ambiguous class name

Summary: The Pass class exists in both the mlir and the llvm namespaces. Use the fully qualified class name to avoid any ambiguities.

Reviewers: rriddle

Reviewed By: rriddle

Subscribers: mehdi_amini, jpienaar, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, stephenneuendorffer, Joonsoo, grosul1, jurahul, msifontes

Tags: #mlir

Differential Revision: https://reviews.llvm.org/D82371
The file was modifiedmlir/tools/mlir-tblgen/PassGen.cpp
Commit 3c79212319d878b07ef259d735b52b379f774e25 by ditaliano
[Host] Check for TARGET_OS_EMBEDDED instead of listing architectures.

With the advent of Apple Silicon, checking for the architectures
specifically is not correct anymore. This code is only supposed to
run on embedded devices (iPhones et similia), so mark it accordingly.
The file was modifiedlldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm
Commit 63d597093cccbb8d4962cf490e2d754a73a77e64 by ditaliano
[ObjectFileMachO] Check for TARGET_EMBEDDED instead of listing architectures.

Now that Apple Silicon is a thing, we need to generalize the check.
The file was modifiedlldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
Commit 33ece57241d8ad46cb91eca483f05515849a85e5 by ditaliano
Generalize TestFormattersBoolRefPtr to work on Apple Silicon.
The file was modifiedlldb/test/API/functionalities/data-formatter/boolreference/TestFormattersBoolRefPtr.py
Commit 74ab1da0285fb1f37fdb4648e2c677e97a2a5231 by waltermelon
Redo of Add terminateCommands to lldb-vscode protocol

Summary:
This redoes https://reviews.llvm.org/D79726 and fixes two things.
- The logic that determines whether to automatically disconnect during the tear down is not very dumb compared to the original implementation. Each test will determine whether to do that or not.
- The terminate commands and terminate event were being sent after the disconnect response was sent to the IDE. That was not good, as VSCode stops the debug session as soon as it receives a disconnect response. Now, the terminate event and terminateEvents are being executed before the disconnect response is sent. This ensures that any connection between the IDE and lldb-vscode is alive while the terminate commands are executed. Besides, it also allows displaying the output of the terminate commands on the debug console, as it's still alive.

Reviewers: clayborg, aadsm, kusmour, labath

Subscribers: lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D81978
The file was modifiedlldb/tools/lldb-vscode/VSCode.cpp
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-vscode/lldbvscode_testcase.py
The file was modifiedlldb/tools/lldb-vscode/VSCode.h
The file was modifiedlldb/tools/lldb-vscode/lldb-vscode.cpp
The file was modifiedlldb/test/API/tools/lldb-vscode/launch/TestVSCode_launch.py
The file was modifiedlldb/test/API/tools/lldb-vscode/attach/TestVSCode_attach.py
The file was modifiedlldb/tools/lldb-vscode/README.md
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-vscode/vscode.py
Commit 3a55a2a97fd419c1b6c5299b3523846a9fa9bc52 by kamau.bridgeman
[LLD][PowerPC] Add support for R_PPC64_PCREL34

Add support for the 34bit relocation R_PPC64_PCREL34 for PC Relative in LLD.
The file was addedlld/test/ELF/ppc64-reloc-pcrel34-overflow.s
The file was modifiedlld/ELF/Arch/PPC64.cpp
The file was addedlld/test/ELF/ppc64-reloc-pcrel34.s
Commit ff4de8683ad1802dbf20d0286861bd98462e92e2 by flo
[DSE,MSSA] Treat `store 0` after calloc as noop stores.

This patch extends storeIsNoop to also detect stores of 0 to an calloced
object. This basically ports the logic from legacy DSE to the MemorySSA
backed version.

It triggers in a few cases on MultiSource, SPEC2000, SPEC2006 with -O3
LTO:

Same hash: 218 (filtered out)
Remaining: 19
Metric: dse.NumNoopStores

Program                                        base   patch2 diff
test-suite...CFP2000/177.mesa/177.mesa.test     1.00  15.00 1400.0%
test-suite...6/482.sphinx3/482.sphinx3.test     1.00  14.00 1300.0%
test-suite...lications/ClamAV/clamscan.test     2.00  28.00 1300.0%
test-suite...CFP2006/433.milc/433.milc.test     1.00   8.00 700.0%
test-suite...pplications/oggenc/oggenc.test     2.00   9.00 350.0%
test-suite.../CINT2000/176.gcc/176.gcc.test     6.00   6.00  0.0%
test-suite.../CINT2006/403.gcc/403.gcc.test    NaN   137.00  nan%
test-suite...libquantum/462.libquantum.test    NaN     3.00  nan%
test-suite...6/464.h264ref/464.h264ref.test    NaN     7.00  nan%
test-suite...decode/alacconvert-decode.test    NaN     2.00  nan%
test-suite...encode/alacconvert-encode.test    NaN     2.00  nan%
test-suite...ications/JM/ldecod/ldecod.test    NaN     9.00  nan%
test-suite...ications/JM/lencod/lencod.test    NaN    39.00  nan%
test-suite.../Applications/lemon/lemon.test    NaN     2.00  nan%
test-suite...pplications/treecc/treecc.test    NaN     4.00  nan%
test-suite...hmarks/McCat/08-main/main.test    NaN     4.00  nan%
test-suite...nsumer-lame/consumer-lame.test    NaN     3.00  nan%
test-suite.../Prolangs-C/bison/mybison.test    NaN     1.00  nan%
test-suite...arks/mafft/pairlocalalign.test    NaN    30.00  nan%

Reviewers: efriedma, zoecarver, asbirlea

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D82204
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/simple.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/simple-todo.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/calloc-store.ll
The file was modifiedllvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
Commit dc72be4e0130675833c56d4d72e22a56872876ea by sivachandra
[libc][Obvious] Fix few typos in tests.
The file was modifiedlibc/test/src/math/ceilf_test.cpp
The file was modifiedlibc/test/src/math/truncf_test.cpp
The file was modifiedlibc/test/src/math/frexpf_test.cpp
The file was modifiedlibc/test/src/math/roundf_test.cpp
The file was modifiedlibc/test/src/math/modff_test.cpp
The file was modifiedlibc/test/src/math/floorf_test.cpp
Commit 52e86797ba687d89a2e9a85c135b7145a5f14739 by nikita.ppv
[IR] Remove unnecessary uint64_t casts (NFC)

As pointed out by foad, it's not necessary to work on uint64_t
here. The values used here fit uint8_t.
The file was modifiedllvm/lib/IR/AttributeImpl.h
Commit e6d8636935e13f57b52c7dcf81f5c4576e2446f5 by ctetreau
[SVE] Remove calls to VectorType::getNumElements from Bitcode

Reviewers: efriedma, evgeny777, tejohnson, david-arm, kmclaughlin

Reviewed By: david-arm

Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82209
The file was modifiedllvm/lib/Bitcode/Writer/BitcodeWriter.cpp
Commit 6904c7129b26373eb33489b43538ab580829655e by nikita.ppv
[IR] Remove MSVC warning workaround (NFC)

While LLVM does fold this to x+1, GCC does not. As this is hot
code, let's try to avoid that.

According to
https://developercommunity.visualstudio.com/content/problem/211134/unsigned-integer-overflows-in-constexpr-functionsa.html
this spurious warning in MSVC has been fixed in Visual Studio 2019
Version 16.4. Let's see if there are any build bots running old
MSVC versions with warnings treated as errors...
The file was modifiedllvm/lib/IR/Attributes.cpp
Commit 47fb21d2ea903fc4cce38f8da8160cf0eacc16d0 by erich.keane
fix test failure for clang/test/CodeGen/builtin-expect-with-probability.cpp

Fix test case added by D79830
Rewrite the test case, which did similar thing as builtin-expect.c
does(test generated llvm intrinsic instead of test branch weights).
Currently pass by "-disable-llvm-passes" option.

Differential Revision: https://reviews.llvm.org/D82403
The file was modifiedclang/test/CodeGen/builtin-expect-with-probability.cpp
Commit e07a8b5efd60f25de84ac89783a5e326dc414cef by Adrian Prantl
Add missing string conversions to fix a compile error in Local.h
The file was modifiedllvm/include/llvm/Analysis/Utils/Local.h
Commit f64dc4e6866c2ab88148abb7d8a27e3828f978e4 by flo
Preserve GlobalsAA analysis result in InjectTLIMappings

InjectTLIMappings fails to preserve the analysis result of GlobalsAA. Not preserving the analysis might affect benchmark performance. This change fixes this issue.

Patch by: Ryan Santhiraraja <rsanthir@quicinc.com>

Reviewers: fpetrogalli, joerg, fhahn

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D82343
The file was modifiedllvm/lib/Transforms/Utils/InjectTLIMappings.cpp
Commit 16784c0558c43ccbc0242c7429bc065c68163cbd by eugenis
test/msan/sigwait: Don't silently ignore assertion failures

Summary: As the parent process would return 0 independent of whether the child succeeded, assertions in the child would be ignored.

Reviewers: eugenis

Reviewed By: eugenis

Subscribers: #sanitizers

Tags: #sanitizers

Differential Revision: https://reviews.llvm.org/D82400
The file was modifiedcompiler-rt/test/msan/sigwait.cpp
Commit be494adb30ec76e1b6738b8bfc22040bfc31ce98 by Jonas Devlieghere
[lldb/Lua] Fix typo: s/stdout/stderr/

This wasn't caught by the existing test, but will be covered by the
extended test that's part of D82412.
The file was modifiedlldb/source/Plugins/ScriptInterpreter/Lua/Lua.cpp
Commit 6a822e20ce700f2f98e80c6ce8dda026099c39b7 by zequanwu
[ASan][MSan] Remove EmptyAsm and set the CallInst to nomerge to avoid from merging.

Summary: `nomerge` attribute was added at D78659. So, we can remove the EmptyAsm workaround in ASan the MSan and use this attribute.

Reviewers: vitalybuka

Reviewed By: vitalybuka

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82322
The file was modifiedllvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
The file was modifiedllvm/test/Instrumentation/SanitizerCoverage/coverage-dbg.ll
The file was modifiedllvm/test/Instrumentation/SanitizerCoverage/coverage2-dbg.ll
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
The file was modifiedllvm/test/Instrumentation/SanitizerCoverage/trace-pc-guard-comdat.ll
The file was modifiedllvm/include/llvm/IR/InstrTypes.h
The file was modifiedllvm/test/Instrumentation/SanitizerCoverage/coverage.ll
The file was modifiedllvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
The file was modifiedllvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
The file was modifiedllvm/test/Instrumentation/SanitizerCoverage/trace-pc-guard-nocomdat.ll
Commit 887c0b5665629866c8798e47a799e6922b2f6735 by david.green
[ARM] Cortex-M4 integer instructions scheduler info test. NFC

Most useful at the moment for showing where unpredicatable instructions are.
The file was addedllvm/test/tools/llvm-mca/ARM/m4-int.s
Commit 433c9adf7b2bea8577a15b5e8c38f2844b965be8 by ctetreau
[SVE] Remove calls to VectorType::getNumElements from AsmParser

Reviewers: efriedma, RKSimon, c-rhodes, fpetrogalli

Reviewed By: fpetrogalli

Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82208
The file was modifiedllvm/lib/AsmParser/LLParser.cpp
Commit 55d09dfc7b147dbb74ae62173f4d5b078b19e328 by ajcbik
[mlir] [VectorOps] Improve vector.create_mask lowering

Use vector compares for the 1-D case. This approach scales much better
than generating insertion operations, and exposes SIMD directly to backend.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D82402
The file was modifiedmlir/test/Dialect/Vector/vector-contract-transforms.mlir
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
Commit a6308c0ad954a08645d9abf0a5e77dc488b8ca28 by richard
When performing a substitution into a dependent alias template, mark the
outer levels as retained rather than omitting their arguments.

This better reflects what's going on (we're performing a substitution
while still inside a template), and in theory is more correct, but I've
not found a testcase where it matters in practice (largely because we
don't allow alias templates to be declared inside a function).

Fixed AST dumping of SubstNonTypeTemplateParm[Pack]Expr to demonstrate
that we're properly substituting through dependent alias templates. (We
can't deduce properly through these yet, but we can at least produce the
right input to template argument deduction.)

No functionality change intended.
The file was modifiedclang/test/SemaTemplate/deduction-guide.cpp
The file was modifiedclang/lib/Sema/SemaTemplate.cpp
The file was modifiedclang/test/SemaTemplate/alias-templates.cpp
The file was modifiedclang/test/AST/ast-dump-openmp-begin-declare-variant_template_1.cpp
The file was modifiedclang/unittests/AST/ASTTraverserTest.cpp
The file was modifiedclang/include/clang/AST/ASTNodeTraverser.h
Commit d604cc6e9a41aa6cf1759b8c58c8d02e5c87dda2 by david.green
[ARM] Mark more integer instructions as not having side effects.

LDRD and STRD along with UBFX and SBFX are selected from DAGToDAG
transforms, so do not have tblgen patterns. They don't get marked as
having side effects so cannot be scheduled as efficiently as you would
like.

This specifically marks then as not having side effects.

Differential Revision: https://reviews.llvm.org/D82358
The file was modifiedllvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
The file was modifiedllvm/test/tools/llvm-mca/ARM/m4-int.s
The file was modifiedllvm/lib/Target/ARM/ARMInstrThumb2.td
Commit 84f380580531d4f44fb3e4a2d17b5033e1e9bb0b by eschweitz
[flang] add RTBuilder.h

This is a set of type building models that is specific to the lowering
process. It provides the mechanism of mapping C(++) header file interfaces
to the MLIR+FIR type system.

It also provides some macros to build a constexpr evaluated table to
runtime functions. This code is used to build the interface tables to
various runtime support libraries.

Differential revision: https://reviews.llvm.org/D82387
The file was addedflang/lib/Lower/RTBuilder.h
Commit 0947a8ca9824e15780075dc3525e30bada4bccdd by luismarques
[RISCV][NFC] Add tests for folds of ADDIs into load/stores

This patch adds tests for folds of ADDIs into load/stores, focusing on
load/stores with nonzero offsets. When the offset is nonzero we currently
don't do the fold. A follow-up patch will improve on that.

Differential Revision: https://reviews.llvm.org/D79689
The file was addedllvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
Commit ba05bf5fc854176c1235a3c1cce4787268e1ba6b by Jonas Devlieghere
[lldb] Fix the modules build

Fixes error: invalid operands to binary expression ('llvm::StringRef'
and 'const char [6]')
The file was modifiedllvm/include/llvm/Analysis/Utils/Local.h
Commit f724ce0d73eb3f85364e346a036588825bc47567 by Alex Lorenz
[clang][driver] allow macOS 11 OS version in the driver
The file was modifiedclang/lib/Driver/ToolChains/Darwin.cpp
The file was modifiedclang/test/Driver/darwin-version.c
Commit 4935419d779bdc6cc2f1c2f9e78821ad550d3b56 by dblaikie
Remove clang::Codegen::EHPadEndScope as unused

Unused since r255423 / D15140 /  4e52d6f811a2269e946c19e77245148bd9221f99

Found indirectly by assessing -debug-info-kind=constructors and
observing the EHPadEndScope type was never emitted because the
constructor is never called. (all credit to Amy Huang for identifying
this issue)
The file was modifiedclang/lib/CodeGen/CGCleanup.h
The file was modifiedclang/lib/CodeGen/CGException.cpp
Commit ba690195d1c68b135680194b378e357f6d6e3f4a by ajcbik
[mlir] [integration-test] Let target check-mlir imply target check-mlir-integration too

Note that this does not mean that check-mlir will run check-mlir-integration
tests for all configurations. You still need to do a set up with the flag
MLIR_INCLUDE_INTEGRATION_TESTS set to ON in order to activate the integration test.

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D82413
The file was modifiedmlir/integration_test/CMakeLists.txt
Commit e49584a34a1242e4f9f0b6e65f19e3cbec43d906 by sbc
[WebAssembly] Fix for use of uninitialized member in WasmObjectWriter.cpp

Currently, section indices may be passed uninitialized by value if
writing the section fails. Removes section indices form class
initialization and returns them from the write{Code,Data}Section
function calls instead.

Patch by Gui Andrade!

Differential Revision: https://reviews.llvm.org/D81702
The file was modifiedllvm/lib/MC/WasmObjectWriter.cpp
Commit 4f5f6c1b83cb60354b7b4dea8fc7da561b6758fd by richard
Move late-parsed class member attribute handling adjacent to all the
other late-parsed class component handling.

No functionality change intended.
The file was modifiedclang/lib/Parse/ParseDecl.cpp
The file was modifiedclang/lib/Parse/ParseCXXInlineMethods.cpp
Commit ea6df2fb8fa57d5f75de284b490ceb1123b78178 by Tony.Tye
[AMDGPU] Update AMD GPU processor information

Summary:
- Add product names for some processors.
- Correct XNACK support for a processor.

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82348
The file was modifiedllvm/docs/AMDGPUUsage.rst
Commit fffd05d52526e0718acf23b4dd34f200e2c79f67 by phosek
[ELF] Add -z start-stop-visibility= to set __start_/__stop_ symbol visibility

This matches the equivalent flag implemented in GNU linkers, see
https://sourceware.org/pipermail/binutils/2020-June/111685.html for
the associated discussion.

Differential Revision: https://reviews.llvm.org/D55682
The file was addedlld/test/ELF/startstop-visibility.s
The file was modifiedlld/ELF/Config.h
The file was modifiedlld/ELF/Writer.cpp
The file was modifiedlld/ELF/Driver.cpp
Commit 723b5a1785426245e3c56b4666ef526b32be84a9 by leonardchan
[lld][ELF][AArch64] Handle R_AARCH64_PLT32 relocation

This is the followup to D77647 which implements handling for the new
R_AARCH64_PLT32 relocation type in lld. This relocation would benefit the
PIC-friendly vtables feature described in D72959.

Differential Revision: https://reviews.llvm.org/D81184
The file was addedlld/test/ELF/aarch64-range-thunk-extension-plt32.s
The file was modifiedlld/test/ELF/aarch64-undefined-weak.s
The file was modifiedlld/ELF/Thunks.cpp
The file was modifiedlld/ELF/Arch/AArch64.cpp
The file was modifiedlld/ELF/InputSection.cpp
The file was addedlld/test/ELF/aarch64-reloc-plt32.s
Commit 90ad786947cc861756c95238f96c267b2a3c4849 by efriedma
[IR] Prefer scalar type for struct indexes in GEP constant expressions.

This has two advantages: one, it's simpler, and two, it doesn't require
heroic pattern matching with scalable vectors.

Also includes a small fix to DataLayout to allow the scalable vector
testcase to work correctly.

Differential Revision: https://reviews.llvm.org/D82061
The file was modifiedllvm/lib/IR/Constants.cpp
The file was modifiedllvm/test/Transforms/InstSimplify/gep.ll
The file was modifiedllvm/lib/IR/DataLayout.cpp
The file was modifiedllvm/test/Analysis/ConstantFolding/vectorgep-crash.ll
Commit e9d4e34ab8a4223de41fbf1881fd6a531880dda9 by efriedma
[AArch64][SVE] Add legalization support for i32/i64 vector srem/urem

Implement them on top of sdiv/udiv, similar to what we do for integer
types.

Potential future work: implementing i8/i16 srem/urem, optimizations for
constant divisors, optimizing the mul+sub to mls.

Differential Revision: https://reviews.llvm.org/D81511
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit c2bb88cc025cd16efee33a46cc0547e51f56bfd0 by akhuang
[NFC] Remove outdated comment in llvm-symbolizer test case.
The file was modifiedllvm/test/tools/llvm-symbolizer/pdb/pdb-native.test
Commit d1446017f3fdc2f6a9efba222008d20afa1e26cc by richard
DR458: Search template parameter scopes in the right order.

C++ unqualified name lookup searches template parameter scopes
immediately after finishing searching the entity the parameters belong
to. (Eg, for a class template, you search the template parameter scope
after looking in that class template and its base classes and before
looking in the scope containing the class template.) This is complicated
by the fact that scope lookup within a template parameter scope looks in
a different sequence of places prior to reaching the end of the
declarator-id in the template declaration.

We used to approximate the proper lookup rule with a hack in the scope /
decl context walk inside name lookup. Now we instead compute the lookup
parent for each template parameter scope.

In order to get this right, we now make sure to enter a distinct Scope
for each template parameter scope, and make sure to re-enter the
enclosing class scopes properly when handling delay-parsed regions
within a class.
The file was modifiedclang/lib/Sema/SemaLookup.cpp
The file was modifiedclang/test/SemaCXX/lambda-expressions.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Sema/SemaDeclCXX.cpp
The file was modifiedclang/test/CXX/temp/temp.res/temp.local/p8.cpp
The file was modifiedclang/test/CXX/drs/dr4xx.cpp
The file was modifiedclang/www/cxx_dr_status.html
The file was modifiedclang/lib/Parse/ParseOpenMP.cpp
The file was modifiedclang/lib/Parse/ParseDeclCXX.cpp
The file was modifiedclang/include/clang/Sema/Scope.h
The file was modifiedclang/lib/AST/DeclBase.cpp
The file was modifiedclang/lib/Parse/ParseCXXInlineMethods.cpp
The file was modifiedclang/lib/Sema/SemaTemplate.cpp
The file was modifiedclang/lib/Parse/ParseTemplate.cpp
The file was modifiedclang/lib/Parse/ParseExprCXX.cpp
The file was modifiedclang/include/clang/Parse/Parser.h
The file was modifiedclang/lib/Sema/SemaDecl.cpp
Commit bf8b63ed296c1ecad03c83b798ffbfa039cbceb4 by efriedma
[clang codegen] Fix alignment of "Address" for incomplete array pointer.

The code was assuming all incomplete types don't have meaningful
alignment, but incomplete arrays do have meaningful alignment.

Fixes https://bugs.llvm.org/show_bug.cgi?id=45710

Differential Revision: https://reviews.llvm.org/D79052
The file was modifiedclang/test/CodeGenCXX/alignment.cpp
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
Commit e7f7137cd7119b93bf2a0fa2049dbc38068ee20c by jurahul
[MLIR] [NFC] Add new line and empty line before printing modified loop
             to make the debug output readable.

Differential Revision: https://reviews.llvm.org/D82417
The file was modifiedmlir/lib/Transforms/LoopInvariantCodeMotion.cpp
Commit 5804a8b1228ba890d48f4085a3a192ef83c73e00 by sbc
[WebAssebmly] Fully disable 'protected' visibility

Emscripten doesn't use protected visibility either.

Differential Revision: https://reviews.llvm.org/D82346
The file was modifiedclang/lib/Basic/Targets/WebAssembly.h
Commit a162048a47b7e1c7e83fca82f09876944307dd2f by Matthew.Arsenault
AMDGPU/GlobalISel: Fix fixed ABI special VGPR function arguments

I forgot to copy the new fixed function ABI into GlobalISel, so this
was mismatched with the DAG compiled calling function. This was
allocating part of the argument list to v31, which was supposed to be
reserved for the workitem IDs.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll
Commit f8bd6a75edac7560deb5fdcb31041b454dd9d7e0 by Vedant Kumar
[SimplifyCFG] Drop debug loc in SpeculativelyExecuteBB

Summary:
According to HowToUpdateDebugInfo.rst:

```
Preserving the debug locations of speculated instructions can make
it seem like a condition is true when it's not (or vice versa), which
leads to a confusing single-stepping experience
```

This patch follows the recommendation to drop debug locations on
speculated instructions.

Reviewers: aprantl, davide

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82420
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
The file was addedllvm/test/Transforms/SimplifyCFG/drop-debug-loc-when-speculating.ll
Commit a2caa3b61497b6be8c8b77823d0fd62b4be1f177 by efriedma
Remove GlobalValue::getAlignment().

This function is deceptive at best: it doesn't return what you'd expect.
If you have an arbitrary GlobalValue and you want to determine the
alignment of that pointer, Value::getPointerAlignment() returns the
correct value.  If you want the actual declared alignment of a function
or variable, GlobalObject::getAlignment() returns that.

This patch switches all the users of GlobalValue::getAlignment to an
appropriate alternative.

Differential Revision: https://reviews.llvm.org/D80368
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
The file was modifiedllvm/include/llvm/IR/GlobalObject.h
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZSubtarget.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-constant.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/global-alignment.ll
The file was modifiedllvm/lib/Object/IRSymtab.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.cpp
The file was modifiedllvm/lib/IR/Core.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
The file was modifiedllvm/include/llvm/CodeGen/AsmPrinter.h
The file was modifiedllvm/lib/IR/ConstantFold.cpp
The file was modifiedllvm/lib/IR/Globals.cpp
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was modifiedllvm/lib/Bitcode/Writer/BitcodeWriter.cpp
The file was modifiedllvm/lib/LTO/LTOModule.cpp
The file was modifiedllvm/test/CodeGen/AArch64/funcptr_cast.ll
The file was modifiedllvm/lib/Target/XCore/XCoreISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was modifiedllvm/include/llvm/IR/GlobalValue.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Commit fceadbcb335da23d0a9beba8c4080a3e4222a385 by Amara Emerson
[AArch64][GlobalISel] Improve codegen for some constant vectors by using constant pool loads.

There's more smarts in AArch64ISelLowering that we don't have yet, but this
change incrementally improves some of the more common patterns. I think future
iterations will want to use some combination of PostLegalizerCombiner and the
selector to catch the other cases.

Differential Revision: https://reviews.llvm.org/D82340
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AArch64/combine-loads.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/select-const-vector.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir
Commit f4c337ab85c0b7ec206da0f2c6576730eefb36c2 by saghir
[PowerPC] Add support for vector bool __int128 for Power10

Summary:
This patch adds support for `vector bool __int128` type for Power10.

Reviewers: #powerpc, hfinkel, lei, stefanp, amyk

Reviewed By: #powerpc, lei, amyk

Subscribers: lei, amyk, wuzish, nemanjai, shchenz, cfe-commits

Tags: #llvm, #powerpc, #clang

Differential Revision: https://reviews.llvm.org/D81816
The file was modifiedclang/lib/Sema/DeclSpec.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was addedclang/test/Parser/p10-vector-bool-128.c
The file was addedclang/test/Parser/cxx-altivec-bool-128.cpp
The file was addedclang/test/Parser/altivec-bool-128.c