SuccessChanges

Summary

  1. [LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. (details)
  2. [mlir][spirv] Define spv.GLSL.Ldexp (details)
  3. [lit] Add --ignore-fail (details)
  4. [RISCV] Support fixed vector extract element. Use VL=1 for scalable vector extract element. (details)
  5. [AArch64][GlobalISel] Fix manual selection for v4s16 and v8s8 G_DUP (details)
  6. Remove a workaround for MSVC 2013, now that MSVC 2017 is the minimum. (details)
  7. [llvm-objcopy] If input=output, preserve umask bits, otherwise drop S_ISUID/S_ISGID bits (details)
  8. [lldb] Support debugging utility functions (details)
  9. [mlir][linalg] Support for using output values in TC definitions. (details)
  10. [mlir][linalg] Reuse the symbol if attribute uses are identical. (details)
  11. [mlir][docs] Small fix to local Pass Manager reproduction documentation (details)
  12. AMDGPU: Add even aligned VGPR/AGPR register classes (details)
  13. AMDGPU: Remove special case in shouldCoalesce (details)
  14. [InstCombine] add tests for fdiv+powi; NFC (details)
  15. [libcxx] [test] Quote the path to the python interpreter (details)
  16. [amdgpu] Atomic should be source of divergence. (details)
  17. [tests] precommit tests for D97219 (details)
Commit fe50be12c8b845fffd44c508ad981901d25ac5f8 by craig.topper
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported.

Rather than converting 3 signbits to bools and comparing them,
we can do bitwise logic on the whole vector and convert the
resulting sign bit to a bool at the end.

This is still a different algorithm than what we do in LegalizeDAG
through expandSADDOSSUBO. That algorithm needs to know that the
RHS of SSUBO is > 0, but that's costly when the type is split.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D97325
The file was modifiedllvm/test/CodeGen/ARM/sadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/ARM/ssub_sat.ll
The file was modifiedllvm/test/CodeGen/ARM/sadd_sat.ll
The file was modifiedllvm/test/CodeGen/AArch64/sadd_sat_vec.ll
The file was modifiedllvm/test/CodeGen/RISCV/ssub_sat.ll
The file was modifiedllvm/test/CodeGen/RISCV/ssub_sat_plus.ll
The file was modifiedllvm/test/CodeGen/ARM/ssub_sat_plus.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
The file was modifiedllvm/test/CodeGen/AArch64/ssub_sat_vec.ll
The file was modifiedllvm/test/CodeGen/RISCV/sadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/RISCV/xaluo.ll
The file was modifiedllvm/test/CodeGen/RISCV/sadd_sat.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
Commit ce2ad938ff1fd4bad6ee91809f970984b1614e35 by antiagainst
[mlir][spirv] Define spv.GLSL.Ldexp

co-authored-by: Alan Liu <alanliu.yf@gmail.com>

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D97228
The file was modifiedmlir/test/Target/SPIRV/glsl-ops.mlir
The file was modifiedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLSLOps.td
The file was modifiedmlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
The file was modifiedmlir/test/Dialect/SPIRV/IR/glsl-ops.mlir
Commit 2a5aa81739d31959600978c0f11332823010a754 by jdenny.ornl
[lit] Add --ignore-fail

For some build configurations, `check-all` calls lit multiple times to
run multiple lit test suites.  Most recently, I've found this to be
true when configuring openmp as part of `LLVM_ENABLE_RUNTIMES`, but
this is not the first time.

If one test suite fails, none of the remaining test suites run, so you
cannot determine if your patch has broken them.  It can then be
frustrating to try to determine which `check-` targets will run the
remaining tests without getting stuck on the failing tests.

When such cases arise, it is probably best to adjust the cmake
configuration for `check-all` to run all test suites as part of one
lit invocation.  Because that fix will likely not be implemented and
land immediately, this patch introduces `--ignore-fail` to serve as a
workaround for developers trying to see test results until it does
land:

```
$ LIT_OPTS=--ignore-fail ninja check-all
```

One problem with `--ignore-fail` is that it makes it challenging to
detect test failures in a script, perhaps in CI.  This problem should
serve as motivation to actually fix the cmake configuration instead of
continuing to use `--ignore-fail` indefinitely.

Reviewed By: jhenderson, thopre

Differential Revision: https://reviews.llvm.org/D96371
The file was addedllvm/utils/lit/tests/Inputs/ignore-fail/xfail.txt
The file was addedllvm/utils/lit/tests/Inputs/ignore-fail/xpass.txt
The file was modifiedllvm/utils/lit/lit/main.py
The file was addedllvm/utils/lit/tests/ignore-fail.py
The file was modifiedllvm/utils/lit/lit/cl_arguments.py
The file was addedllvm/utils/lit/tests/Inputs/ignore-fail/fail.txt
The file was modifiedllvm/docs/CommandGuide/lit.rst
The file was addedllvm/utils/lit/tests/Inputs/ignore-fail/lit.cfg
The file was addedllvm/utils/lit/tests/Inputs/ignore-fail/unresolved.txt
Commit 086670d367869e62a3c5dffe3cd9bed04a5898c2 by craig.topper
[RISCV] Support fixed vector extract element. Use VL=1 for scalable vector extract element.

I've changed to use VL=1 for slidedown and shifts to avoid extra
element processing that we don't need.

The i64 fixed vector handling on i32 isn't great if the vector type
isn't legal due to an ordering issue in type legalization. If the
vector type isn't legal, we fall back to default legalization
which will bitcast the vector to vXi32 and use two independent extracts.
Doing better will require handling several different cases by
manually inserting insert_subvector/extract_subvector to adjust the type
to a legal vector before emitting custom nodes.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D97319
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
Commit e339bba637b941c8e78057319b7654c4babf18cb by Jessica Paquette
[AArch64][GlobalISel] Fix manual selection for v4s16 and v8s8 G_DUP

The manual G_DUP selection code would produce DUPv16i8 for v8s8s and DUPv8i16
for v4s16.

This adds the missing cases to the manual selection code, and makes it return
false when there is an unexpected size.

Update select-dup.mir to reflect the change.

Differential Revision: https://reviews.llvm.org/D97240
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
Commit c2487bf7dfdda59b775b3d5a06684af243790125 by jyknight
Remove a workaround for MSVC 2013, now that MSVC 2017 is the minimum.

In MSVC 2013, 'alignas(integer-template-arg)' didn't compile; verified
on godbolt that this now works properly.
The file was modifiedllvm/include/llvm/Support/TrailingObjects.h
Commit 17b4e695ce0ef89eac4a37df2df49d4c0e700766 by i
[llvm-objcopy] If input=output, preserve umask bits, otherwise drop S_ISUID/S_ISGID bits

This makes the behavior similar to cp

```
chmod u+s,g+s,o+x a
sudo llvm-strip a -o b
// With this patch, b drops set-user-ID and set-group-ID bits.
// sudo cp a b => b does not have set-user-ID or set-group-ID bits.
```

This also changes the behavior for the following case:

```
chmod u+s,g+s,o+x a
llvm-strip a
// a preserves set-user-ID and set-group-ID bits.
// This matches binutils<2.36 and probably >=2.37.  2.36 and 2.36.1 have some compatibility issues.
```

Differential Revision: https://reviews.llvm.org/D97253
The file was modifiedllvm/tools/llvm-objcopy/llvm-objcopy.cpp
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/mirror-permissions-unix.test
Commit 38dfb235db19caa1aaa58c1c8153a7464b932087 by Jonas Devlieghere
[lldb] Support debugging utility functions

LLDB uses utility functions to run code in the inferior for its own
internal purposes, such as reading classes from the Objective-C runtime
for example. Because these expressions should be transparent to the
user, we ignore breakpoints and unwind the stack on errors, which
makes them hard to debug.

This patch adds a new setting target.debug-utility-expression that, when
enabled, changes these options to facilitate debugging. It enables
breakpoints, disables unwinding and writes out the utility function
source code to disk so it shows up in the source view.

Differential revision: https://reviews.llvm.org/D97249
The file was modifiedlldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
The file was modifiedlldb/include/lldb/Expression/UtilityFunction.h
The file was modifiedlldb/source/Expression/FunctionCaller.cpp
The file was modifiedlldb/source/Expression/UtilityFunction.cpp
The file was modifiedlldb/include/lldb/Target/Target.h
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangExpressionSourceCode.cpp
The file was modifiedlldb/source/Target/Target.cpp
The file was modifiedlldb/source/Target/TargetProperties.td
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangUtilityFunction.cpp
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangUtilityFunction.h
The file was modifiedlldb/source/Plugins/ExpressionParser/Clang/ClangExpressionSourceCode.h
Commit 705068cb8c4d86c798c4134f0a332f4a45c7df04 by hanchung
[mlir][linalg] Support for using output values in TC definitions.

This will allow us to define select(pred, in, out) for TC ops, which is useful
for pooling ops.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D97312
The file was modifiedmlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
The file was modifiedmlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOpsSpec.tc
Commit 21895a2beff7fcd92441c884de7c04f324996c79 by hanchung
[mlir][linalg] Reuse the symbol if attribute uses are identical.

Depends On D97312

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D97383
The file was modifiedmlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
The file was modifiedmlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
Commit e79cd47e1620045562960ddfe17ab0c4f6e6628f by riddleriver
[mlir][docs] Small fix to local Pass Manager reproduction documentation
The file was modifiedmlir/docs/PassManagement.md
Commit 78b6d73a93fc6085d2a2fc84bdce1bbde740cf16 by Matthew.Arsenault
AMDGPU: Add even aligned VGPR/AGPR register classes

gfx90a operations require even aligned registers, but this was
previously achieved by reserving registers inside the full class.

Ideally this would be captured in the static instruction definitions
for the operands, and we would have different instructions per
subtarget. The hackiest part of this is we need to manually reassign
AGPR register classes after instruction selection (we get away without
this for VGPRs since those types are actually registered for legal
types).
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/dpp64_combine.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was removedllvm/test/CodeGen/AMDGPU/reserved-vgpr-tuples.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was addedllvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
The file was modifiedllvm/lib/Target/AMDGPU/GCNSubtarget.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
The file was addedllvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.h
The file was addedllvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/reserved-reg-in-clause.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/twoaddr-fma-f64.mir
Commit 589223e044dbea0554d2e8b54bf49e9cc278b643 by Matthew.Arsenault
AMDGPU: Remove special case in shouldCoalesce

Unaligned registers are now constrained with classes, rather than
specially reserving a subset of the whole class.
The file was modifiedllvm/test/CodeGen/AMDGPU/coalesce-vgpr-alignment.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/global-atomics-fp.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
Commit 3475159122b656ff098e2f44af32dc56f3beb610 by spatel
[InstCombine] add tests for fdiv+powi; NFC
The file was modifiedllvm/test/Transforms/InstCombine/fdiv.ll
Commit c218c80c730a14a1cbcebd588b18220a879702c6 by martin
[libcxx] [test] Quote the path to the python interpreter

This should allow running tests with the interpreter in some of the
default paths where Python for Windows might be installed.

Differential Revision: https://reviews.llvm.org/D97369
The file was modifiedlibcxx/test/CMakeLists.txt
Commit 0d4e12e3c110e5d73302a369f5e17d1fa67710e1 by michael.hliao
[amdgpu] Atomic should be source of divergence.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D97392
The file was addedllvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit 52745e4d907867bbb28fb8b0e8456915611a47a3 by listmail
[tests] precommit tests for D97219
The file was modifiedllvm/test/Transforms/LoopStrengthReduce/post-increment-insertion.ll