SuccessChanges

Summary

  1. [lldb][NFC] Remove StringList::AutoComplete (details)
  2. [DebugInfo] Test for variable range un-coalescing (details)
  3. [ARM] MVE sext costs (details)
  4. [ARM] Add support for MVE vaddv (details)
  5. [ELF][ARM] Add a test that maxes out the thunk convergence limit (details)
  6. [DebugInfo] Make postra sinking of DBG_VALUEs subregister-safe (details)
Commit b8639f5c0fd82d4c29eb55590e1dfaf0a54dbb94 by Raphael Isemann
[lldb][NFC] Remove StringList::AutoComplete
We don't need this very specific function in StringList that we only
call once in LLDB.
llvm-svn: 369242
The file was modifiedlldb/source/Commands/CommandCompletions.cpp
The file was modifiedlldb/source/Utility/StringList.cpp
The file was modifiedlldb/include/lldb/Utility/StringList.h
Commit b58ba8aae710cba925e3c59accde6695c1d40aa3 by jeremy.morse.llvm
[DebugInfo] Test for variable range un-coalescing
LiveDebugVariables can coalesce ranges of variable locations across
multiple basic blocks. However when it recreates DBG_VALUE instructions,
it has to recreate one DBG_VALUE per block, otherwise it doesn't
represent the pre-regalloc layout and variable assignments can go
missing.
This feature works -- however while mucking around with
LiveDebugVariables, I commented the relevant code it out and no tests
failed. Thus, here's a test that checks LiveDebugVariables preserves
DBG_VALUEs across block boundaries.
Differential Revision: https://reviews.llvm.org/D66347
llvm-svn: 369243
The file was addedllvm/test/DebugInfo/MIR/X86/livedebugvars-crossbb-interval.mir
Commit 2bfc13fde1296a63dba5d5589aac9aa5ae45949e by david.green
[ARM] MVE sext costs
This adds some sext costs for MVE, taken from the length of assembly
sequences that we currently generate.
Differential Revision: https://reviews.llvm.org/D66010
llvm-svn: 369244
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/ARM/cast.ll
Commit f312c1ecf4bc7003f4b10231a3147d004a39bfae by sam.tebbs
[ARM] Add support for MVE vaddv
This patch adds vecreduce_add and the relevant instruction selection for
vaddv.
Differential revision: https://reviews.llvm.org/D66085
llvm-svn: 369245
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.h
The file was addedllvm/test/CodeGen/Thumb2/mve-vaddv.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit 2cafd872fb97f2899ac0f1b01ed82ee88581c86d by peter.smith
[ELF][ARM] Add a test that maxes out the thunk convergence limit
Add a test that takes the maximum amount of passes permitted to
converge. This will make sure that any symbol defined in a linker script
gets the correct value and that any other convergence limit involving
symbol address doesn't restrict Thunk convergence.
Differential Revision: https://reviews.llvm.org/D66346
llvm-svn: 369246
The file was addedlld/test/ELF/arm-thunk-many-passes.s
Commit 176bbd5cde362ad965dcda5cc72b655117685a5a by jeremy.morse.llvm
[DebugInfo] Make postra sinking of DBG_VALUEs subregister-safe
Currently the machine instruction sinker identifies DBG_VALUE insts that
also need to sink by comparing register numbers. Unfortunately this
isn't safe, because (after register allocation) a DBG_VALUE may read a
register that aliases what's being sunk. To fix this, identify the
DBG_VALUEs that need to sink by recording & examining their register
units. Register units gives us the following guarantee:
  "Two registers overlap if and only if they have a common register
unit"
[MCRegisterInfo.h]
Thus we can always identify aliasing DBG_VALUEs if the set of register
units read by the DBG_VALUE, and the register units of the instruction
being sunk, intersect. (MachineSink already uses classes like
"LiveRegUnits" for determining sinking validity anyway).
The test added checks for super and subregister DBG_VALUE reads of a
sunk copy being sunk as well.
Differential Revision: https://reviews.llvm.org/D58191
llvm-svn: 369247
The file was addedllvm/test/DebugInfo/MIR/X86/postra-subreg-sink.mir
The file was modifiedllvm/lib/CodeGen/MachineSink.cpp