Changes

[ARM][MVE] Tail predicate bottom/top muls.
Add VMULL and VQDMULL variants to our tail predication white list.
Differential Revision: https://reviews.llvm.org/D71465

[ARM][MVE] Tail predicate in the presence of vcmp
Record the discovered VPT blocks while checking for validity and, for 
now, only handle blocks that begin with VPST and not VPT. We're now 
allowing more than one instruction to define vpr, but each block must 
somehow be predicated using the vctp. This leaves us with several 
scenarios which need fixing up: 1) A VPT block with is only predicated
by the vctp and has no
  internal vpr defs. 2) A VPT block which is only predicated by the vctp
but has an
  internal vpr def. 3) A VPT block which is predicated upon the vctp as
well as another
  vpr def. 4) A VPT block which is not predicated upon a vctp, but
contains it
  and all instructions within the block are predicated upon in.
The changes needed are, for: 1) The easy one, just remove the vpst and
unpredicate the
  instructions in the block. 2) Remove the vpst and unpredicate the
instructions up to the
  internal vpr def. Need insert a new vpst to predicate the
  remaining instructions. 3) No nothing. 4) The vctp will be inside a
vpt and the instruction will be removed,
  so adjust the size of the mask on the vpst.
Differential Revision: https://reviews.llvm.org/D71107

[lldb] Remove XFAIL from TestDeadStrip.py
Fixed by 92211b.

Re-land "[cmake] Add dependency on llvm-dwarfdump to llvm-locstats"
This reverts commit f8e2ab3cd347cb7fb959ea0ece795f4eb347094c.

[ARM][MVE] Fixes for tail predication.
1) Fix an issue with the incorrect value being used for the number of
  elements being passed to [d|w]lstp. We were trying to check that
  the value was available at LoopStart, but this doesn't consider
  that the last instruction in the block could also define the
  register. Two helpers have been added to RDA for this. 2) Insert some
code to now try to move the element count def or the
  insertion point so that we can perform more tail predication. 3)
Related to (1), the same off-by-one could prevent us from
  generating a low-overhead loop when a mov lr could have been
  the last instruction in the block. 4) Fix up some instruction
attributes so that not all the
  low-overhead loop instructions are labelled as branches and
  terminators - as this is not true for dls/dlstp.
Differential Revision: https://reviews.llvm.org/D71609