SuccessChanges

Summary

  1. [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0 (details)
Commit 6d88b7d6e712789115c149c5abb0f359d1222545 by shkzhang
[PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0
Summary: If we didn't set the value for hasSideEffects bit in our td
file, `llvm-tblgen` will set it as true for those instructions which has
no match pattern. The instructions `MTLR` and `MFLR` don't set the
hasSideEffects flag and don't have match pattern, so their
hasSideEffects flag will be set true by
`llvm-tblgen`. But in fact, we can use `[LR]` to model the two
instructions, so they should not have SideEffects.
This patch is to modify the hasSideEffects of MTLR and MFLR from 1 to 0.
Reviewed By: jsji
Differential Revision: https://reviews.llvm.org/D71390
The file was modifiedllvm/lib/Target/PowerPC/PPCInstr64Bit.td
The file was modifiedllvm/test/CodeGen/PowerPC/not-fixed-frame-object.ll
The file was modifiedllvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
The file was modifiedllvm/test/CodeGen/PowerPC/machine-pre.ll
The file was modifiedllvm/test/CodeGen/PowerPC/pr43527.ll
The file was modifiedllvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
The file was modifiedllvm/test/CodeGen/PowerPC/pr44183.ll
The file was modifiedllvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll
The file was modifiedllvm/test/CodeGen/PowerPC/sms-phi-1.ll
The file was modifiedllvm/test/CodeGen/PowerPC/CSR-fit.ll
The file was modifiedllvm/test/CodeGen/PowerPC/sms-phi-3.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/test/CodeGen/PowerPC/csr-split.ll
The file was modifiedllvm/test/CodeGen/PowerPC/sjlj.ll