SuccessChanges

Summary

  1. AMDGPU/GlobalISel: Account for G_PHI result bank (details)
  2. AMDGPU: Generate check lines (details)
  3. AMDGPU: Improve llvm.round.f64 lowering for CI+ (details)
  4. GlobalISel: moreElementsVector for FP min/max (details)
  5. AMDGPU/GlobalISel: Add select test for fexp2 (details)
  6. [ARM][Thumb][FIX] Add unwinding information to t4 (details)
  7. [InstCombine] propagate sign argument through nested copysigns (details)
Commit 491cfa4250d7a146131202ad33878ba398c7ae87 by arsenm2
AMDGPU/GlobalISel: Account for G_PHI result bank
Sometimes the result bank of the phi is already assigned to something,
and should not be ignored. This is in preparation for additional boolean
phi handling changes.
Also refine the logic to fix some cases that were incorrectly deciding
to use SGPRs.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit 58bcf51107033a1b6ce77c365578d38bfb62062a by arsenm2
AMDGPU: Generate check lines
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
Commit 9e1a2a668b9d52bc76c92577ac01c301f95bb697 by arsenm2
AMDGPU: Improve llvm.round.f64 lowering for CI+
The path already used for f16/f32 works a lot better when v_trunc_f64 is
available.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
Commit 9fd31fdbd3049e3e45fc046bedb9011d0c828e87 by arsenm2
GlobalISel: moreElementsVector for FP min/max
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
Commit 18240c3cd632521f95f2ddd08ecc4f7cf0efe3c8 by arsenm2
AMDGPU/GlobalISel: Add select test for fexp2
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir
Commit f33fd9648c442a23f863e03ea1c806da15278fd1 by diogo.sampaio
[ARM][Thumb][FIX] Add unwinding information to t4
Summary: Add missing part of patch D71361. Now that the stack-frame can
be operated using a addw/subw instruction, they should appear in the
unwinding list.
Reviewers: dmgreen, efriedma
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72000
The file was modifiedllvm/lib/Target/ARM/ARMAsmPrinter.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/emit-unwinding.ll
Commit 987eb8e26ccf73180b3b53b8a38d87e3e6489326 by spatel
[InstCombine] propagate sign argument through nested copysigns
This is another optimization suggested in PR44153:
https://bugs.llvm.org/show_bug.cgi?id=44153
The file was modifiedllvm/test/Transforms/InstCombine/copysign.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp