Commit
02f694b69a8b30db7b5d43670da5ab3b9f31bb81
by wan.yu [NFC] Test commit, revert whitespace change As per the Developer Policy, upon obtaining commit access.
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 | clang/lib/Driver/ToolChains/AIX.cpp |
Commit
7b518dcb291e740c3e957d93c2b4046bc8a97f00
by a.bataev[OPENMP50]Support lastprivate conditional updates in inc/dec unary ops. Added support for checking of updates of variables used in unary pre(pos) inc/dec expressions.
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 | clang/lib/CodeGen/CGExpr.cpp |
 | clang/lib/CodeGen/CGOpenMPRuntime.cpp |
 | clang/test/OpenMP/sections_lastprivate_codegen.cpp |
 | clang/lib/CodeGen/CGExprScalar.cpp |
 | clang/lib/CodeGen/CGOpenMPRuntime.h |
 | clang/lib/CodeGen/CGStmtOpenMP.cpp |
 | clang/test/OpenMP/for_lastprivate_codegen.cpp |
Commit
ca868002d31b013b1d5998177ea4252ffcd84b67
by craig.topper[X86] Rename vec-strict-*-cmp.ll to vec-strict-cmp-*.ll to match other strict files wich have the size at the end. NFC
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 | llvm/test/CodeGen/X86/vec-strict-256-cmp.ll |
 | llvm/test/CodeGen/X86/vec-strict-cmp-512.ll |
 | llvm/test/CodeGen/X86/vec-strict-cmp-256.ll |
 | llvm/test/CodeGen/X86/vec-strict-512-cmp.ll |
 | llvm/test/CodeGen/X86/vec-strict-128-cmp.ll |
 | llvm/test/CodeGen/X86/vec-strict-cmp-128.ll |
Commit
62f3403bfc17906aba555d6100e0136363f6a649
by craig.topper[LegalizeTypes] Add widening support for STRICT_FSETCC/FSETCCS This patch adds widening which really just scalarizes because we don't have a strategy for the extra elements we would need to pad with. Differential Revision: https://reviews.llvm.org/D72193
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 | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp |
 | llvm/test/CodeGen/X86/vec-strict-cmp-sub128.ll |
 | llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h |
Commit
317cbdad4d1b9ea7ec703072aba34eeb62c9d3af
by Jonas Devlieghere[lldb/Docs] Describe optional dependencies on build page. List the different CMake flags controlling the optional dependencies as per the discussion on the mailing list: http://lists.llvm.org/pipermail/lldb-dev/2020-January/015867.html
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 | lldb/docs/resources/build.rst |
Commit
6a0564adcfe65956cb1099e8ec6c4801655007c4
by craig.topper[X86] Improve v4i32->v4f64 uint_to_fp for AVX1/AVX2 targets. Use zext+or+fsub to do the conversion. Similar to D71971. Differential Revision: https://reviews.llvm.org/D71971
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 | llvm/test/CodeGen/X86/vec_uint_to_fp.ll |
 | llvm/lib/Target/X86/X86ISelLowering.cpp |
 | llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll |
 | llvm/test/CodeGen/X86/vec_int_to_fp.ll |
 | llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll |
Commit
5518a02a83e855edeff7d8b4db685ec5d1b4144e
by arsenm2llc/MIR: Fix setFunctionAttributes for MIR functions A random set of attributes are implemented by llc/opt forcing the string attributes on the IR functions before processing anything. This would not happen for MIR functions, which have not yet been created at this point. Use a callback in the MIR parser, purely to avoid dealing with the ugliness that the command line flags are in a .inc file, and would require allowing access to these flags from multiple places (either from the MIR parser directly, or a new utility pass to implement these flags). It would probably be better to cleanup the flag handling into a separate library. This is in preparation for treating more command line flags with a corresponding function attribute in a more uniform way. The fast math flags in particular have a messy system where the command line flag sets the behavior from a function attribute if present, and otherwise the command line flag. This means if any other pass tries to inspect the function attributes directly, it will be inconsistent with the intended behavior. This is also inconsistent with the current behavior of -mcpu and -mattr, which overwrites any pre-existing function attributes. I would like to move this to consistenly have the command line flags not overwrite any pre-existing attributes, and to always ensure the command line flags are consistent with the function attributes.
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 | llvm/tools/llc/llc.cpp |
 | llvm/include/llvm/CodeGen/MIRParser/MIRParser.h |
 | llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline.mir |
 | llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline-ir.mir |
 | llvm/lib/CodeGen/MIRParser/MIRParser.cpp |
 | llvm/include/llvm/CodeGen/CommandFlags.inc |
Commit
14d25052a2902dacdd73aa1714ba1fb639c1dedd
by arsenm2AMDGPU: Use ImmLeaf for inline immediate predicates
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 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
 | llvm/lib/Target/AMDGPU/SIInstrInfo.h |
 | llvm/lib/Target/AMDGPU/SIInstrInfo.td |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |
 | llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
 | llvm/lib/Target/AMDGPU/SIInstructions.td |
Commit
a506efff18224a0c73db42bed8679413514c28b1
by arsenm2AMDGPU: Use ImmLeaf This solves one GlobalISel importer error, but the pattern still fails for another reason.
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 | llvm/lib/Target/AMDGPU/SIInstrInfo.td |
Commit
7f2db2917da9e4fe43976b7abe37400812ed5dea
by arsenm2AMDGPU: Fix legalizing f16 fpow The existing test only covered one case for r600. The use of mul_legacy also looks suspicious to me, but leave it for now. The patterns are also not making use of source modifiers.
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 | llvm/lib/Target/AMDGPU/SIInstructions.td |
 | llvm/lib/Target/AMDGPU/SIISelLowering.cpp |
 | llvm/test/CodeGen/AMDGPU/fpow.ll |
Commit
0b093f02120e212b9c1305eae626e9b5e99b92fa
by arsenm2GlobalISel: Start adding computeNumSignBits to GISelKnownBits
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 | llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp |
 | llvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h |
 | llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp |
Commit
1060b9e23b8f9d2802835896947ec281ba3b4f6b
by arsenm2GlobalISel: Correct result type for G_FCMP in lowerFPTOUI Using the final result type doesn't make any sense. Use the natural default boolean type for the select condition.
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 | llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp |
 | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll |
 | llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir |
Commit
ee6b8722ffa101b57af9029c84691cb7e8a43799
by arsenm2GlobalISel: Fix unsupported legalize action This would complain about invalid legalizer rules otherwise. Mark some operations as unsupported for AMDGPU. This currently seems to produce the same legalize error as when no rules are defined, but eventually this should produce a proper user facing error.
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 | llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h |
 | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir |
Commit
f5329bfc76bb6fc30a589e8238aabc005c52e5d6
by tyker[Diagnostic] make Wmisleading-indendation not warn about labels Reviewers: aaron.ballman, xbolva00 Reviewed By: aaron.ballman Subscribers: nickdesaulniers, nathanchance Differential Revision: https://reviews.llvm.org/D72202
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 | clang/lib/Parse/ParseStmt.cpp |
 | clang/test/Parser/warn-misleading-indentation.cpp |
Commit
24ee4edee8e00bb7ad3d3cda17d02a442456ff3e
by Jinsong Ji[PowerPC][NFC] Rename record instructions to use _rec suffix instead of o We use o suffix to indicate record form instuctions, (as it is similar to dot '.' in mne?) This was fine before, as we did not support XO-form. However, with https://reviews.llvm.org/D66902, we now have XO-form support. It becomes confusing now to still use 'o' for record form, and it is weird to have something like 'Oo' . This patch rename all 'o' instructions to use '_rec' instead. Also rename `isDot` to `isRecordForm`. Reviewed By: #powerpc, hfinkel, nemanjai, steven.zhang, lkail Differential Revision: https://reviews.llvm.org/D70758
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 | llvm/lib/Target/PowerPC/PPCISelLowering.cpp |
 | llvm/lib/Target/PowerPC/PPCInstrVSX.td |
 | llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir |
 | llvm/lib/Target/PowerPC/PPCMIPeephole.cpp |
 | llvm/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir |
 | llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir |
 | llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir |
 | llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll |
 | llvm/lib/Target/PowerPC/PPCInstrAltivec.td |
 | llvm/lib/Target/PowerPC/PPCISelLowering.h |
 | llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir |
 | llvm/test/CodeGen/PowerPC/fold-rlwinm.mir |
 | llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp |
 | llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp |
 | llvm/lib/Target/PowerPC/P9InstrResources.td |
 | llvm/lib/Target/PowerPC/PPCInstr64Bit.td |
 | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp |
 | llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir |
 | llvm/lib/Target/PowerPC/PPCInstrHTM.td |
 | llvm/lib/Target/PowerPC/PPCInstrInfo.td |
 | llvm/test/CodeGen/PowerPC/block-placement.mir |
 | llvm/lib/Target/PowerPC/PPCInstrFormats.td |
Commit
d8fd92eaaa34b463a573ed1b216f93a3d1ff6eef
by thomasp[FileCheck] Remove FileCheck prefix in API Summary: When FileCheck was made a library, types in the public API were renamed to add a FileCheck prefix, such as Pattern to FileCheckPattern. Many types were moved into a private interface and thus don't need this prefix anymore. This commit removes those unneeded prefixes. Reviewers: jhenderson, jdenny, probinson, grimar, arichardson, rnk Reviewed By: jhenderson Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72186
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 | llvm/lib/Support/FileCheckImpl.h |
 | llvm/lib/Support/FileCheck.cpp |
 | llvm/unittests/Support/FileCheckTest.cpp |
Commit
83d690a149802d40c711d4fb5a058dd1ebe4aa23
by isanbardDon't rely on 'l'(ell) modifiers to indicate a label reference Summary: It's not necessary to use an 'l'(ell) modifier when referencing a label. Treat block addresses and MBB references as if the modifier is used anyway. This prevents us from generating references to ficticious labels. Reviewers: jyknight, nickdesaulniers, hfinkel Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71849
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 | llvm/test/CodeGen/X86/callbr-asm.ll |
 | llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp |
Commit
71a2a62163cfafbc31cd827106506c73ff49e8b5
by phosek[CMake] Pass symlink dependency to add_llvm_install_targets explicitly The install-${name}-stripped targets don't strip when ${name} is being symlinked, e.g. llvm-ar or llvm-objcopy. The problem is that llvm_install_symlink passes install-${dest} as a dependency of install-${name}, e.g. install-llvm-ar becomes a dependency of both install-llvm-ranlib and install-llvm-ranlib-stripped. What this means is that when installing a distribution that contains both llvm-ar and llvm-ranlib is that first the stripped version of llvm-ar is installed (by the install-llvm-ar-stripped target) and then it's overwritten by an unstripped version of llvm-ar bnecause install-llvm-ranlib-stripped has install-llvm-ranlib as a dependency as mentioned earlier. To avoid this issue, rather than passing the install-${dest} as dependency, we introduce a new argument to add_llvm_install_targets for symlink target which expands it into an appropriate dependency, i.e. install-${dest} for install-${name} target and install-${dest}-stripped for install-${name}-stripped. Differential Revision: https://reviews.llvm.org/D71951
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 | llvm/cmake/modules/AddLLVM.cmake |
Commit
59fadc14eeb1d63177b76147b26348a106ac1f9b
by ditaliano[NSArray] Remove a very old and deprecated formatter. Checked with the Foundation folks.
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 | lldb/source/Plugins/Language/ObjC/NSArray.cpp |
Commit
b5e7f95cfbeb28ff8b966a2b7e38a03f32410030
by eugenis[msan] Check qsort input. Summary: Qsort interceptor suppresses all checks by unpoisoning the data in the wrapper of a comparator function, and then unpoisoning the output array as well. This change adds an explicit run of the comparator on all elements of the input array to catch any sanitizer bugs. Reviewers: vitalybuka Subscribers: #sanitizers, llvm-commits Tags: #sanitizers, #llvm Differential Revision: https://reviews.llvm.org/D71780
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 | compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc |
 | compiler-rt/test/msan/qsort.cpp |
Commit
08d17cb065da46be02d36ebeaac1106ee330935b
by listmail[X86] Move an enum definition into a header to simplify future patches [NFC]
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 | llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp |
 | llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h |
Commit
450073c639d7f182e48ec8b1b588212194089a52
by Jason MolendaChange the patterns to include the prefix '= ' so we don't pass errantly. Looking at a sometimes-passing test case on a platform where random values were being returned - sometimes the expected digit ('1' or '2') would be included in the random returned value. Add a prefix to reduce the likelihood of this a bit.
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 | lldb/packages/Python/lldbsuite/test/commands/expression/call-overridden-method/TestCallOverriddenMethod.py |
Commit
f3de8ab5ccedefb3165dae2511650d6a60e905cf
by arsenm2GlobalISel: Implement lower for G_INTRINSIC_ROUND Mostly copied from AMDGPU lowering implementation, except used G_SITOFP instead of directly creating a select on -1.0, 0.0.
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 | llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h |
 | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
 | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp |
 | llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-round.mir |
 | llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp |
Commit
26f714ff43e3498ae2528ad8c9875de77a529472
by arsenm2TableGen/GlobalISel: Handle default operands that are used Copy the logic from the existing handling in the DAG matcher emittter. This will enable some AMDGPU pattern cleanups without breaking GlobalISel tests, and eventually handle importing more patterns. The test is a bit annoying since the sections seem to randomly sort themselves if anything else is added in the future.
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 | llvm/test/TableGen/DefaultOpsGlobalISel.td |
 | llvm/utils/TableGen/GlobalISelEmitter.cpp |
Commit
4e85ca9562a588eba491e44bcbf73cb2f419780f
by arsenm2AMDGPU/GlobalISel: Replace handling of boolean values This solves selection failures with generated selection patterns, which would fail due to inferring the SGPR reg bank for virtual registers with a set register class instead of VCC bank. Use instruction selection would constrain the virtual register to a specific class, so when the def was selected later the bank no longer was set to VCC. Remove the SCC reg bank. SCC isn't directly addressable, so it requires copying from SCC to an allocatable 32-bit register during selection, so these might as well be treated as 32-bit SGPR values. Now any scalar boolean value that will produce an outupt in SCC should be widened during RegBankSelect to s32. Any s1 value should be a vector boolean during selection. This makes the vcc register bank unambiguous with a normal SGPR during selection. Summary of how this should now work: - G_TRUNC is always a no-op, and never should use a vcc bank result. - SALU boolean operations should be promoted to s32 in RegBankSelect apply mapping - An s1 value means vcc bank at selection. The exception is for legalization artifacts that use s1, which are never VCC. All other contexts should infer the VCC register classes for s1 typed registers. The LLT for the register is now needed to infer the correct register class. Extensions with vcc sources should be legalized to a select of constants during RegBankSelect. - Copy from non-vcc to vcc ensures high bits of the input value are cleared during selection. - SALU boolean inputs should ensure the inputs are 0/1. This includes select, conditional branches, and carry-ins. There are a few somewhat dirty details. One is that G_TRUNC/G_*EXT selection ignores the usual register-bank from register class functions, and can't handle truncates with VCC result banks. I think this is OK, since the artifacts are specially treated anyway. This does require some care to avoid producing cases with vcc. There will also be no 100% reliable way to verify this rule is followed in selection in case of register classes, and violations manifests themselves as invalid copy instructions much later. Standard phi handling also only considers the bank of the result register, and doesn't insert copies to make the source banks match. This doesn't work for vcc, so we have to manually correct phi inputs in this case. We should add a verifier check to make sure there are no phis with mixed vcc and non-vcc register bank inputs. There's also some duplication with the LegalizerHelper, and some code which should live in the helper. I don't see a good way to share special knowledge about what types to use for intermediate operations depending on the bank for example. Using the helper to replace extensions with selects also seems somewhat awkward to me. Another issue is there are some contexts calling getRegBankFromRegClass that apparently don't have the LLT type for the register, but I haven't yet run into a real issue from this. This also introduces new unnecessary instructions in most cases, since we don't yet try to optimize out the zext when the source is known to come from a compare.
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 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir |
 | llvm/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def |
 | llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir |
 | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir |
 | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir |
 | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
 | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi-invalid.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir |
Commit
d4c9e13324443c0324148156d54d2c7c81393327
by arsenm2AMDGPU/GlobalISel: Select G_UADDE/G_USUBE
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 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.gfx10.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.gfx10.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.mir |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp |
 | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.mir |
Commit
c6fd16af2be98b49d663285e3808ecde61bec614
by AkiraUse FileCheck instead of grep
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 | clang/test/CodeGenObjC/encode-test-2.m |