SuccessChanges

Summary

  1. AMDGPU/GlobalISel: Fix constant bus violation with source modifiers (details)
  2. AMDGPU/GlobalISel: Select llvm.amdgcn.fmul.legacy (details)
  3. AMDGPU/GlobalISel: Legalize G_FPOW (details)
  4. AMDGPU/GlobalISel: Manually select G_BUILD_VECTOR_TRUNC (details)
  5. [ARM] Correct Formatting. NFC (details)
  6. AMDGPU/GlobalISel: Precommit xnor matching test (details)
  7. [ELF] Ignore the maximum of input section alignments for two cases (details)
  8. [ELF] Warn changed output section address (details)
  9. [lldb-vscode] Use libOption with tablegen to parse command line options. (details)
  10. [ELF] Shuffle .init_array/.fini_array with --shuffle-sections= (details)
  11. [TargetLowering] Apply basic shift combines before recursive SimplifyDemandedBits calls. (details)
  12. AMDGPU/GlobalISel: Fix xnor matching (details)
  13. AMDGPU/GlobalISel: Commit test changes I forgot to squash (details)
  14. GlobalISel: Fix narrowing of (G_ASHR i64:x, 32) (details)
  15. [AArch64][SVE] Add +fullfp16 to sve-vector-splat.ll (details)
  16. [DSE,MSSA] Add debug counter. (details)
  17. [AST matchers] Add basic matchers for googletest EXPECT/ASSERT calls. (details)
  18. [VectorCombine] refactor matching code to reduce duplication; NFC (details)
  19. [AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations (details)
  20. AMDGPU: Use default operand for VOP3P clamp (details)
  21. [SystemZ]  Return scalarized costs for vector instructions on older archs. (details)
  22. [gn build] Port 23444edf30b (details)
  23. [SimplifyLibCalls][IRBuilder] Accept any IRBuilder in SimplifyLibCalls (details)
  24. [X86] Fix SDLoc initialization (details)
  25. [VectorUtils] Move ToVectorTy to VectorUtils.h (NFC). (details)
  26. [DSE,MSSA] Dbg counters required assertions. Mark test accordingly. (details)
  27. [InstCombine] Use replaceOperand() in more places (details)
Commit b64aa8c715112ac4b9fd1ae8eb5ecb981ecd091a by arsenm2
AMDGPU/GlobalISel: Fix constant bus violation with source modifiers

This looked through copies to find the source modifiers, which may
have been SGPR->VGPR copies added to avoid potential constant bus
violations. Re-insert a copy to a VGPR if this happens.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
Commit fab4cdea3911b19d1b1819102aee0252cbd4eba4 by arsenm2
AMDGPU/GlobalISel: Select llvm.amdgcn.fmul.legacy
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
Commit 79ff188addeeea127c7a7edd808c5821917d4bb6 by arsenm2
AMDGPU/GlobalISel: Legalize G_FPOW

There are few differences from the DAG handling. First, the DAG
handling uses a primitive selection pattern instead of custom
legalizing it. Because of this, this makes use of source modifiers
while the DAG does not.

Also instead of promoting f16, try to use the f16 log/exp. There's no
f16 fmul_legacy, so widen just for the multiply, although I'm not sure
that's the best solution.
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
Commit ac7abe0ba9ae4c6a2248cc3ef4e4fe7e6d270105 by arsenm2
AMDGPU/GlobalISel: Manually select G_BUILD_VECTOR_TRUNC

We have patterns for s_pack* selection, but they assume the inputs are
a build_vector with 16-bit inputs, not a truncating build
vector. Since there's still outstanding work for how to handle
mismatched result and source element vector operations, and since I'm
trying a different packed vector strategy than SelectionDAG, just
manually select this for now.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit 83012cb217189bb6faa1256cc44fd0c306363264 by david.green
[ARM] Correct Formatting. NFC

Also removed an unnecessary TODO that I don't believe is relevant for
the instruction in question.
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit 89dc8fe6222041319e073ceb8ee0cb38d045ea16 by arsenm2
AMDGPU/GlobalISel: Precommit xnor matching test
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
Commit 6ed8e2014330b6a48d238cdc4357e788cdd6d445 by maskray
[ELF] Ignore the maximum of input section alignments for two cases

Follow-up for D74286.

Notations:

* alignExpr: the computed ALIGN value
* max_input_align: the maximum of input section alignments

This patch changes the following two cases to match GNU ld:

* When ALIGN is present, GNU ld sets output sh_addr to alignExpr, while lld use max(alignExpr, max_input_align)
* When addrExpr is specified but alignExpr is not, GNU ld sets output sh_addr to addrExpr, while lld uses `advance(0, max_input_align)`

Note, sh_addralign is still set to max(alignExpr, max_input_align).

lma-align.test is enhanced a bit to check we don't overalign sh_addr.

fixSectionAlignments() sets addrExpr but not alignExpr for the `!hasSectionsCommand` case.
This patch sets alignExpr as well so that max_input_align will be respected.

Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D74736
The file was modifiedlld/test/ELF/linkerscript/outsections-addr.s
The file was modifiedlld/ELF/LinkerScript.cpp
The file was modifiedlld/ELF/Writer.cpp
The file was addedlld/test/ELF/linkerscript/section-align2.test
The file was modifiedlld/test/ELF/linkerscript/lma-align.test
Commit de0dda54d38137d0714c279a540074fe73822b8b by maskray
[ELF] Warn changed output section address

When the output section address (addrExpr) is specified, GNU ld warns if
sh_addr is different. This patch implements the warning.

Note, LinkerScript::assignAddresses can be called more than once. We
need to record the changed section addresses, and only report the
warnings after the addresses are finalized.

Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D74741
The file was modifiedlld/ELF/LinkerScript.cpp
The file was modifiedlld/ELF/Writer.cpp
The file was modifiedlld/ELF/LinkerScript.h
The file was modifiedlld/test/ELF/linkerscript/lma-align.test
The file was modifiedlld/test/ELF/linkerscript/section-align2.test
Commit c47e0e2d37d32ec56c760f1a2c9740d69c370b57 by Jonas Devlieghere
[lldb-vscode] Use libOption with tablegen to parse command line options.

This change will bring lldb-vscode in line with how several other llvm
tools process command line arguments and make it easier to add future
options.

Differential revision: https://reviews.llvm.org/D74798
The file was modifiedlldb/test/Shell/helper/toolchain.py
The file was addedlldb/tools/lldb-vscode/Options.td
The file was addedlldb/test/Shell/VSCode/TestOptions.test
The file was modifiedlldb/tools/lldb-vscode/CMakeLists.txt
The file was modifiedlldb/tools/lldb-vscode/lldb-vscode.cpp
Commit dbd7281aa775a0e23c43a02583593900cd4c05be by maskray
[ELF] Shuffle .init_array/.fini_array with --shuffle-sections=

Useful for detecting static initialization order fiasco.

Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D74887
The file was modifiedlld/ELF/Writer.cpp
The file was addedlld/test/ELF/shuffle-sections-init-fini.s
Commit 42ec6fdce92090c02a10506fbdb2257fdbc2d1fd by llvm-dev
[TargetLowering] Apply basic shift combines before recursive SimplifyDemandedBits calls.

Minor refactor/cleanup before we begin adding non-uniform support.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit 043ed2e22ac442c2116f5df6367d3889ea0b9de1 by arsenm2
AMDGPU/GlobalISel: Fix xnor matching

We should try the generated matchers before the manual selection. This
means the patterns are now handling the common cases, but the manual
selection code is not yet dead. It's still handling the non-s32/s64
cases (like v2s16 and v2s32). Currently tablegen doesn't have a nice
way to have a single pattern that covers multiple types.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
Commit 6a479220b5e8b25ec3ffe193c463cb3fdaac0e06 by arsenm2
AMDGPU/GlobalISel: Commit test changes I forgot to squash

These should have been in ac7abe0ba9ae4c6a2248cc3ef4e4fe7e6d270105
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
Commit cab39e4b8c826ec5dfebe17a18137272022e64ac by jay.foad
GlobalISel: Fix narrowing of (G_ASHR i64:x, 32)

Reviewers: arsenm

Subscribers: jvesely, wdng, nhaehnle, rovka, hiraditya, volkan, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74950
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir
Commit 9fff6e823cf79075d1f386e1e875b73405368620 by mcinally
[AArch64][SVE] Add +fullfp16 to sve-vector-splat.ll

Add +fullfp16 to sve-vector-splat.ll so we can test folding of immediates into moves.

This attribute can go away later when SVE has a full set of fp16 patterns in place.

Differential Revision: https://reviews.llvm.org/D74965
The file was modifiedllvm/test/CodeGen/AArch64/sve-vector-splat.ll
Commit 134bab7cd5679673d6807595ae77b5bc0c3b83c2 by flo
[DSE,MSSA] Add debug counter.

Can be used like
-debug-counter=dse-memoryssa-skip=10,dse-memoryssa-counter-count=20

Reviewers: dmgreen, rnk, efriedma, bryant, asbirlea

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D72147
The file was modifiedllvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
The file was addedllvm/test/Transforms/DeadStoreElimination/MSSA/debug-counter.ll
Commit 23444edf30ba00ccefa3a582ac7ddc29774e9da5 by yitzhakm
[AST matchers] Add basic matchers for googletest EXPECT/ASSERT calls.

Summary:
This revision adds matchers that match calls to the gtest EXPECT and ASSERT
macros almost like function calls. The matchers are placed in separate files
(GtestMatchers...), because they are specific to the gtest library.

Reviewers: gribozavr2

Subscribers: mgorny, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D74840
The file was addedclang/include/clang/ASTMatchers/GtestMatchers.h
The file was modifiedclang/lib/ASTMatchers/CMakeLists.txt
The file was addedclang/lib/ASTMatchers/GtestMatchers.cpp
The file was addedclang/unittests/ASTMatchers/GtestMatchersTest.cpp
The file was modifiedclang/unittests/ASTMatchers/CMakeLists.txt
Commit fc4455891c00bfa16c85d0cebe6158fafe11667d by spatel
[VectorCombine] refactor matching code to reduce duplication; NFC

cmp/binop were already diverging even though they are largely
the same logic.
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
Commit db9c40f5624e6d55e0cbafe3f3980a7223e197c4 by danilo.carvalho.grael
[AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations

Summary:
Add intrinsics for the following operations:
- eor3, bcax
- bsl, bsl1n, bsl2n, nbsl

Fix MC tests for bsl instructions.

Reviewers: kmclaughlin, c-rhodes, sdesmalen, efriedma, rengolin

Reviewed By: efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74785
The file was modifiedllvm/test/MC/AArch64/SVE2/nbsl-diagnostics.s
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/test/MC/AArch64/SVE2/bsl-diagnostics.s
The file was modifiedllvm/test/MC/AArch64/SVE2/bsl2n-diagnostics.s
The file was addedllvm/test/CodeGen/AArch64/sve2-bitwise-ternary.ll
The file was modifiedllvm/test/MC/AArch64/SVE2/bsl1n-diagnostics.s
Commit 60023e347116e5004295e8c7f2f09cc1855d4d84 by arsenm2
AMDGPU: Use default operand for VOP3P clamp

We don't use this, and matching from the def doesn't make much sense.

There are multiple tablegen bugs with default operand
handling. undef_tied_input should work to handle the vdst_in
correctly, but this breaks the operand register class constraint which
it should be able to infer.
The file was modifiedllvm/lib/Target/AMDGPU/VOP3PInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
Commit 41bd9ead35f60823c59367efe4f3d5ade87e756d by paulsson
[SystemZ]  Return scalarized costs for vector instructions on older archs.

A cost query for a vector instruction should return a cost even without
target vector support, and not trigger an assert.

VectorCombine does this with an input containing source code vectors.

Review: Ulrich Weigand
The file was addedllvm/test/Analysis/CostModel/SystemZ/oldarch-vectors.ll
The file was modifiedllvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
Commit 8c70a2597f53457efc8eb2798c1d1056bb105ec3 by llvmgnsyncbot
[gn build] Port 23444edf30b
The file was modifiedllvm/utils/gn/secondary/clang/unittests/ASTMatchers/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang/lib/ASTMatchers/BUILD.gn
Commit a8db806d52ce02ddca179b811da164023316d4b9 by nikita.ppv
[SimplifyLibCalls][IRBuilder] Accept any IRBuilder in SimplifyLibCalls

This changes the SimplifyLibCalls utility to accept an IRBuilderBase,
which allows us to pass through the IRBuilder used by InstCombine.
This will ensure that new instructions get added to the worklist.
The annotated test-case drops from 4 to 2 InstCombine iterations thanks
to this.

To achieve this, I'm adding an IRBuilderBase::OperandBundlesGuard,
which is basically the same as the existing InsertPointGuard and
FastMathFlagsGuard, but for operand bundles. Also add a
setDefaultOperandBundles() method so these can be set outside the
constructor.

Differential Revision: https://reviews.llvm.org/D74792
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
The file was modifiedllvm/include/llvm/IR/IRBuilder.h
The file was modifiedllvm/test/Transforms/InstCombine/simplify-libcalls.ll
Commit c90ea87cfd71f8da05f2e684d3cf139f9773c15d by nikita.ppv
[X86] Fix SDLoc initialization

Fixes -Wparentheses warning, in this case indicating a genuine
bug.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 98f5268a7292c2996e2f718382e2d5404eb5d112 by flo
[VectorUtils] Move ToVectorTy to VectorUtils.h (NFC).

ToVectorTy is defined and used in multiple places. Hoist it to
VectorUtils.h to avoid duplication and improve re-usability.

Reviewers: rengolin, hsaito, Ayal, gilr, fpetrogalli

Reviewed By: fpetrogalli

Differential Revision: https://reviews.llvm.org/D74959
The file was modifiedllvm/lib/Transforms/Utils/InjectTLIMappings.cpp
The file was modifiedllvm/include/llvm/Analysis/VectorUtils.h
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit deb0a8bfc4923356beaa47b960d14b0c46a14721 by flo
[DSE,MSSA] Dbg counters required assertions. Mark test accordingly.
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/debug-counter.ll
Commit 656dff9af48bd242fc0f8a20cf50c6d0921df052 by nikita.ppv
[InstCombine] Use replaceOperand() in more places

Followup to D73919 with another batch of replacements of
setOperand() -> replaceOperand(), to make sure the old
operand gets DCEd right away.

Differential Revision: https://reviews.llvm.org/D74932
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp