Started 1 yr 9 mo ago
Took 12 hr on green-dragon-13

Success Build #4172 (Jul 19, 2019 8:17:58 AM)

  • : 366586
  • : 366546
  • : 366588
  • : 366573
  • : 364589
  • : 366594
  • : 366290
  • : 366577
  • : 366510
  1. [libc++] Use _EnableIf instead of std::enable_if in deduction guides for map and set (detail/ViewSVN)
    by ldionne
  2. [libc++] Integrate the PSTL into libc++

    This commit allows specifying LIBCXX_ENABLE_PARALLEL_ALGORITHMS when
    configuring libc++ in CMake. When that option is enabled, libc++ will
    assume that the PSTL can be found somewhere on the CMake module path,
    and it will provide the C++17 parallel algorithms based on the PSTL
    (that is assumed to be available).

    The commit also adds support for running the PSTL tests as part of
    the libc++ test suite.

    Reviewers: rodgert, EricWF

    Subscribers: mgorny, christof, jkorous, dexonsmith, libcxx-commits, mclow.lists, EricWF

    Tags: #libc

    Differential Revision: (detail/ViewSVN)
    by ldionne
  3. Fix asan infinite loop on undefined symbol

    Fix llvm#39641

    Recommit of r366413

    Differential Revision: (detail/ViewSVN)
    by serge_sans_paille
  4. AMDGPU: Attempt to fix bot error

    Manually remove file name from check line, since it somehow ends
    up being different on an msvc bot. (detail/ViewSVN)
    by arsenm
  5. AMDGPU/GlobalISel: Selection for fminnum/fmaxnum

    v2f16 case doesn't work yet because the VOP3P complex patterns haven't
    been ported yet. (detail/ViewSVN)
    by arsenm
  6. AMDGPU/GlobalISel: Support arguments with multiple registers

    Handles structs used directly in argument lists. (detail/ViewSVN)
    by arsenm
  7. AMDGPU/GlobalISel: Rewrite lowerFormalArguments

    This should now handle everything except structs passed as multiple

    I think most of the packing logic should be handled by
    handleAssignments, but I'm unclear on what the contract is for
    multiple registers. This is copying how x86 handles this.

    This does change the behavior of the test_sgpr_alignment0 amdgpu_vs
    test. I don't think shader arguments should try to follow the
    alignment, and registers need to be repacked. I also don't think it
    matters, since I think the pointers are packed to the beginning of the
    argument list anyway. (detail/ViewSVN)
    by arsenm
  8. [libc++] Add missing %link_flags to .sh.cpp test

    Without the link flags, the test always fails on Linux. For some reason,
    however, it works on Darwin -- which is why it wasn't caught at first. (detail/ViewSVN)
    by ldionne
  9. AMDGPU: Decompose all values to 32-bit pieces for calling conventions

    This is the more natural lowering, and presents more opportunities to
    reduce 64-bit ops to 32-bit.

    This should also help avoid issues graphics shaders have had with
    64-bit values, and simplify argument lowering in globalisel. (detail/ViewSVN)
    by arsenm
  10. [clangd] Provide a way to publish highlightings in non-racy manner

    By exposing a callback that can guard code publishing results of
    'onMainAST' callback in the same manner we guard diagnostics.

    Reviewers: sammccall

    Reviewed By: sammccall

    Subscribers: javed.absar, MaskRay, jkorous, arphaman, kadircet, hokein, jvikstrom, cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by ibiryukov
  11. gn build: Set +x on (detail/ViewSVN)
    by nico
  12. [clangd] Disable background-index on lit-tests by default

    Since background-index can perform disk writes, we don't want to turn
    it on tests that won't clear it.

    Reviewers: sammccall

    Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits

    Tags: #clang

    Differential Revision: (detail/ViewSVN)
    by kadircet
  13. DAG: Handle dbg_value for arguments split into multiple subregs

    This was handled previously for arguments split due to not fitting in
    an MVT. This was dropping the register for argument registers split
    due to TLI::getRegisterTypeForCallingConv. (detail/ViewSVN)
    by arsenm
  14. lld-link: Demangle symbols from archives in diagnostics

    Also add test coverage for thin archives (which are the only way I could
    come up with to test at least some of the diagnostic changes).

    Differential Revision: (detail/ViewSVN)
    by nico
  15. [NFC] include cstdint/string prior to using uint8_t/string

    Summary: include proper header prior to use of uint8_t typedef
    and std::string.

    Subscribers: llvm-commits

    Reviewers: cherry

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by thanm
  16. [AMDGPU][MC] Corrected parsing of branch offsets

    See bug 40820:

    Reviewers: artem.tamazov, arsenm

    Differential Revision: (detail/ViewSVN)
    by dpreobra
  17. [MachineCSE][MachinePRE] Avoid hoisting code from code regions into hot BBs.

    Current PRE hoists common computations into
    CMBB = DT->findNearestCommonDominator(MBB, MBB1).
    However, if CMBB is in a hot loop body, we might get performance

    Differential Revision: (detail/ViewSVN)
    by lkail
  18. [X86] for split stack, not save/restore nested arg if unused

    For split-stack, if the nested argument (i.e. R10) is not used, no need to save/restore it in the prologue.

    Reviewers: thanm

    Reviewed By: thanm

    Subscribers: mstorsjo, llvm-commits

    Tags: #llvm

    Differential Revision: (detail/ViewSVN)
    by thanm
  19. [Clangd] Fixed ExtractVariable test (detail/ViewSVN)
    by sureyeaah
  20. [NFC][InstCombine] Tests for 'rem' formation from sub-of-mul-by-'div' (PR42673) (detail/ViewSVN)
    by lebedevri
  21. [NFC][InstCombine] Redundant masking before left-shift: tests with assume

    If the legality check is `(shiftNbits-maskNbits) s>= 0`,
    then we can simplify it to `shiftNbits u>= maskNbits`,
    which is easier to check for.

    However, currently switching the `dropRedundantMaskingOfLeftShiftInput()`
    to `SimplifyICmpInst()` does not catch these cases and regresses
    currently-handled cases, so i'll leave it as is for now. (detail/ViewSVN)
    by lebedevri
  22. Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI. (detail/ViewSVN)
    by rksimon

Started by upstream project "clang-stage1-configure-RA" build number 58,123
originally caused by:

Started by upstream project "clang-stage1-configure-RA" build number 58,124
originally caused by:

Started by upstream project "clang-stage1-configure-RA" build number 58,125
originally caused by:

Started by upstream project "clang-stage1-configure-RA" build number 58,121
originally caused by:

Started by upstream project "clang-stage1-configure-RA" build number 58,126
originally caused by:

This run spent:

  • 3 hr 42 min waiting;
  • 12 hr build duration;
  • 15 hr total from scheduled to completion.
LLVM/Clang Warnings: 12 warnings.