SuccessChanges

Summary

  1. [lldb][NFC] Remove name parameter from CreateFunctionTemplateDecl (details)
  2. [LLD][ELF] - Do not produce an invalid dynamic relocation order with --shuffle-sections. (details)
  3. [NFC] Run update script on test (details)
  4. [DemandedBits] Reorder addition test checks. NFC. (details)
  5. [DemandedBits] Improve accuracy of Add propagator (details)
  6. [llvm-readobj/elf] - Refine the warning about the broken PT_DYNAMIC segment. (details)
  7. [InstCombine] reduce code duplication; NFC (details)
  8. [InstCombine] add tests for sdiv-of-abs; NFC (details)
  9. [InstCombine] fold abs(X)/X to cmp+select (details)
  10. [gn build] Port c1f6ce0c732 (details)
  11. [RISCV] Indirect branch generation in position independent code (details)
  12. [RISCV] Enable the use of the old mucounteren name (details)
Commit 7e6c437fb413eb7ae102e8db869bb55a748411ff by Raphael Isemann
[lldb][NFC] Remove name parameter from CreateFunctionTemplateDecl

It's unused and not documented.
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp (diff)
The file was modifiedlldb/unittests/Symbol/TestTypeSystemClang.cpp (diff)
The file was modifiedlldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h (diff)
The file was modifiedlldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp (diff)
Commit c135a68d426fd69d26454658bfa62102993f12a7 by grimar
[LLD][ELF] - Do not produce an invalid dynamic relocation order with --shuffle-sections.

Normally (when not on android with android relocation packing enabled),
we put IRelative relocations to ".rel[a].dyn", after other relocations,
to ensure that IRelatives are processed last by the dynamic loader.

To achieve that we add the `in.relaIplt` after the `part.relaDyn`:
https://github.com/llvm/llvm-project/blob/master/lld/ELF/Writer.cpp#L540

The problem is that `--shuffle-sections` might break the sections order.
This patch fixes it.

Fixes https://bugs.llvm.org/show_bug.cgi?id=47056.

Differential revision: https://reviews.llvm.org/D85651
The file was modifiedlld/ELF/Writer.cpp (diff)
The file was modifiedlld/test/ELF/gnu-ifunc-plt.s (diff)
Commit 613d8f29538ee43137a77dfd0d6464c65b328b68 by sam.parker
[NFC] Run update script on test

Update IndVarSimplify/no-iv-rewrite.ll
The file was modifiedllvm/test/Transforms/IndVarSimplify/no-iv-rewrite.ll (diff)
Commit 79d9e2cd93a3ff7b448f40caf50dbfd3516f7c0d by llvm-dev
[DemandedBits] Reorder addition test checks. NFC.

As suggested on D72423 we should try to keep the same order as the original IR
The file was modifiedllvm/test/Analysis/DemandedBits/add.ll (diff)
Commit c1f6ce0c7322d47f1bb90169585fa54232231ede by llvm-dev
[DemandedBits] Improve accuracy of Add propagator

The current demand propagator for addition will mark all input bits at and right of the alive output bit as alive. But carry won't propagate beyond a bit for which both operands are zero (or one/zero in the case of subtraction) so a more accurate answer is possible given known bits.

I derived a propagator by working through truth tables and using a bit-reversed addition to make demand ripple to the right, but I'm not sure how to make a convincing argument for its correctness in the comments yet. Nevertheless, here's a minimal implementation and test to get feedback.

This would help in a situation where, for example, four bytes (<128) packed into an int are added with four others SIMD-style but only one of the four results is actually read.

Known A:     0_______0_______0_______0_______
Known B:     0_______0_______0_______0_______
AOut:        00000000001000000000000000000000
AB, current: 00000000001111111111111111111111
AB, patch:   00000000001111111000000000000000

Committed on behalf of: @rrika (Erika)

Differential Revision: https://reviews.llvm.org/D72423
The file was modifiedllvm/lib/Analysis/DemandedBits.cpp (diff)
The file was modifiedllvm/include/llvm/Analysis/DemandedBits.h (diff)
The file was modifiedllvm/test/Analysis/DemandedBits/add.ll (diff)
The file was addedllvm/unittests/IR/DemandedBitsTest.cpp
The file was modifiedllvm/unittests/IR/CMakeLists.txt (diff)
The file was modifiedllvm/unittests/Support/KnownBitsTest.cpp (diff)
The file was addedllvm/unittests/Support/KnownBitsTest.h
Commit 6567f822160ea7c4d13a7e3358883eafc61af337 by grimar
[llvm-readobj/elf] - Refine the warning about the broken PT_DYNAMIC segment.

Splitted out from D85519.

Currently we report "PT_DYNAMIC segment offset + size exceeds the size of the file",
this changes it to
"PT_DYNAMIC segment offset (0x1234) + file size (0x5678) exceeds the size of the file (0x68ab)"

Differential revision: https://reviews.llvm.org/D85654
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp (diff)
The file was modifiedllvm/test/tools/llvm-readobj/ELF/malformed-pt-dynamic.test (diff)
The file was modifiedllvm/test/Object/invalid.test (diff)
Commit 6cd4a6f6b27eea40dbddccb21c206fb4d4354c53 by spatel
[InstCombine] reduce code duplication; NFC
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp (diff)
Commit 61512ddd2d57fc33464bda477dab04829266faa1 by spatel
[InstCombine] add tests for sdiv-of-abs; NFC
The file was modifiedllvm/test/Transforms/InstCombine/sdiv-canonicalize.ll (diff)
Commit e6b6787d01e9ea6338b5b51c6e3ba1b903876b3a by spatel
[InstCombine] fold abs(X)/X to cmp+select

The backend can convert the select-of-constants to
bit-hack shift+logic if desirable.

https://alive2.llvm.org/ce/z/pgJT6E

  define i8 @src(i8 %x) {
  %0:
    %a = abs i8 %x, 1
    %d = sdiv i8 %x, %a
    ret i8 %d
  }
  =>
  define i8 @tgt(i8 %x) {
  %0:
    %cond = icmp sgt i8 %x, 255
    %r = select i1 %cond, i8 1, i8 255
    ret i8 %r
  }
  Transformation seems to be correct!
The file was modifiedllvm/test/Transforms/InstCombine/sdiv-canonicalize.ll (diff)
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp (diff)
Commit e0eb4f204a0ef48cff8fedc0cbc5be2c71fe2afe by llvmgnsyncbot
[gn build] Port c1f6ce0c732
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn (diff)
Commit 5f9ecc5d857fa5d95f6ea36153be19db40576f8a by selliott
[RISCV] Indirect branch generation in position independent code

This fixes the "Unable to insert indirect branch" fatal error sometimes
seen when generating position-independent code.

Patch by msizanoen1

Reviewed By: jrtc27

Differential Revision: https://reviews.llvm.org/D84833
The file was modifiedllvm/test/CodeGen/RISCV/branch-relaxation.ll (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.td (diff)
Commit 3f7068ad986d7f44f47faec78597a5e62b07b20b by selliott
[RISCV] Enable the use of the old mucounteren name

The RISC-V Privileged Specification 1.11 defines `mcountinhibit`, which
has the same numeric CSR value as `mucounteren` from 1.09.1. This patch
enables the use of the old `mucounteren` name.

Patch by Yuichi Sugiyama.

Reviewed By: lenary, jrtc27, pzheng

Differential Revision: https://reviews.llvm.org/D85067
The file was modifiedllvm/test/MC/RISCV/machine-csr-names.s (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVSystemOperands.td (diff)