SuccessChanges

Summary

  1. [InstCombine] add tests for fneg+fabs; NFC (details)
  2. [InstCombine] fold fabs of select with negated operand (details)
  3. [llvm-readobj/elf] - Refine testing of broken Android's packed relocation sections. (details)
  4. AMDGPU/GlobalISel: Fix selection of s1/s16 G_[F]CONSTANT (details)
  5. AMDGPU/GlobalISel: Select llvm.amdgcn.groupstaticsize (details)
  6. [X86][AVX] lowerShuffleWithVTRUNC - pull out TRUNCATE/VTRUNC creation into helper code. NFCI. (details)
Commit e0aa335334813b15d2106ccdcf4930d72aa33772 by spatel
[InstCombine] add tests for fneg+fabs; NFC
The file was modifiedllvm/test/Transforms/InstCombine/fabs.ll (diff)
Commit 139da9c4d74391cd9d12600650ef95d5d68d8b59 by spatel
[InstCombine] fold fabs of select with negated operand

This is the FP example shown in:
https://bugs.llvm.org/PR39474
The file was modifiedllvm/test/Transforms/InstCombine/fabs.ll (diff)
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp (diff)
Commit 740332b6cce3e59dca4e50d3e2fd0d008f5e9529 by grimar
[llvm-readobj/elf] - Refine testing of broken Android's packed relocation sections.

This uses modern `split-file` tool to merge 5 `packed-relocs-error*.s` tests to a
new `packed-relocs-errors.s` and adds testing for GNU style.

Differential revision: https://reviews.llvm.org/D85835
The file was removedllvm/test/tools/llvm-readobj/ELF/packed-relocs-error3.s
The file was removedllvm/test/tools/llvm-readobj/ELF/packed-relocs-error4.s
The file was removedllvm/test/tools/llvm-readobj/ELF/packed-relocs-error2.s
The file was removedllvm/test/tools/llvm-readobj/ELF/packed-relocs-error1.s
The file was removedllvm/test/tools/llvm-readobj/ELF/packed-relocs-error5.s
The file was addedllvm/test/tools/llvm-readobj/ELF/packed-relocs-errors.s
Commit 3ba7777b94d887af594ba8d6c1378166bd361a20 by Matthew.Arsenault
AMDGPU/GlobalISel: Fix selection of s1/s16 G_[F]CONSTANT

The code to determine the value size was overcomplicated and only
correct in the case where the result register already had a register
class assigned. We can always take the size directly from the
register's type.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fconstant.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir (diff)
Commit 2f5f5febf3e4fa9bc80e8a8f63a99d3e6813c499 by Matthew.Arsenault
AMDGPU/GlobalISel: Select llvm.amdgcn.groupstaticsize

Previously, it would successfully select and assert if not HSA or PAL
when expanding the pseudoinstruction. We don't need the
pseudoinstruction anymore since we know the total size after
legalization.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h (diff)
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.groupstaticsize.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll (diff)
Commit d5621b83a58c1faaa0e413ac7c4f0ca8811d0c61 by llvm-dev
[X86][AVX] lowerShuffleWithVTRUNC - pull out TRUNCATE/VTRUNC creation into helper code. NFCI.

Prep work toward adding v16i16/v32i8 support for lowerShuffleWithVTRUNC and improving lowerShuffleWithVPMOV.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp (diff)