SuccessChanges

Summary

  1. [RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move (details)
  2. [RISC-V] Mark C_MV as a move instruction (details)
  3. [RISC-V] fmv.s/fmv.d should be as cheap as a move (details)
  4. [lld][ELF][test] Expand testing of symbols in mergeable sections (details)
  5. Follow up of rGca243b07276a: fixed a typo. NFC. (details)
  6. [AArch64][SVE] Add missing debug info for ACLE types. (details)
  7. [SVE] Fallback to default expansion when lowering SIGN_EXTEN_INREG from non-byte based source. (details)
  8. [NFC][ValueTracking] Fix typo in test (details)
  9. [AArch64] Optimize instruction selection for certain vector shuffles (details)
Commit 2259ce8c9116e2fd057332a1ede08396e8d64d30 by Alexander.Richardson
[RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move

The isTriviallyRematerializable hook is only called for instructions that are
tagged as isAsCheapAsAMove. Since ADDI 0 is used for "mv" it should definitely
be marked with "isAsCheapAsAMove". This change avoids one stack spill in most of
the atomic-rmw.ll tests functions. It also avoids stack spills in two of our
out-of-tree CHERI tests.
ORI/XORI with zero may or may not be the same as a move micro-architecturally,
but since we are already doing it for register == x0, we might as well
do the same if the immediate is zero.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D86480
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp (diff)
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/vararg.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/atomic-rmw.ll (diff)
Commit a11eeb4d4a99f61c2626ce2c0d44175a9eaa2c59 by Alexander.Richardson
[RISC-V] Mark C_MV as a move instruction

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D86517
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoC.td (diff)
Commit 5ba4d0365b36de440d82b4672ccd41a5a7dd4592 by Alexander.Richardson
[RISC-V] fmv.s/fmv.d should be as cheap as a move

Since the canonical floatig-point move is fsgnj rd, rs, rs, we should
handle this case in RISCVInstrInfo::isAsCheapAsAMove().

Reviewed By: lenary

Differential Revision: https://reviews.llvm.org/D86518
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp (diff)
Commit d2385f6d2f1bea4e4913ae3bc3948590e8d9f6c3 by james.henderson
[lld][ELF][test] Expand testing of symbols in mergeable sections

Whilst reviewing some internal testing, I noticed a couple of holes in
coverage of mergeable sections containing symbols. This patch addresses
these holes:
1) Show that mid-piece symbols have their values updated properly when
   pieces are merged.
2) Show the behaviour of symbols in mergeable pieces when --gc-sections
   is enabled.

Reviewed by: grimar, MaskRay

Differential Revision: https://reviews.llvm.org/D86543
The file was addedlld/test/ELF/merge-sym-gc.s
The file was modifiedlld/test/ELF/merge-sym.s (diff)
Commit ff6dbb231923de7756f3370fa490aed3ce35787d by sjoerd.meijer
Follow up of rGca243b07276a: fixed a typo. NFC.
The file was modifiedllvm/docs/LangRef.rst (diff)
Commit 4e9b66de3f046c1e97b34c938b0920fa6401f40c by sander.desmalen
[AArch64][SVE] Add missing debug info for ACLE types.

This patch adds type information for SVE ACLE vector types,
by describing them as vectors, with a lower bound of 0, and
an upper bound described by a DWARF expression using the
AArch64 Vector Granule register (VG), which contains the
runtime multiple of 64bit granules in an SVE vector.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D86101
The file was modifiedclang/test/CodeGen/aarch64-sve.c (diff)
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp (diff)
The file was addedclang/test/CodeGen/aarch64-debug-sve-vectorx2-types.c
The file was addedclang/test/CodeGen/aarch64-debug-sve-vectorx3-types.c
The file was addedclang/test/CodeGen/aarch64-debug-sve-vectorx4-types.c
The file was addedllvm/test/DebugInfo/AArch64/dbg-sve-types.ll
The file was addedclang/test/CodeGen/aarch64-debug-sve-vector-types.c
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp (diff)
Commit 81337c915f150f0fbe729a380c7ff32e917859ba by paul.walker
[SVE] Fallback to default expansion when lowering SIGN_EXTEN_INREG from non-byte based source.

Differential Revision: https://reviews.llvm.org/D86394
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll (diff)
Commit 8191603dc42a1e2631996aae7d24569fbd90c52c by Vitaly Buka
[NFC][ValueTracking] Fix typo in test
The file was modifiedllvm/unittests/Analysis/ValueTrackingTest.cpp (diff)
Commit 23d5e93f342e168b59838476abc0e03853609617 by mikhail.maltsev
[AArch64] Optimize instruction selection for certain vector shuffles

This patch adds code to recognize vector shuffles which can be
represented as VDUP (splat) of a vector lane with of a different
(wider) type than the original vector lane type.

For example:
    shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
is essentially:
    shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> <i32 0, i32 0>

Such patterns are generated by the SelectionDAG machinery in some cases
(see DAGCombiner::visitBITCAST in DAGCombiner.cpp, the "Remove double
bitcasts from shuffles" part).

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D86225
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll (diff)
The file was addedllvm/test/CodeGen/AArch64/neon-wide-splat.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-neon-2velem.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vext_reverse.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/neon-extract.ll (diff)