SuccessChanges

Summary

  1. [RegisterScavenging] Delete dead function unprocess(). (details)
  2. [Hexagon] Emit better 32-bit multiplication sequence for HVXv62+ (details)
  3. GlobalISel: Add and_trivial_mask to all_combines (details)
  4. AMDGPU: Use caller subtarget, not intrinsic declaration (details)
  5. [NFC][ValueTracking] Add OffsetZero into findAllocaForValue (details)
  6. [StackSafety] Ignore allocas with partial lifetime markers (details)
  7. MIR: Infer not-SSA for subregister defs (details)
  8. AArch64/GlobalISel: Fix missing function begin marker in test (details)
  9. GlobalISel: Implement known bits for min/max (details)
  10. [OpenMP] Fix a failing test after D85214 (details)
Commit 8d21985a752416823a803d74f9265c4e148003a0 by efriedma
[RegisterScavenging] Delete dead function unprocess().
The file was modifiedllvm/lib/CodeGen/RegisterScavenging.cpp (diff)
The file was modifiedllvm/include/llvm/CodeGen/RegisterScavenging.h (diff)
Commit 4ef9275b9b4875a131898ead943e17389e797b12 by kparzysz
[Hexagon] Emit better 32-bit multiplication sequence for HVXv62+
The file was modifiedllvm/test/CodeGen/Hexagon/autohvx/arith.ll (diff)
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp (diff)
Commit 201f770f16e8ea89e92a1edd79c41559f4031187 by Matthew.Arsenault
GlobalISel: Add and_trivial_mask to all_combines

Also make up a new category of combines.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll (diff)
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll (diff)
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll (diff)
Commit a1bc37c9e54e0163bc6ccb7a438a68047310ccff by Matthew.Arsenault
AMDGPU: Use caller subtarget, not intrinsic declaration

Intrinsic declarations use the default subtarget, but this should be
using the subtarget for the calling function. I haven't been able to
come up with a case where it matters though.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.h (diff)
Commit a6927c8621269a3c00c0ac83ec57b66f28c78863 by Vitaly Buka
[NFC][ValueTracking] Add OffsetZero into findAllocaForValue

For StackLifetime after finding alloca we need to check that
values ponting to the begining of alloca.

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D86692
The file was modifiedllvm/unittests/Analysis/ValueTrackingTest.cpp (diff)
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp (diff)
The file was modifiedllvm/include/llvm/Analysis/ValueTracking.h (diff)
Commit a40660551ea1ed01f69406d81e39efe73d86cbec by Vitaly Buka
[StackSafety] Ignore allocas with partial lifetime markers

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D86672
The file was modifiedllvm/test/Transforms/SafeStack/X86/layout-frag.ll (diff)
The file was modifiedllvm/lib/Analysis/StackLifetime.cpp (diff)
The file was modifiedllvm/test/Analysis/StackSafetyAnalysis/lifetime.ll (diff)
Commit ee679638d75ca9a7f7d7be728fa069606dcc8ec7 by Matthew.Arsenault
MIR: Infer not-SSA for subregister defs

It's possible to have a single virtual register def with a subreg
index that would pass the previous check, but it's not possible to
have a subregister def in SSA.

This is in preparation for adding stricter checks for SSA MIR.
The file was modifiedllvm/include/llvm/CodeGen/MachineRegisterInfo.h (diff)
The file was modifiedllvm/lib/CodeGen/MIRParser/MIRParser.cpp (diff)
The file was addedllvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir
Commit 0034e00da0e5448b03e15eee0279736dab29c944 by Matthew.Arsenault
AArch64/GlobalISel: Fix missing function begin marker in test
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-and-trivial-mask.mir (diff)
Commit abc99ab5725636c17fa9c9ced0269f92bf5398cb by Matthew.Arsenault
GlobalISel: Implement known bits for min/max
The file was modifiedllvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp (diff)
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir (diff)
Commit a1ac047b3453f205eacc36adc787ac31b952a502 by Saiyedul.Islam
[OpenMP] Fix a failing test after D85214

Removed version 45 testing from a failing test for now.
The file was modifiedclang/test/OpenMP/declare_target_ast_print.cpp (diff)