SuccessChanges

Summary

  1. AMDGPU: Convert test to MIR (details)
  2. AMDGPU: Check some offsets in test (details)
  3. PowerPC: Switch test to generated checks (details)
  4. GlobalISel: Artifact combine unmerge of unmerge (details)
  5. Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain" (details)
  6. GlobalISel: Implement computeKnownBits for G_UNMERGE_VALUES (details)
  7. GlobalISel: Implement computeNumSignBits for G_SEXTLOAD/G_ZEXTLOAD (details)
Commit 4a9a4885aef9529788cc32999f998254a3730179 by Matthew.Arsenault
AMDGPU: Convert test to MIR

Currently the dbg_value ends up in the relaxed branch block. A future
commit will push the dbg_value out of this block, and I'm not sure how
to coax the IR into producing the same MIR at the relevant point.
The file was removedllvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.ll
The file was addedllvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir
Commit 7f5b4eaae4892539f2c4c1e32c61b297363c7341 by Matthew.Arsenault
AMDGPU: Check some offsets in test

This will make updating the checks easier in a future change.
The file was modifiedllvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll (diff)
Commit 0f42d185346a5c383cf4d30e02c68b39440ed9dd by Matthew.Arsenault
PowerPC: Switch test to generated checks
The file was modifiedllvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll (diff)
The file was modifiedllvm/test/CodeGen/PowerPC/vsx-args.ll (diff)
Commit 18bbd9f15eb031c5c7e58ebe0692f87fa8d5954f by Matthew.Arsenault
GlobalISel: Artifact combine unmerge of unmerge

Unmerges have the same fundamental problem as G_TRUNC, and G_TRUNC
could be implemented in terms of G_UNMERGE_VALUES. Reducing the number
of elements in unmerge results ends up producing the original unmerge
type profile, so the artifact combiner needs to eliminate the
intermediate illegal registers. This avoids infinite looping in the
legalizer in a future change.

Assuming an unmerge has each result unmerged the same way, this ends
up producing a new unmerge of the source for every definition. I'm not
sure if the artifact combiner should either insert temporary merges
here and erase the original merge, or if the combiner should look at
uses from defs rather than defs from uses for unmerges.

In a few cases this regresses from using 16-bit shifts for 8-bit
values to using 32-bit shifts, but I think these can be legalized
later (the other legalization rules don't try very hard to use 16-bit
shifts either).
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir (diff)
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir (diff)
The file was modifiedllvm/lib/Target/Mips/MipsRegisterBankInfo.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir (diff)
Commit bc9a29b9ee6ade4894252b1470977142c32b4602 by paul.walker
Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain"

This reverts commit e9d9a612084b47fc4277523561d61e675370c854.

This patch was previously revert by 04879086b44348cad600a0a1ccbe1f7776cc3cf9
with the reapplication being done after breaking the assert used to
ensure SP is always 16-byte aligned, which is a requirement of the AAPCS.

For extra context the latest patch caused runtime failures when
building with "-march=armv8-a+sve -mllvm -aarch64-sve-vector-bits-min=256".
The file was modifiedllvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h (diff)
The file was removedllvm/test/CodeGen/AArch64/framelayout-fp-csr.ll
The file was removedllvm/test/CodeGen/AArch64/framelayout-frame-record.mir
The file was removedllvm/test/CodeGen/AArch64/framelayout-unaligned-fp.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp (diff)
Commit 92090e8bd80179ec780bb67e1e7d95eceefbdd56 by Matthew.Arsenault
GlobalISel: Implement computeKnownBits for G_UNMERGE_VALUES
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll (diff)
The file was modifiedllvm/include/llvm/Support/KnownBits.h (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll (diff)
The file was modifiedllvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp (diff)
The file was modifiedllvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll (diff)
Commit 9e7e1b2d4b13d0abb1e34feedfc004ae2b2dab3a by Matthew.Arsenault
GlobalISel: Implement computeNumSignBits for G_SEXTLOAD/G_ZEXTLOAD
The file was modifiedllvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir (diff)