SuccessChanges

Summary

  1. [ARM] Constant fold VMOVrh (details)
  2. [X86] Add 32-bit command lines to masked_store.ll and masked_load.ll (details)
  3. [X86] Stop reduceMaskedLoadToScalarLoad/reduceMaskedStoreToScalarStore from creating scalar i64 load/stores in 32-bit mode (details)
Commit 29bd8ea11091d996d166257e07bf2308651d284d by david.green
[ARM] Constant fold VMOVrh

This adds simple constant folding for VMOVrh, to constant fold fp16
constants to integer values. It can help especially with soft calling
conventions, but some of the results are not optimal as we end up
loading using a vldr. This will be improved in a follow up patch.

Differential Revision: https://reviews.llvm.org/D87789
The file was modifiedllvm/test/CodeGen/ARM/fp16-bitcast.ll (diff)
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/ARM/cmse-clear-float-hard.ll (diff)
Commit 9b1c98c0fbe2d7fdc22debd3e7d1fcf44952a0ce by craig.topper
[X86] Add 32-bit command lines to masked_store.ll and masked_load.ll
The file was modifiedllvm/test/CodeGen/X86/masked_load.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/masked_store.ll (diff)
Commit 4e8c028158b56d9c2142a62464e8e0686bde3584 by craig.topper
[X86] Stop reduceMaskedLoadToScalarLoad/reduceMaskedStoreToScalarStore from creating scalar i64 load/stores in 32-bit mode

If we emit a scalar i64 load/store it will get type legalized to two i32 load/stores.

Differential Revision: https://reviews.llvm.org/D87862
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/X86/masked_load.ll (diff)