Started 1 yr 6 mo ago
Took 3 hr 39 min on green-dragon-18

Success Build rL:366802 - C:366792 - #58186 (Jul 23, 2019 6:13:15 AM)

  • : 366802
  • : 366792
  • : 366805
  • : 364589
  • : 366740
  • : 366776
  • : 366698
  1. [NFC][ASAN] Add brackets around not command

    Under certain execution conditions, the `not` command binds to the command the
    output is piped to rather than the command piping the output. In this case, that
    flips the return code of the FileCheck invocation, causing a failure when
    FileCheck succeeds. (detail/ViewSVN)
    by lei
  2. [NFC][InstCombine] Fixup commutative/negative tests with icmp preds in @llvm.umul.with.overflow tests (detail/ViewSVN)
    by lebedevri
  3. [InstSimplify][NFC] Tests for skipping 'div-by-0' checks before inverted @llvm.umul.with.overflow

    It would be already handled by the non-inverted case if we were hoisting
    the `not` in InstCombine, but we don't (granted, we don't sink it
    in this case either), so this is a separate case. (detail/ViewSVN)
    by lebedevri
  4. [NFC][PhaseOredering][SimplifyCFG] Add more runlines to umul.with.overflow tests

    This way it will be more obvious that the problem is both
    in cost threshold and in hardcoded benefit check,
    plus will show how the instsimplify cleans this all in the end. (detail/ViewSVN)
    by lebedevri
  5. [TargetLowering] Add SimplifyMultipleUseDemandedBits

    This patch introduces the DAG version of SimplifyMultipleUseDemandedBits, which attempts to peek through ops (mainly and/or/xor so far) that don't contribute to the demandedbits/elts of a node - which means we can do this even in cases where we have multiple uses of an op, which normally requires us to demanded all bits/elts. The intention is to remove a similar instruction - SelectionDAG::GetDemandedBits - once SimplifyMultipleUseDemandedBits has matured.

    The InstCombine version of SimplifyMultipleUseDemandedBits can constant fold which I haven't added here yet, and so far I've only wired this up to some basic binops (and/or/xor/add/sub/mul) to demonstrate its use.

    We do see a couple of regressions that need to be addressed:

        AMDGPU unsigned dot product codegen retains an AND mask (for ZERO_EXTEND) that it previously removed (but otherwise the dotproduct codegen is a lot better).

        X86/AVX2 has poor handling of vector ANY_EXTEND/ANY_EXTEND_VECTOR_INREG - it prematurely gets converted to ZERO_EXTEND_VECTOR_INREG.

    The code owners have confirmed its ok for these cases to fixed up in future patches.

    Differential Revision: (detail/ViewSVN)
    by rksimon
  6. [RISCV] Re-enable rv32i-aliases-invalid.s test

    We were getting test failures on some builders, which pointed to @LINE
    being an undefined variable. I think that these failures should have
    been fixed by, so I'm re-enabling the
    test. (detail/ViewSVN)
    by lenary
  7. [Object/ELF.h] - Improve testing of the fields in ELFFile<ELFT>::sections().

    This eliminates a one error untested and
    also introduces a error for one more possible case
    which lead to crash previously.

    Differential revision: (detail/ViewSVN)
    by grimar

Started by an SCM change (5 times)

This run spent:

  • 1 hr 30 min waiting;
  • 3 hr 39 min build duration;
  • 5 hr 9 min total from scheduled to completion.
LLVM/Clang Warnings: 1 warning.
    Test Result (no failures)