Started 1 mo 7 days ago
Took 1 hr 24 min

Success Build #2886 (May 10, 2021 1:12:38 PM)

Changes
  1. [DebugInfo] UnwindTable::create() should not add empty rows to CFI unwind table (details)
  2. [NewPM] Hide pass manager debug logging behind -debug-pass-manager-verbose (details)
  3. Replace a remaining CRLF with LF. NFC. (details)
  4. [X86] Support AMX fast register allocation (details)
  5. Revert "[X86] Support AMX fast register allocation" (details)
  6. Fix build after 34a8a437b (details)
  7. [X86] Support AMX fast register allocation (details)
  8. [mlir] Debug print pattern before and after matchAndRewrite call (details)
  9. [VectorCombine] Simplify to scalar store if only one element updated (details)
  10. [libc++] Use Xcode's CMake if it's present (details)
  11. [X86] Improve costmodel for scalar byte swaps (details)
  12. Revert "[LICM] Hoist loads with invariant.group metadata" (details)
  13. [MLIR][NFC] Remove unused MLIRContext declaration (details)
  14. [MLIR] Add memref dialect dependency for affine fusion pass (details)
  15. [libc++] Move handling of the target triple to the DSL (details)
  16. [X86] combineHorizOpWithShuffle - generalize HOP(SHUFFLE(X),SHUFFLE(Y)) -> SHUFFLE(HOP(X,Y)) fold. (details)
  17. [GlobalISel] Ensure MachineIRBuilder::getDebugLoc() returns a const reference. NFCI. (details)
  18. [VPlan] Add test for sink scalars and merging using VPlan. (details)
  19. [libc++] NFC: Refactor Lit annotations (details)
  20. [lld/mac] Copy some of the commit message of d5a70db193 into a comment (details)
  21. [MCA][RegisterFile] Refactor the move elimination logic to address PR50258. (details)
  22. [lld-macho] Explicitly undefine literal exported symbols (details)
  23. [llvm-mca][View] Update the Register File statistics. (details)
  24. [Hexagon] Propagate metadata in Hexagon Vector Combine (details)
  25. [test] Fix tools/gold/X86/new-pm.ll after D101797 (details)
  26. [NFCI][X86] Mark a few lately-added system instructions as such for Scheduling purposes (details)
  27. [NFCI][X86] Mark Znver3 scheduling model as complete (details)
  28. [NFC][LoopIdiom] Add some tests for 'lshr until zero' ('count active bits') "on steroids" idiom (details)
  29. [lld-macho][NFC] Purge stale test-output trees prior to split-file (details)
  30. [libc++][doc] Update the Format library status. (details)
  31. [SROA] Regenerate test checks (NFC) (details)
  32. [SelectionDAG] Regenerate test checks (NFC) (details)
  33. [X86] AMD Zen 3: XCHG is a zero-cycle instruction (details)
  34. [NFC][X86] Znver3: drop obsolete fixme (details)
  35. [SCEV] Add additional loop guard and/or tests (NFC) (details)
  36. [SCEV] Handle and/or in applyLoopGuards() (details)
  37. [ARM] Fix postinc of vst1xN (details)
  38. [NFC][X86][MCA] AMD Zen3: add GPR zero-idiom dependency breaking tests (details)
  39. [X86] AMD Zen 3: same-register XOR/SUB are GPR dependency breaking zero-idioms (details)
  40. [NFC][X86][MCA] AMD Zen 3: add tests for SBB dependency breaking (details)
  41. [X86] AMD Zen 3: same-reg SBB is a dependency-breaking instruction (details)
  42. [NFC][X86][MCA] AMD Zen 3: add tests for CMP dependency breaking (details)
  43. [X86] AMD Zen 3: same-reg CMP is a zero-cycle dependency-breaking instruction (details)
  44. [Demangle][Rust] Print special namespaces (details)
  45. [lld-macho] Don't reference entry symbol for non-executables (details)
  46. [lld/mac] Fix alignment on subsections (details)
  47. [lld-macho] Add llvm-otool as a test dependency (details)
  48. Support NativeCodeCall binding in rewrite pattern. (details)
  49. [RISCV][NFC] Don't need to create a new STI in RISCVAsmPrinter. (details)
  50. [NFC][Coroutines] Fix two tests by removing hardcoded SSA value. (details)
  51. [SimplifyCFG] Ignore ephemeral values when counting insts for threading (details)
  52. [ORC] Generalize materialization dispatch to task dispatch. (details)
  53. [ORC] Use the new dispatchTask API to run query callbacks. (details)
  54. [AArch64][SVE] Remove index_vector node. (details)
  55. [mlir] Fix compile error. (details)
  56. [LegalizeVectorOps][RISCV] Add scalable-vector SELECT expansion (details)
  57. [amdgpu-arch] Guard hsa.h with __has_include (details)
  58. [AMDGPU][OpenMP] Disable tests when amdgpu-arch fails (details)
  59. [libc] Allow target architecture customization (details)
  60. [AMDGPU][OpenMP] Emit textual IR for -emit-llvm -S (details)
  61. [mlir] OpenMP-to-LLVM: properly set outer alloca insertion point (details)
  62. AMDGPU/GlobalISel: Add regbankselect test for vgpr(dest) sgpr(address) load (details)
  63. AMDGPU/GlobalISel: Use destination register bank in applyMappingLoad (details)
  64. [libc] Simplifies multi implementations and benchmarks (details)
  65. [MLIR][Shape] Concretize broadcast result type if possible (details)
  66. [compiler-rt] Handle None value when polling addr2line pipe (details)
  67. Fixed bug in buffer deallocation pass using unranked memref types. (details)
  68. [OpenMP][MLIR]Add support for guided, auto and runtime scheduling (details)
  69. [clang][PreProcessor] Cutoff parsing after hitting completion point (details)
  70. HexagonVectorCombine.cpp - don't negate a bool value. NFCI. (details)
  71. [AArch64][SVE] Fix isel failure for FP-extending loads (details)
  72. [GlobalISel] Fix wrong invocation of `getParamStackAlign` (NFC) (details)
  73. [AArch64][SVE] Better utilisation of unpredicated forms of arithmetic intrinsics (details)
  74. [AArch64][SVE] Better utilisation of unpredicated forms of remaining intrinsics (details)
  75. clang: Fix tests after 7f78e409d028 if clang is not called clang-13 (details)
  76. [NFC][llvm-dwarfdump] Code clean up for inlined var loc stats (details)
  77. [clangd] Fix data type of WorkDoneProgressReport::percentage (details)
  78. [Constant] Allow ConstantAggregateZero a scalable element count (details)
  79. X86LoadValueInjectionLoadHardening.cpp - use const-reference in for-range loops to avoid unnecessary copies. NFCI. (details)
  80. X86FlagsCopyLowering.cpp - try to pass DebugLoc by const-ref to avoid costly TrackingMDNodeRef copies. NFCI. (details)
  81. [TableGen] Remove redundant `Error:` in msg (NFC) (details)
  82. [OPENMP]Fix PR48851: the locals are not globalized in SPMD mode. (details)
  83. [AArch64][SVE] Improve SVE codegen for fixed length BITCAST (details)
  84. [libc++][AIX] Define _LIBCPP_ELAST (details)
  85. [SLP]Do not count perfect diamond matches for gathers several times. (details)
  86. [PowerPC] Enable safe for 32bit vins* P10 instructions (details)
  87. [libomptarget] Add support for target allocators to dynamic cuda RTL (details)
  88. Revert "[PassManager] add helper function to hold set of vector passes" (details)
  89. [clang][AArch32] Correctly align HA arguments when passed on the stack (details)
  90. [NFC] Synchronize reserved identifier code between macro and variables / symbols (details)
  91. [X86] Fix position-independent TType encoding (details)
  92. [libc++][NFC] Remove _VSTD:: when not needed. (details)
  93. [llvm-objdump][MachO] Print a newline before lazy bind/bind/weak/exports trie (details)
  94. [X86][SSE] Merge equal X32/X64 check prefixes. NFCI. (details)
  95. [X86][SSE] Add tests for missing shuffle(pack(x,y),pack(z,w)) -> permute(pack()) folds. (details)
  96. [llvm-symbolizer] Update Command Guide (details)
  97. [llvm-nm] Help option output should be consistent with the command guide (details)
  98. [ORC] Update SpeculativeJIT example for dispatchTask changes in 5344c88dcb2. (details)
  99. [clang] Support -fpic -fno-semantic-interposition for AArch64 (details)
  100. [Demangle][Rust] Parse basic types (details)
  101. [RISCV] Correct VL for fixed length masked scatter. (details)
  102. [X86][SSE] Add examples of failures to remove a permute(pack(pack(),pack())) shuffle by reordering the packed operands. (details)
  103. [mlir][CAPI] Add CAPI bindings for the sparse_tensor dialect. (details)
  104. [cmake] Enable -Wmisleading-indentation (details)
  105. [lld][WebAssembly] Disallow exporting of TLS symbols (details)
  106. [mlir][Python] Upstream the PybindAdaptors.h helpers and use it to implement sparse_tensor.encoding. (details)
  107. [Dependence Analysis] Enable delinearization of fixed sized arrays (details)
  108. [lld-macho] Improve an external weak def test (details)
  109. [X86][SSE] canonicalizeShuffleMaskWithHorizOp - add TODO for better 256/512-bit shuffle+hop folding support. NFC. (details)
  110. [X86][AVX] Add example of failure to remove a 256-bit permute(hadd(hadd(),hadd())) shuffle by reordering the packed operands. (details)
  111. [NFC][X86][MCA] AMD Zen 3: add tests for sub-32-bit CMP dep breaking (details)
  112. [X86] AMD Zen 3: sub-32-bit CMP also break dependencies (details)
  113. [mlir][Python] Re-export cext sparse_tensor module to the public namespace. (details)
  114. [PassManager] add helper function to hold set of vector passes (2nd try) (details)
  115. [GlobalISel][IRTranslator] Fix bit-test lowering dropping phi edges. (details)
  116. [RISCV] Validate the SEW and LMUL operands to __builtin_rvv_vsetvli(max) (details)
  117. [scudo] [GWP-ASan] Add GWP-ASan variant of scudo benchmarks. (details)
  118. [libc] Rever "Simplifies multi implementations and benchmarks". (details)
  119. [mlir][linalg] Restrict distribution to parallel dims (details)
  120. [TargetLowering] Only inspect attributes in the arguments for ArgListEntry (details)
  121. [PowerPC] Spilling to registers does not require frame index scavenging (details)
  122. [lld-macho][nfc] Clean up tests (details)
  123. [lld-macho] Treat undefined symbols uniformly (details)
  124. [lld-macho] Fix order file arch filtering (details)
  125. [mlir][sparse] complete migration to sparse tensor type (details)
  126. [Scudo] Use GWP-ASan's aligned allocations and fixup postalloc hooks. (details)
  127. [Inliner] Fix noalias metadata handling for instructions simplified during cloning (PR50270) (details)
  128. [ORC] Use a unique_function rather than std::function for dispatchTask. (details)
  129. [NFC] Use ArgListEntry indirect types more in ISel lowering (details)

Started by upstream project LLDB Incremental build number 31861
originally caused by:

  • Started by timer

This run spent:

  • 7.1 sec waiting;
  • 1 hr 24 min build duration;
  • 1 hr 24 min total from scheduled to completion.
Revision: f7b888457641941a8e6024f36ee2e5ddc53695d5
  • refs/remotes/origin/main
Revision: 85af8a8c1b574faa0d5d57d189ae051debdfada8
  • refs/remotes/origin/main
Revision: f7b888457641941a8e6024f36ee2e5ddc53695d5
  • refs/remotes/origin/main
Test Result (no failures)
    Revision: 6a075b6de4cafebec9ca1ff9eec7229a617c93f6
    • llvmorg-5.0.2
    Revision: d0d8eb2e5415b8be29343e3c17a18e49e67b5551
    • llvmorg-7.0.1
    Revision: 0399d5a9682b3cef71c653373e38890c63c4c365
    • llvmorg-9.0.0