FailedChanges

Summary

  1. [TableGen] Allow mnemonics with uppercase letters to be matched (details)
  2. [SLC] sprintf(dst, "%s", str) -> strcpy(dst, str) (details)
  3. Temporarily revert "[SCEVExpander] Add helper to clean up instrs inserted while expanding." (details)
  4. [TestPtrRefs] Prefer `command script import`. (details)
  5. [TestPtrRefsObjC] Prefer `command script import`. (details)
  6. [X86][MC][Target] Initial backend support a tune CPU to support -mtune (details)
  7. [ELF] Re-initialize InputFile::isInGroup so that elf::link can be called more than once (details)
  8. Fix TargetSubtargetInfo derivatives after D85165 (details)
  9. [NewPM][optnone] Mark various passes as required (details)
  10. [test][LoopUnroll] Cleanup FullUnroll.ll (details)
  11. Remove deopt and gc transition arguments from gc.statepoint intrinsic (details)
  12. [libcxx/variant] Avoided variable name shadowing. (details)
  13. [SVE] Remove calls to VectorType::getNumElements from AggressiveInstCombine (details)
  14. [SVE] Lower fixed length vXi32/vXi64 SDIV to scalable vectors. (details)
  15. [MSAN] Avoid dangling ActualFnStart when replacing instruction (details)
  16. [SLC] Transform strncpy(dst, "text", C) to memcpy(dst, "text\0\0\0", C) for C <= 128 only (details)
  17. [AMDGPU] Fix MAI ld/st hazard handling (details)
Commit 3cf7efec986da0e2e8812f83eb7507512475687d by nguillemot
[TableGen] Allow mnemonics with uppercase letters to be matched

The assembly parser "canonicalizes" the mnemonics it processes at an
early level by making them lowercase. The goal of this is presumably to
allow assembly to be case-insensitive. However, if one declares an
instruction with a mnemonic using uppercase letters, then it will
never get matched, since the generated lookup tables for the
AsmMatcherEmitter didn't lower() their inputs. This made it difficult to
have instructions that get printed using a mnemonic that includes
uppercase letters, since they could not be parsed.

To fix this problem, this patch adds a few calls to lower() to make the
lookup tables used in AsmMatcherEmitter be case-insensitive. This allows
instruction mnemonics with uppercase letters to be parsed.

Differential Revision: https://reviews.llvm.org/D85858
The file was addedllvm/test/TableGen/MixedCasedMnemonic.td
The file was modifiedllvm/utils/TableGen/AsmMatcherEmitter.cpp
Commit 6dbf0cfcf789365493f70ae69df8a7a59be41c75 by Dávid Bolvanský
[SLC] sprintf(dst, "%s", str) -> strcpy(dst, str)

Transform sprintf(dst, "%s", str) -> strcpy(dst, str) if result is unused
Avoid sprintf(dest, "%s", str) -> llvm.memcpy(align 1 dest, align 1 str, strlen(str)+1) if optimizing for size.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D85963
The file was modifiedllvm/test/Transforms/InstCombine/2010-05-30-memcpy-Struct.ll
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
The file was modifiedllvm/test/Transforms/InstCombine/sprintf-1.ll
Commit 38884641f28e373ce291dc5ea93416756216e536 by rupprecht
Temporarily revert "[SCEVExpander] Add helper to clean up instrs inserted while expanding."

This reverts commit 7829c33084a7a5097533cf862daef521380c4e63. The assertion is triggering on some internal code. A reduced test case is in progress.
The file was modifiedllvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
The file was modifiedllvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
The file was modifiedllvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
Commit 8fcfe2862fd4fde4793e232cfeebe6c5540c80a5 by ditaliano
[TestPtrRefs] Prefer `command script import`.
The file was modifiedlldb/test/API/functionalities/ptr_refs/TestPtrRefs.py
Commit 0cceb54366b406649fdfe7bb11b133ab96f3cd70 by ditaliano
[TestPtrRefsObjC] Prefer `command script import`.
The file was modifiedlldb/test/API/lang/objc/ptr_refs/TestPtrRefsObjC.py
Commit c7a0b2684f74de5ba725d984cacd151863f9f803 by craig.topper
[X86][MC][Target] Initial backend support a tune CPU to support -mtune

This patch implements initial backend support for a -mtune CPU controlled by a "tune-cpu" function attribute. If the attribute is not present X86 will use the resolved CPU from target-cpu attribute or command line.

This patch adds MC layer support a tune CPU. Each CPU now has two sets of features stored in their GenSubtargetInfo.inc tables . These features lists are passed separately to the Processor and ProcessorModel classes in tablegen. The tune list defaults to an empty list to avoid changes to non-X86. This annoyingly increases the size of static tables on all target as we now store 24 more bytes per CPU. I haven't quantified the overall impact, but I can if we're concerned.

One new test is added to X86 to show a few tuning features with mismatched tune-cpu and target-cpu/target-feature attributes to demonstrate independent control. Another new test is added to demonstrate that the scheduler model follows the tune CPU.

I have not added a -mtune to llc/opt or MC layer command line yet. With no attributes we'll just use the -mcpu for both. MC layer tools will always follow the normal CPU for tuning.

Differential Revision: https://reviews.llvm.org/D85165
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
The file was modifiedllvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
The file was modifiedllvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
The file was modifiedllvm/lib/Target/Lanai/LanaiSubtarget.cpp
The file was modifiedllvm/lib/CodeGen/TargetSubtargetInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64Subtarget.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonSubtarget.h
The file was modifiedllvm/lib/Target/Sparc/SparcSubtarget.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetSubtargetInfo.h
The file was modifiedllvm/unittests/CodeGen/MFCommon.inc
The file was modifiedllvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/Lanai/LanaiSubtarget.h
The file was modifiedllvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/X86/X86.td
The file was modifiedllvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/BPF/BPFSubtarget.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.h
The file was modifiedllvm/lib/MC/MCSubtargetInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZSubtarget.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.h
The file was modifiedllvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64Subtarget.h
The file was modifiedllvm/lib/Target/Mips/MipsSubtarget.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXSubtarget.h
The file was modifiedllvm/lib/Target/XCore/XCoreSubtarget.h
The file was modifiedllvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonSubtarget.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZSubtarget.h
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
The file was modifiedllvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/Sparc/SparcSubtarget.h
The file was modifiedllvm/lib/Target/BPF/BPFSubtarget.h
The file was modifiedllvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/X86/X86TargetMachine.cpp
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
The file was modifiedllvm/lib/Target/AVR/AVRSubtarget.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
The file was modifiedllvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
The file was modifiedllvm/lib/Target/XCore/XCoreSubtarget.cpp
The file was modifiedllvm/lib/Target/X86/X86Subtarget.cpp
The file was modifiedllvm/lib/Target/ARM/ARMSubtarget.h
The file was modifiedllvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/AVR/AVRSubtarget.h
The file was modifiedllvm/lib/Target/MSP430/MSP430Subtarget.cpp
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
The file was modifiedllvm/include/llvm/MC/MCSubtargetInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.cpp
The file was modifiedllvm/include/llvm/Target/Target.td
The file was modifiedllvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/ARM/ARMSubtarget.cpp
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/X86/X86Subtarget.h
The file was modifiedllvm/utils/TableGen/SubtargetEmitter.cpp
The file was modifiedllvm/lib/Target/MSP430/MSP430Subtarget.h
The file was modifiedllvm/lib/Target/Mips/MipsSubtarget.h
Commit b358daddea04ea3c52e0e5bd5e851cee47f7f27f by i
[ELF] Re-initialize InputFile::isInGroup so that elf::link can be called more than once
The file was modifiedlld/ELF/Driver.cpp
Commit 58f5966d5bc197a052f638545cc5fecc2f3277de by i
Fix TargetSubtargetInfo derivatives after D85165
The file was modifiedllvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/ARC/ARCSubtarget.cpp
The file was modifiedllvm/lib/Target/VE/VESubtarget.h
The file was modifiedllvm/lib/Target/ARC/ARCSubtarget.h
The file was modifiedllvm/lib/Target/VE/VESubtarget.cpp
Commit e6ea8779c2e0c60007d1015cc98fe3d2642a1652 by aeubanks
[NewPM][optnone] Mark various passes as required

This was done by turning on -enable-npm-optnone and fixing failures.
That will be enabled in a follow-up change for ease of reverting.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D85457
The file was modifiedllvm/include/llvm/Transforms/IPO/AlwaysInliner.h
The file was modifiedllvm/include/llvm/Transforms/Instrumentation/SanitizerCoverage.h
The file was modifiedllvm/include/llvm/Transforms/Coroutines/CoroCleanup.h
The file was modifiedllvm/include/llvm/Transforms/Coroutines/CoroSplit.h
The file was modifiedllvm/include/llvm/Transforms/Scalar/LowerAtomic.h
The file was addedclang/test/CodeGen/O0-no-skipped-passes.c
The file was modifiedllvm/include/llvm/IR/PassManager.h
The file was modifiedllvm/include/llvm/IR/Verifier.h
The file was modifiedllvm/include/llvm/Transforms/Instrumentation/HWAddressSanitizer.h
The file was modifiedllvm/include/llvm/Transforms/Instrumentation/BoundsChecking.h
The file was modifiedllvm/include/llvm/IR/IRPrintingPasses.h
The file was modifiedllvm/include/llvm/Transforms/Instrumentation/ThreadSanitizer.h
The file was modifiedllvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
The file was modifiedllvm/include/llvm/Transforms/Instrumentation/MemorySanitizer.h
The file was modifiedllvm/include/llvm/Transforms/Coroutines/CoroEarly.h
The file was modifiedllvm/test/Feature/optnone-opt.ll
The file was modifiedllvm/include/llvm/Transforms/Coroutines/CoroElide.h
The file was modifiedllvm/include/llvm/Transforms/Scalar/LowerMatrixIntrinsics.h
Commit 72effd8d5b08df54806dde68c5c505b15d56f316 by aeubanks
[test][LoopUnroll] Cleanup FullUnroll.ll

This is in preparation for enabling proper handling of optnone under the
NPM. Most optimizations won't run on an optnone function.

Previously the test would rely on lots of optimizations to optimize the
IR into a simple infinite loop. This is an optnone function, so clearly
that shouldn't be the case.

This IR was found by printing the module before the LoopFullUnrollerPass ran.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D85578
The file was modifiedllvm/test/Transforms/LoopUnroll/FullUnroll.ll
Commit a96fc4638b732d9d28b1803f94f50cb58a456e9e by listmail
Remove deopt and gc transition arguments from gc.statepoint intrinsic

(Forgot to land this a couple of weeks back.)

In a recent series of changes, I've introduced support for using the respective operand bundle kinds on the statepoint. At the moment, code supports either/or, but there's no need to keep the old support around. For the moment, I am simply changing the specification and verifier to require zero length argument sets in the intrinsic.

The intrinsic itself is experimental. Given that, there's no forward serialization needed. The in tree uses and generation have already been updated to use the new operand bundle based forms, the only folks broken by the change will be those with frontends generating statepoints directly and the updates should be easy.

Why not go ahead and just remove the arguments entirely? Well, I plan to. But while working on this I've found that almost all of the arguments to the statepoint can be expressed via operand bundles or attributes. Given that, I'm planning a radical simplification of the arguments and figured I'd do one update not several small ones.

Differential Revision: https://reviews.llvm.org/D80892
The file was modifiedllvm/lib/CodeGen/TargetInstrInfo.cpp
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedllvm/docs/Statepoints.rst
The file was modifiedllvm/test/Verifier/statepoint.ll
The file was modifiedllvm/docs/LangRef.rst
Commit 02197f7e50b938f8167b17b89bdf7c55feff4339 by mcypark
[libcxx/variant] Avoided variable name shadowing.
The file was modifiedlibcxx/include/variant
Commit 416a6a85b14883149a1eb48c9705dad097704d3b by ctetreau
[SVE] Remove calls to VectorType::getNumElements from AggressiveInstCombine

Reviewed By: fpetrogalli

Differential Revision: https://reviews.llvm.org/D82218
The file was modifiedllvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
Commit 92593f9e77c387cee1ab5573b2f4b5c42162e8b8 by mcinally
[SVE] Lower fixed length vXi32/vXi64 SDIV to scalable vectors.

Differential Revision: https://reviews.llvm.org/D85982
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
Commit 05e3ab41e418e3d19541b7e88587f8302888e5ab by guiand
[MSAN] Avoid dangling ActualFnStart when replacing instruction

This would be a problem if the entire instrumented function was a call
to
e.g. memcpy

Use FnPrologueEnd Instruction* instead of ActualFnStart BB*

Differential Revision: https://reviews.llvm.org/D86001
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/clmul.ll
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/array_types.ll
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/msan_eager.ll
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/unsized_type.ll
The file was modifiedllvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/attributes.ll
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/masked-store-load.ll
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/msan_kernel_basic.ll
The file was modifiedllvm/test/Instrumentation/MemorySanitizer/msan_x86intrinsics.ll
Commit f62de7c9c71134af060a3a1686e30e69d439e785 by Dávid Bolvanský
[SLC] Transform strncpy(dst, "text", C) to memcpy(dst, "text\0\0\0", C) for C <= 128 only

Transformation creates big strings for big C values, so bail out for C > 128.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D86004
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
The file was modifiedllvm/test/Transforms/InstCombine/strncpy-3.ll
Commit 43a38dc25173d5139a7f14b06f3ee7b59325c96c by Stanislav.Mekhanoshin
[AMDGPU] Fix MAI ld/st hazard handling

It did not process hazard for ds_permute because it does not
load or store even though it is DS.

Differential Revision: https://reviews.llvm.org/D86003
The file was modifiedllvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/mai-hazards.mir