SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [SLP] add more FMF tests for fmax/fmin reductions; NFC (details)
  2. [RISCV][NFC] Increase test coverage of Zbt extension (details)
  3. [AArch64] Make target intrinsics DefaultAttrIntrinsics. (details)
  4. [LLD][ELF][AArch64] Set _GLOBAL_OFFSET_TABLE_ at the start of .got (details)
  5. [AArch64] Revert back to Intrinsic<> for TME instructions. (details)
  6. [lldb][docs] Use 'any' as the default role in LLDB's sphinx project (details)
  7. [llvm] Populate std::vector at construction time (NFC) (details)
  8. [STLExtras] Add a default value to drop_begin (details)
  9. [llvm] Use the default value of drop_begin (NFC) (details)
  10. [clang] Allow LifetimeExtendedTemporary to have no access specifier (details)
  11. [RISCV] Add a test of vector sadd.overflow to demonstrate intrinsics with multiple scalable vector results. (details)
  12. Revert "[RISCV] Add a test of vector sadd.overflow to demonstrate intrinsics with multiple scalable vector results." (details)
  13. Recommit "[RISCV] Add a test of vector sadd.overflow to demonstrate intrinsics with multiple scalable vector results." (details)
  14. [libc++] Rename check-cxx-deps to cxx-test-depends for consistency (details)
  15. [NFC] Update some mlir python documentation. (details)
  16. [libc++] improve feature test macro script (details)
  17. NFC: Document current MLIR Python ODS conventions. (details)
  18. [OpenMP][NFC] Fix test (details)
  19. [PredicateInfo] Add more and/or tests (NFC) (details)
  20. [RISCV] Remove empty Sched instantiations from the end of InstAlias defs. NFCI (details)
  21. [SLP] match maxnum/minnum intrinsics as FP reduction ops (details)
  22. [libc++] NFCI: Refactor allocator_traits (details)
  23. [x86] add cast to avoid compile-time warning; NFC (details)
  24. [LoopInfo] Fix a typo in compareLoops (details)
  25. [SimplifyCFG] Update SimplifyBranchOnICmpChain to recognize select form of and/or (details)
  26. [OpenMP][Docs] Fix typos in FAQ (NFC) (details)
  27. Regenerate the feature test macro unit-tests. NFCI. (details)
  28. [InstCombine,InstSimplify] Optimize select followed by and/or/xor (details)
  29. Address unused variable warning (details)
  30. Revert "[NFC] [TargetRegisterInfo] add one use check to lookThruCopyLike." (details)
  31. [X86] Fix tile spill merge issue. (details)
  32. PR48763: Better handling for classes that inherit a default constructor. (details)
  33. [PowerPC] Sign extend comparison operand for signed atomic comparisons (details)
  34. [X86][AMX] Clear AMX lit test case. (details)
Commit ca7e27054c25c2bc6cf88879d73745699251412c by spatel
[SLP] add more FMF tests for fmax/fmin reductions; NFC
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
Commit b42ff9fb038206c7967e22ceef2c7ea8275dc198 by sam
[RISCV][NFC] Increase test coverage of Zbt extension

Add Zbt (ternary) extension code generation to the select lowering
tests since it can have a significant impact on how select is
lowered.

While we are here make the neg-abs commands more consistent with
the other tests.

Reviewed By: lenary

Differential Revision: https://reviews.llvm.org/D94798
The file was modifiedllvm/test/CodeGen/RISCV/neg-abs.ll
The file was modifiedllvm/test/CodeGen/RISCV/select-optimize-multiple.ll
The file was removedllvm/test/CodeGen/RISCV/bare-select.ll
The file was modifiedllvm/test/CodeGen/RISCV/select-cc.ll
The file was addedllvm/test/CodeGen/RISCV/select-bare.ll
The file was modifiedllvm/test/CodeGen/RISCV/select-or.ll
The file was modifiedllvm/test/CodeGen/RISCV/select-optimize-multiple.mir
The file was modifiedllvm/test/CodeGen/RISCV/select-const.ll
The file was modifiedllvm/test/CodeGen/RISCV/select-and.ll
Commit 50ae6a3ac9bdf640ecc69fe6540b08a8b4355398 by flo
[AArch64] Make target intrinsics DefaultAttrIntrinsics.

DefaultAttrIntrinsics was introduced to add very common attributes to a
large set of intrinsics.

Currently the added attributes include:

    nofree nosync nounwind willreturn

I think those should hold for most AArch64 target intrinsics, but
there are too many to check manually. This patch makes most AArch64 target
intrinsics DefaultAttrsIntrinsics.

Some notable exceptions I think are exclusive loads and stores as well
as the memory barrier intrinsics, for which nosync does not apply I
think.

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D94687
The file was modifiedllvm/test/Assembler/aarch64-intrinsics-attributes.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
Commit 2f92386e721acd7badac06b67229537c4f0adfad by adhemerval.zanella
[LLD][ELF][AArch64] Set _GLOBAL_OFFSET_TABLE_ at the start of .got

The commit 18aa0be36ed9 changed the default GotBaseSymInGotPlt to true
for AArch64.  This is different than binutils, where
_GLOBAL_OFFSET_TABLE_ points at the start or .got.

It seems to not intefere with current relocations used by LLVM.  However
as indicated by PR#40357 [1] gcc generates R_AARCH64_LD64_GOTPAGE_LO15
for -pie (in fact it also generated the relocation for -fpic).

This change is requires to correctly handle R_AARCH64_LD64_GOTPAGE_LO15
by lld from objects generated by gcc.

[1] https://bugs.llvm.org/show_bug.cgi?id=40357
The file was modifiedlld/test/ELF/global-offset-table-position-aarch64.s
The file was modifiedlld/ELF/Arch/AArch64.cpp
Commit 291ac7e622d542f8b25f74bc28051762edc90938 by flo
[AArch64] Revert back to Intrinsic<> for TME instructions.

This patch reverts back to Intrinsic for the instructions for the
transactional memory extension, so nosync is not included.
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was modifiedclang/test/CodeGen/aarch64-tme.cpp
Commit a58aceffad61ebffb1a860763299b3307041efa6 by Raphael Isemann
[lldb][docs] Use 'any' as the default role in LLDB's sphinx project

sphinx processes text in backticks depending on what 'role' it has (e.g.,
`:code:\`blub\`` -> role is `code`). If no role is provided, the default role is
taken which is right now using the default value of `content`. `content` only
really makes the text cursive which isn't really useful for anything right now.

Sphinx recommends using the `any` role by default [1] as that turns text in
backticks without an explicit roles into some kind of smart reference. If we did
this in LLDB, then we could just reference SB API classes by doing `\`SBValue\``
instead of typing out the rather verbose `:py:class:`/`:py:func:`/... role
before each reference. This would be especially nice when writing the SB API
docs itself as we constantly have to reference other classes.

[1] https://www.sphinx-doc.org/en/master/usage/restructuredtext/roles.html#role-any

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D94899
The file was modifiedlldb/docs/use/variable.rst
The file was modifiedlldb/docs/use/python.rst
The file was modifiedlldb/docs/conf.py
Commit 28ea50f524b56e11b608ca1f768d2981579ebe75 by kazu
[llvm] Populate std::vector at construction time (NFC)
The file was modifiedllvm/lib/ProfileData/SampleProf.cpp
The file was modifiedllvm/lib/ObjectYAML/MachOEmitter.cpp
The file was modifiedllvm/lib/ObjectYAML/DWARFEmitter.cpp
Commit dc300beba7a849aac44c39ccc450a575db99bc14 by kazu
[STLExtras] Add a default value to drop_begin

This patch adds the default value of 1 to drop_begin.

In the llvm codebase, 70% of calls to drop_begin have 1 as the second
argument.  The interface similar to with std::next should improve
readability.

This patch converts a couple of calls to drop_begin as examples.

Differential Revision: https://reviews.llvm.org/D94858
The file was modifiedllvm/unittests/ADT/STLExtrasTest.cpp
The file was modifiedllvm/lib/Transforms/Utils/LoopUtils.cpp
The file was modifiedllvm/include/llvm/ADT/STLExtras.h
Commit 23b0ab2acb424e3e74722c0183e5c5ac84e6ea4c by kazu
[llvm] Use the default value of drop_begin (NFC)
The file was modifiedllvm/lib/Transforms/Scalar/LoopInterchange.cpp
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
The file was modifiedllvm/lib/Target/X86/X86MCInstLower.cpp
The file was modifiedllvm/lib/CodeGen/SafeStackLayout.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
The file was modifiedllvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp
The file was modifiedllvm/lib/Analysis/LoopInfo.cpp
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
The file was modifiedllvm/lib/Analysis/ModuleSummaryAnalysis.cpp
The file was modifiedllvm/lib/Analysis/VFABIDemangling.cpp
The file was modifiedllvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
The file was modifiedllvm/tools/llvm-xray/xray-stacks.cpp
Commit 196cc96f9a643d1cb828f48ef15ec30d0de24df7 by adamcz
[clang] Allow LifetimeExtendedTemporary to have no access specifier

The check only runs in debug mode during serialization, but
assert()-fail on:
  struct S { const int& x = 7; };
in C++ mode.

Differential Revision: https://reviews.llvm.org/D94804
The file was modifiedclang/test/PCH/cxx-reference.h
The file was modifiedclang/lib/AST/DeclBase.cpp
Commit 2c51bef76cbf0149101b9e7c7c658b4a58657929 by craig.topper
[RISCV] Add a test of vector sadd.overflow to demonstrate intrinsics with multiple scalable vector results.

This builds on D94142 where scalable vectors are allowed in structs.

I did have to fix one scalable vector issue in the vector type
creation for these intrinsics where we used getVectorNumElements
instead of ElementCount.

Differential Revision: https://reviews.llvm.org/D94149
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
Commit 5d431c3d32c7736d74c6a9dfe4a9a43f183d880f by craig.topper
Revert "[RISCV] Add a test of vector sadd.overflow to demonstrate intrinsics with multiple scalable vector results."

This reverts commit 2c51bef76cbf0149101b9e7c7c658b4a58657929.

I seem to have messed up the check lines in the test.
The file was removedllvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Commit 79e798aca38baa260b9f3318991232dd1b5fc3f6 by craig.topper
Recommit "[RISCV] Add a test of vector sadd.overflow to demonstrate intrinsics with multiple scalable vector results."

This recommits 2c51bef76cbf0149101b9e7c7c658b4a58657929.

I've fixed the broken check line from when I renamed the test function.

Original commit message:
This builds on D94142 where scalable vectors are allowed in structs.

I did have to fix one scalable vector issue in the vector type
creation for these intrinsics where we used getVectorNumElements
instead of ElementCount.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
Commit 01a13f127a8b17c7827cc19302fc612532249795 by Louis Dionne
[libc++] Rename check-cxx-deps to cxx-test-depends for consistency

Several subprojects have targets that do the same thing, and they all
follow the same naming convention: llvm-test-depends, clang-test-depends,
lld-test-depends, etc.

This makes libc++ consistent with other LLVM projects.
Thanks to Duncan Exon Smith for noticing and suggesting the change.

Differential Revision: https://reviews.llvm.org/D94499
The file was modifiedlibcxx/test/CMakeLists.txt
The file was modifiedlibcxx/docs/TestingLibcxx.rst
Commit 417f613743239a716d812443ba131207d78c6c9d by stellaraccident
[NFC] Update some mlir python documentation.

* Development setup recommendations.
* Test updates to match what we actually do.
* Update cmake variable `PYTHON_EXECUTABLE` -> `Python3_EXECUTABLE` to match the upgrade to python3 repo wide.
The file was modifiedmlir/docs/Bindings/Python.md
Commit 2776be43f0c28031348d2b18a050a8d6d01120f2 by Louis Dionne
[libc++] improve feature test macro script

I've been playing a bit with the `generate_feature_test_macro_components.py` script and replaced some hardcoded values with extra code generation (generate ALL the things).
The output is the same and it makes updating the script less work for the coming 25 C++ standards (until 2 digit number overflow).

Feel free to 'veto' if you think it's overkill.

Differential Revision: https://reviews.llvm.org/D94530
The file was modifiedlibcxx/utils/generate_feature_test_macro_components.py
Commit d9b6e4d583c5585b756680e6da3fbd0bb8f0a722 by stellaraccident
NFC: Document current MLIR Python ODS conventions.

* We had let the documentation get stale and catching it up prior to proposing changes.
The file was modifiedmlir/docs/Bindings/Python.md
Commit aa3a59e0c69e16ff25ee991636247f9f99bfc34d by Andrey.Churbanov
[OpenMP][NFC] Fix test

The test fails if memkind library is accessible.
The file was modifiedopenmp/runtime/test/api/omp_alloc_null_fb.c
Commit 22b68440e1647e16b5ee24b924986207173c02d1 by nikita.ppv
[PredicateInfo] Add more and/or tests (NFC)
The file was modifiedllvm/test/Transforms/Util/PredicateInfo/testandor.ll
Commit 1c31459153647a21da9b5cdbb01f78bccfb341a5 by craig.topper
[RISCV] Remove empty Sched instantiations from the end of InstAlias defs. NFCI

InstAliases don't need scheduling information so I'm not sure what
these lines were even doing. Especially since the records don't
have names.
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoB.td
Commit 5b77ac32b1150d066b35b45d6d982f4b4a1f62ff by spatel
[SLP] match maxnum/minnum intrinsics as FP reduction ops

After much refactoring over the last 2 weeks to the reduction
matching code, I think this change is finally ready.

We effectively broke fmax/fmin vector reduction optimization
when we started canonicalizing to intrinsics in instcombine,
so this should restore that functionality for SLP.

There are still FMF problems here as noted in the code comments,
but we should be avoiding miscompiles on those for fmax/fmin by
restricting to full 'fast' ops (negative tests are included).

Fixing FMF propagation is a planned follow-up.

Differential Revision: https://reviews.llvm.org/D94913
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
Commit 2cb4a96a99e8acbf57a31d4d06ed5e21799d878e by Louis Dionne
[libc++] NFCI: Refactor allocator_traits

The implementation had a lot of boilerplate and was more complicated than
necessary. This NFC refactoring introduces a few macros to reduce code
duplication, and uses a consistent style and formatting for the whole file.

Differential Revision: https://reviews.llvm.org/D94544
The file was modifiedlibcxx/include/memory
The file was modifiedlibcxx/include/__memory/allocator_traits.h
Commit d27bb5c375ca8e96e15168587a3bcd91b244fcad by spatel
[x86] add cast to avoid compile-time warning; NFC
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit fe301f474977da0b82548652ef4bbd058542d076 by kazu
[LoopInfo] Fix a typo in compareLoops

The code here is checking to see if two sets are identical.
OtherBlocksSet should point to OtherL->getBlocksSet() instead.

Differential Revision: https://reviews.llvm.org/D94926
The file was modifiedllvm/include/llvm/Analysis/LoopInfoImpl.h
Commit 395c737d9fcefb0fb99ac6c524b1d47e697d31d6 by aqjune
[SimplifyCFG] Update SimplifyBranchOnICmpChain to recognize select form of and/or

This patch teaches SimplifyCFG::SimplifyBranchOnICmpChain to understand select form of
(x == C1 || x == C2 || ...) / (x != C1 && x != C2 && ...) and optimize them into switch if possible.
D93065 has more context about the transition, including links to the list of optimizations being updated.

Differential Revision: https://reviews.llvm.org/D93943
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
The file was modifiedllvm/test/Transforms/SimplifyCFG/switch_create.ll
Commit 9d81073acb49d2bdf32dc3477310dd20ffa0436f by kkwli0
[OpenMP][Docs] Fix typos in FAQ (NFC)
The file was modifiedopenmp/docs/SupportAndFAQ.rst
Commit 14573d44ae097969a6168fbf14cc7f796442a296 by arthur.j.odwyer
Regenerate the feature test macro unit-tests. NFCI.

Somehow commit 1f1250151f222ba391d05dcc173f4b6c65d05ca2 added the
right code but with the wrong whitespace.
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/version.version.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/type_traits.version.pass.cpp
Commit 0441df94ad874c0c59a3785bd54a3d2f9a616fac by aqjune
[InstCombine,InstSimplify] Optimize select followed by and/or/xor

This patch adds `A & (A && B)` -> `A && B`  (similarly for or + logical or)

Also, this patch adds `~(select C, (icmp pred X, Y), const)` -> `select C, (icmp pred' X, Y), ~const`.

Alive2 proof:
merge_and: https://alive2.llvm.org/ce/z/teMR97
merge_or: https://alive2.llvm.org/ce/z/b4yZUp
xor_and: https://alive2.llvm.org/ce/z/_-TXHi
xor_or: https://alive2.llvm.org/ce/z/2uYx_a

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D94861
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
The file was modifiedllvm/test/Transforms/InstCombine/select-safe-transforms.ll
Commit 2d89ebd5d17b8d8800606880fe02cd867e4a0b90 by aqjune
Address unused variable warning
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit a9b3303a8847e100ae23fa711f9b5b8963ebdaf9 by czhengsz
Revert "[NFC] [TargetRegisterInfo] add one use check to lookThruCopyLike."

This reverts commit 3bdf4507b66348ad78df4655a8e4f36c3fc10f3c.

Post commit comments need to be addressed first.
The file was modifiedllvm/lib/CodeGen/TargetRegisterInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetRegisterInfo.h
Commit c535a7fdadb4679327ebb1b3b82c73c9ff6a164a by yuanke.luo
[X86] Fix tile spill merge issue.

This is a additional bug fix for c5be0e0cc0. The distance for
the spill instructions is wrong in previous patch.

Differential Revision: https://reviews.llvm.org/D94772
The file was modifiedllvm/lib/CodeGen/InlineSpiller.cpp
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
Commit bc713f6a004723d1325bc16e1efc32d0ac82f939 by richard
PR48763: Better handling for classes that inherit a default constructor.

The C++ standard wording doesn't appear to properly handle the case
where a class inherits a default constructor from a base class. Various
properties of classes are defined in terms of the corresponding property
of the default constructor, and in this case, the class does not have a
default constructor despite being default-constructible, which the
wording doesn't handle properly.

This change implements a tentative fix for these problems, which has
also been proposed to the C++ committee: if a class would inherit a
default constructor, and does not explicitly declare one, then one is
implicitly declared.
The file was modifiedclang/test/CXX/special/class.inhctor/p1.cpp
The file was modifiedclang/include/clang/AST/CXXRecordDeclDefinitionBits.def
The file was modifiedclang/test/CXX/special/class.ctor/p6-0x.cpp
The file was modifiedclang/test/CXX/special/class.inhctor/p2.cpp
The file was modifiedclang/include/clang/AST/DeclCXX.h
The file was modifiedclang/lib/AST/DeclCXX.cpp
The file was modifiedclang/test/CXX/dcl.dcl/basic.namespace/namespace.udecl/p15.cpp
Commit 61f69153e8dd7956d03ce46e30257c5bb3e41873 by nemanja.i.ibm
[PowerPC] Sign extend comparison operand for signed atomic comparisons

As of 8dacca943af8a53a23b1caf3142d10fb4a77b645, we sign extend the atomic loaded
operand for signed subword comparisons. However, the assumption that the other
operand is correctly sign extended doesn't always hold. This patch sign extends
the other operand if it needs to be sign extended.

This is a second fix for https://bugs.llvm.org/show_bug.cgi?id=30451

Differential revision: https://reviews.llvm.org/D94058
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-regression.ll
The file was addedllvm/test/CodeGen/PowerPC/sign-ext-atomics.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
Commit e147eccafa157668c9cd0eb26f0042ad82425874 by yuanke.luo
[X86][AMX] Clear AMX lit test case.

Add nounwind attribute to avoid generating cfi instructions. Also make
global buffer 64 bytes align in lit test case.

Differential Revision: https://reviews.llvm.org/D94910
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-across-func.ll
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-config.ll
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-type.ll
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-intrinsic-chain.ll
The file was modifiedllvm/test/CodeGen/X86/AMX/amx-spill.ll