FailedChanges

Summary

  1. Enable export of FIR includes into the install tree (details)
  2. [RISCV] Fix the calculation of the offset of Zvlsseg spilling. (details)
  3. [AMDGPU] Pre-commit tests for D102211 (details)
Commit 1e11616a071d07d0f3cdae1140b5c8685eb564a2 by rkauffmann
Enable export of FIR includes into the install tree
https://reviews.llvm.org/D102040
The file was modifiedflang/CMakeLists.txt
Commit d8ec2b183e9243366e3a0cd1116dbe879856b333 by kai.wang
[RISCV] Fix the calculation of the offset of Zvlsseg spilling.

For Zvlsseg spilling, we need to convert the pseudo instructions
into multiple vector load/store instructions with appropriate offsets.
For example, for PseudoVSPILL3_M2, we need to convert it to

VS2R %v2, %base
ADDI %base, %base, (vlenb x 2)
VS2R %v4, %base
ADDI %base, %base, (vlenb x 2)
VS2R %v6, %base

We need to keep the size of the offset in the pseudo spilling instructions.
In this case, it is (vlenb x 2).

In the original implementation, we use the size of frame objects divide the
number of vectors in zvlsseg types. The size of frame objects is not
necessary exactly the same as the spilling data. It may be larger than
it. So, we change it to (VLENB x LMUL) in this patch. The calculation is
more direct and easy to understand.

Differential Revision: https://reviews.llvm.org/D101869
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
Commit ad558a4ff7cd61081cfeaabff1dbc8c0a9afa92b by carl.ritson
[AMDGPU] Pre-commit tests for D102211
The file was modifiedllvm/test/CodeGen/AMDGPU/hard-clauses.mir