Commit
0ae989a1fede0e512e2bfd57b328aad6c1920329
by llvm-devPass DebugLoc::appendInlinedAt DebugLoc arg by const reference not value.
Noticed by clang-tidy performance-unnecessary-value-param warning.
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 | llvm/lib/IR/DebugLoc.cpp |
 | llvm/include/llvm/IR/DebugLoc.h |
Commit
c83ec0a633583e5b12e0aeb70627eb35f7cd4847
by llvm-devMake dyn_cast results explicitly auto* instead of just auto.
Noticed by clang-tidy llvm-qualified-auto warning.
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 | llvm/lib/IR/Instructions.cpp |
Commit
38907b696c0e31d2269ec4b8966bf603c36b579c
by Xing[DWARFYAML][debug_abbrev] Emit 0 byte for terminating abbreviations.
The abbreviations for a given compilation unit end with an entry consisting of a 0 byte for the abbreviation code.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D82933
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 | llvm/test/ObjectYAML/MachO/DWARF2-AddrSize8-FormValues.yaml |
 | llvm/test/tools/yaml2obj/ELF/DWARF/debug-abbrev.yaml |
 | llvm/lib/ObjectYAML/DWARFEmitter.cpp |
 | llvm/test/tools/yaml2obj/ELF/DWARF/debug-info.yaml |
Commit
ca4c1ad854ab9baf510e489d81625cace991beb1
by david.green[Outliner] Set nounwind for outlined functions
This prevents the outlined functions from pulling in a lot of unnecessary code in our downstream libraries/linker. Which stops outlining making codesize worse in c++ code with no-exceptions.
Differential Revision: https://reviews.llvm.org/D57254
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 | llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-b.ll |
 | llvm/test/CodeGen/AArch64/machine-outliner-throw.ll |
 | llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-v8-3.ll |
 | llvm/test/CodeGen/AArch64/machine-outliner.ll |
 | llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll |
 | llvm/lib/CodeGen/MachineOutliner.cpp |
 | llvm/test/CodeGen/AArch64/machine-outliner-throw2.ll |
Commit
6bd1db08e7ccd61996d3867d22ff8eb1979f8621
by yamauchi[InstCombine] Don't let an alignment assume prevent new/delete removals.
Remove allocations with alignment assume.
Differential Revision: https://reviews.llvm.org/D81854
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 | llvm/test/Transforms/InstCombine/malloc-free-delete.ll |
 | llvm/lib/Transforms/InstCombine/InstructionCombining.cpp |
 | llvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll |
Commit
0f9d623b63e87b4ba30c30fd884ecc333eb32b4a
by gchatelet[Alignment][NFC] Use Align for BPFAbstractMemberAccess::RecordAlignment
This patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Differential Revision: https://reviews.llvm.org/D82962
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 | llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp |
Commit
353a169cb814334e47bc2e98f03931e62023665a
by epastor[ms] [llvm-ml] Use default RIP-relative addressing for x64 MASM.
Summary: When parsing 64-bit MASM, treat memory operands with unspecified base register as RIP-based.
Documented in several places, including https://software.intel.com/en-us/articles/introduction-to-x64-assembly: "Unfortunately, MASM does not allow this form of opcode, but other assemblers like FASM and YASM do. Instead, MASM embeds RIP-relative addressing implicitly."
Reviewed By: thakis
Differential Revision: https://reviews.llvm.org/D73227
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 | llvm/lib/Target/X86/AsmParser/X86Operand.h |
 | llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp |
 | llvm/include/llvm/MC/MCParser/MCAsmParser.h |
 | llvm/lib/MC/MCParser/MasmParser.cpp |
 | llvm/test/tools/llvm-ml/rip-relative-addressing.test |
Commit
0f6afd946d25a2e83288339934f8fa384e38eea3
by nikita.ppv[CVP] Use different number in test (NFC)
To make it clear that this is not intended to be specific to mask / bit tests.
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 | llvm/test/Transforms/CorrelatedValuePropagation/icmp.ll |
Commit
78c69a00a4cff786e0ef13c895d0db309d6b3f42
by Yuanfang Chen[NFC] Clean up uses of MachineModuleInfoWrapperPass
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 | llvm/lib/CodeGen/BBSectionsPrepare.cpp |
 | llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp |
 | llvm/lib/CodeGen/BranchFolding.cpp |
 | llvm/lib/CodeGen/MachineBlockPlacement.cpp |
 | llvm/lib/CodeGen/GCRootLowering.cpp |
 | llvm/lib/Target/X86/X86IndirectThunks.cpp |
 | llvm/lib/CodeGen/UnreachableBlockElim.cpp |
 | llvm/lib/Target/AArch64/AArch64SLSHardening.cpp |
 | llvm/lib/Target/X86/X86InsertPrefetch.cpp |
 | llvm/lib/CodeGen/BranchFolding.h |
 | llvm/lib/CodeGen/IfConversion.cpp |
Commit
4b0aa5724feaa89a9538dcab97e018110b0e4bc3
by jyknightChange the INLINEASM_BR MachineInstr to be a non-terminating instruction.
Before this instruction supported output values, it fit fairly naturally as a terminator. However, being a terminator while also supporting outputs causes some trouble, as the physreg->vreg COPY operations cannot be in the same block.
Modeling it as a non-terminator allows it to be handled the same way as invoke is handled already.
Most of the changes here were created by auditing all the existing users of MachineBasicBlock::isEHPad() and MachineBasicBlock::hasEHPadSuccessor(), and adding calls to isInlineAsmBrIndirectTarget or mayHaveInlineAsmBr, as appropriate.
Reviewed By: nickdesaulniers, void
Differential Revision: https://reviews.llvm.org/D79794
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 | llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp |
 | llvm/test/CodeGen/ARM/ifcvt-size.mir |
 | llvm/lib/CodeGen/MachineVerifier.cpp |
 | llvm/include/llvm/Target/Target.td |
 | llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp |
 | llvm/lib/CodeGen/RegisterCoalescer.cpp |
 | llvm/lib/CodeGen/BranchFolding.cpp |
 | llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir |
 | llvm/test/CodeGen/X86/callbr-asm-instr-scheduling.ll |
 | llvm/test/CodeGen/X86/callbr-asm-outputs-pred-succ.ll |
 | llvm/lib/CodeGen/PHIEliminationUtils.cpp |
 | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp |
 | llvm/test/Verifier/callbr.ll |
 | llvm/include/llvm/CodeGen/ISDOpcodes.h |
 | llvm/lib/CodeGen/ShrinkWrap.cpp |
 | llvm/lib/CodeGen/MachineBasicBlock.cpp |
 | llvm/lib/CodeGen/SplitKit.cpp |
 | llvm/test/CodeGen/X86/shrinkwrap-callbr.ll |
 | llvm/include/llvm/CodeGen/MachineBasicBlock.h |
 | llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp |
 | llvm/lib/Target/Hexagon/BitTracker.cpp |
 | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp |
 | llvm/lib/CodeGen/MachineSink.cpp |
 | llvm/lib/CodeGen/TailDuplicator.cpp |
 | llvm/lib/CodeGen/SplitKit.h |
 | llvm/test/CodeGen/X86/callbr-asm-label-addr.ll |
 | llvm/test/CodeGen/AArch64/callbr-asm-label.ll |
 | llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp |
 | llvm/test/CodeGen/AArch64/callbr-asm-obj-file.ll |
 | llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll |
 | llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll |
 | llvm/test/CodeGen/X86/callbr-asm.ll |
 | llvm/lib/CodeGen/TargetInstrInfo.cpp |
 | llvm/test/CodeGen/X86/callbr-asm-outputs.ll |
 | llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp |
Commit
3eacfdc72f1aa3ac53eb300116f194d560053ec7
by yhs[BPF] Fix a BTF gen bug related to a pointer struct member
Currently, BTF generation stops at pointer struct members if the pointee type is a struct. This is to avoid bloating generated BTF size. The following is the process to correctly record types for these pointee struct types. - During type traversal stage, when a struct member, which is a pointer to another struct, is encountered, the pointee struct type, keyed with its name, is remembered in a Fixup map. - Later, when all type traversal is done, the Fixup map is scanned, based on struct name matching, to either resolve as pointing to a real already generated type or as a forward declaration.
Andrii discovered a bug if the struct member pointee struct is anonymous. In this case, a struct with empty name is recorded in Fixup map, and later it happens another anonymous struct with empty name is defined in BTF. So wrong type resolution happens.
To fix the problem, if the struct member pointee struct is anonymous, pointee struct type will be generated in stead of being put in Fixup map.
Differential Revision: https://reviews.llvm.org/D82976
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 | llvm/test/CodeGen/BPF/BTF/struct-anon-2.ll |
 | llvm/lib/Target/BPF/BTFDebug.cpp |