Revision
366822
by ro:
[compiler-rt][builtins] Provide __clear_cache for SPARC While working on https://reviews.llvm.org/D40900, two tests were failing since __clear_cache aborted. While libgcc's __clear_cache is just empty, this only happens because gcc (in gcc/config/sparc/sparc.c (sparc32_initialize_trampoline, sparc64_initialize_trampoline)) emits flush insns directly. The following patch mimics that. Tested on sparcv9-sun-solaris2.11. Differential Revision: https://reviews.llvm.org/D64496 |
| Change Type | Path in Repository | Path in Workspace |
|---|
 | /compiler-rt/trunk/lib/builtins/clear_cache.c (diff) | compiler-rt.src/lib/builtins/clear_cache.c |
Revision
366821
by ro:
[CMake] Add -z defs on Solaris Like other ELF targets, shared objects should be linked with -z defs on Solaris. Tested on x86_64-pc-solaris2.11 and sparcv9-sun-solaris2.11. Differential Revision: https://reviews.llvm.org/D64484 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/cmake/modules/HandleLLVMOptions.cmake (diff) | llvm.src/cmake/modules/HandleLLVMOptions.cmake |
Revision
366820
by ro:
[clang, test] Fix Clang :: Headers/max_align.c on 64-bit SPARC Clang :: Headers/max_align.c currently FAILs on 64-bit SPARC: error: 'error' diagnostics seen but not expected: File /vol/llvm/src/clang/dist/test/Headers/max_align.c Line 12: static_assert failed due to requirement '8 == _Alignof(max_align_t)' "" 1 error generated. This happens because SuitableAlign isn't defined for SPARCv9 unlike SPARCv8 (which uses the default of 64 bits). gcc's sparc/sparc.h has #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) This patch sets SuitableAlign to match and updates the corresponding testcase. Tested on sparcv9-sun-solaris2.11. Differential Revision: https://reviews.llvm.org/D64487 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /cfe/trunk/lib/Basic/Targets/Sparc.h (diff) | clang.src/lib/Basic/Targets/Sparc.h |
| /cfe/trunk/test/Preprocessor/init.c (diff) | clang.src/test/Preprocessor/init.c |
Revision
366819
by paquette:
[GlobalISel][AArch64] Teach GISel to handle shifts in load addressing modes When we select the XRO variants of loads, we can pull in very specific shifts (of the size of an element). E.g. ``` ldr x1, [x2, x3, lsl #3] ``` This teaches GISel to handle these when they're coming from shifts specifically. This adds a new addressing mode function, `selectAddrModeShiftedExtendXReg` which recognizes this pattern. This also packs this up with `selectAddrModeRegisterOffset` into `selectAddrModeXRO`. This is intended to be equivalent to `selectAddrModeXRO` in AArch64ISelDAGtoDAG. Also update load-addressing-modes to show that all of the cases here work. Differential Revision: https://reviews.llvm.org/D65119 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (diff) | llvm.src/lib/Target/AArch64/AArch64InstructionSelector.cpp |
| /llvm/trunk/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir (diff) | llvm.src/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir |
Revision
366818
by martong:
[ASTImporter] Fix inequivalence of ClassTemplateInstantiations Summary: We falsely state inequivalence if the template parameter is a qualified/nonquialified template in the first/second instantiation. Also, different kinds of TemplateName should be equal if the template decl (if available) is equal (even if the name kind is different). Reviewers: a_sidorin, a.sidorin Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D64241 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /cfe/trunk/lib/AST/ASTStructuralEquivalence.cpp (diff) | clang.src/lib/AST/ASTStructuralEquivalence.cpp |
| /cfe/trunk/unittests/AST/StructuralEquivalenceTest.cpp (diff) | clang.src/unittests/AST/StructuralEquivalenceTest.cpp |
Revision
366817
by rksimon:
[TargetLowering] SimplifyMultipleUseDemandedBits - add VECTOR_SHUFFLE support. If all the demanded elts are from one operand and are inline, then we can use the operand directly. The changes are mainly from SSE41 targets which has blendvpd but not cmpgtq, allowing the v2i64 comparison to be simplified as we only need the signbit from alternate v4i32 elements. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (diff) | llvm.src/lib/CodeGen/SelectionDAG/TargetLowering.cpp |
| /llvm/trunk/test/CodeGen/X86/midpoint-int-vec-128.ll (diff) | llvm.src/test/CodeGen/X86/midpoint-int-vec-128.ll |
| /llvm/trunk/test/CodeGen/X86/psubus.ll (diff) | llvm.src/test/CodeGen/X86/psubus.ll |
| /llvm/trunk/test/CodeGen/X86/sat-add.ll (diff) | llvm.src/test/CodeGen/X86/sat-add.ll |
| /llvm/trunk/test/CodeGen/X86/uadd_sat_vec.ll (diff) | llvm.src/test/CodeGen/X86/uadd_sat_vec.ll |
| /llvm/trunk/test/CodeGen/X86/usub_sat_vec.ll (diff) | llvm.src/test/CodeGen/X86/usub_sat_vec.ll |
| /llvm/trunk/test/CodeGen/X86/vec_minmax_sint.ll (diff) | llvm.src/test/CodeGen/X86/vec_minmax_sint.ll |
| /llvm/trunk/test/CodeGen/X86/vec_minmax_uint.ll (diff) | llvm.src/test/CodeGen/X86/vec_minmax_uint.ll |
| /llvm/trunk/test/CodeGen/X86/vector-fshl-rot-512.ll (diff) | llvm.src/test/CodeGen/X86/vector-fshl-rot-512.ll |
| /llvm/trunk/test/CodeGen/X86/vector-fshr-rot-512.ll (diff) | llvm.src/test/CodeGen/X86/vector-fshr-rot-512.ll |
| /llvm/trunk/test/CodeGen/X86/vector-reduce-smax-widen.ll (diff) | llvm.src/test/CodeGen/X86/vector-reduce-smax-widen.ll |
| /llvm/trunk/test/CodeGen/X86/vector-reduce-smax.ll (diff) | llvm.src/test/CodeGen/X86/vector-reduce-smax.ll |
| /llvm/trunk/test/CodeGen/X86/vector-reduce-smin-widen.ll (diff) | llvm.src/test/CodeGen/X86/vector-reduce-smin-widen.ll |
| /llvm/trunk/test/CodeGen/X86/vector-reduce-smin.ll (diff) | llvm.src/test/CodeGen/X86/vector-reduce-smin.ll |
| /llvm/trunk/test/CodeGen/X86/vector-reduce-umax-widen.ll (diff) | llvm.src/test/CodeGen/X86/vector-reduce-umax-widen.ll |
| /llvm/trunk/test/CodeGen/X86/vector-reduce-umax.ll (diff) | llvm.src/test/CodeGen/X86/vector-reduce-umax.ll |
| /llvm/trunk/test/CodeGen/X86/vector-reduce-umin-widen.ll (diff) | llvm.src/test/CodeGen/X86/vector-reduce-umin-widen.ll |
| /llvm/trunk/test/CodeGen/X86/vector-reduce-umin.ll (diff) | llvm.src/test/CodeGen/X86/vector-reduce-umin.ll |
| /llvm/trunk/test/CodeGen/X86/vector-trunc-packus-widen.ll (diff) | llvm.src/test/CodeGen/X86/vector-trunc-packus-widen.ll |
| /llvm/trunk/test/CodeGen/X86/vector-trunc-packus.ll (diff) | llvm.src/test/CodeGen/X86/vector-trunc-packus.ll |
| /llvm/trunk/test/CodeGen/X86/vector-trunc-ssat-widen.ll (diff) | llvm.src/test/CodeGen/X86/vector-trunc-ssat-widen.ll |
| /llvm/trunk/test/CodeGen/X86/vector-trunc-ssat.ll (diff) | llvm.src/test/CodeGen/X86/vector-trunc-ssat.ll |
| /llvm/trunk/test/CodeGen/X86/vector-trunc-usat-widen.ll (diff) | llvm.src/test/CodeGen/X86/vector-trunc-usat-widen.ll |
| /llvm/trunk/test/CodeGen/X86/vector-trunc-usat.ll (diff) | llvm.src/test/CodeGen/X86/vector-trunc-usat.ll |
Revision
366815
by vlad.tsyrklevich:
Revert "[Object/ELF.h] - Improve testing of the fields in ELFFile<ELFT>::sections()." This reverts commit r366796 because it was causing ubsan buildbot failures. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/include/llvm/Object/ELF.h (diff) | llvm.src/include/llvm/Object/ELF.h |
| /llvm/trunk/include/llvm/ObjectYAML/ELFYAML.h (diff) | llvm.src/include/llvm/ObjectYAML/ELFYAML.h |
| /llvm/trunk/test/Object/invalid.test (diff) | llvm.src/test/Object/invalid.test |
| /llvm/trunk/tools/yaml2obj/yaml2elf.cpp (diff) | llvm.src/tools/yaml2obj/yaml2elf.cpp |
Revision
366813
by gbreynoo:
[llvm-ar] Fix support for archives with members larger than 4GB llvm-ar outputs a strange error message when handling archives with members larger than 4GB due to not checking file size when passing the value as an unsigned 32 bit integer. This overflow issue caused malformed archives to be created.: https://bugs.llvm.org/show_bug.cgi?id=38058 This change allows for members above 4GB and will error in a case that is over the formats size limit, a 10 digit decimal integer. Differential Revision: https://reviews.llvm.org/D65093 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/include/llvm/Object/Archive.h (diff) | llvm.src/include/llvm/Object/Archive.h |
| /llvm/trunk/lib/Object/Archive.cpp (diff) | llvm.src/lib/Object/Archive.cpp |
| /llvm/trunk/lib/Object/ArchiveWriter.cpp (diff) | llvm.src/lib/Object/ArchiveWriter.cpp |
Revision
366811
by sammccall:
[clangd] Log version, cwd, args, and transport on startup. NFC Reviewers: hokein Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D65146 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /clang-tools-extra/trunk/clangd/tool/ClangdMain.cpp (diff) | clang-tools-extra.src/clangd/tool/ClangdMain.cpp |
Revision
366809
by sam_parker:
[ARM][LowOverheadLoops] Fix branch target codegen While lowering test.set.loop.iterations, it wasn't checked how the brcond was using the result and so the wls could branch to the loop preheader instead of not entering it. The same was true for loop.decrement.reg. So brcond and br_cc and now lowered manually when using the hwloop intrinsics. During this we now check whether the result has been negated and whether we're using SETEQ or SETNE and 0 or 1. We can then figure out which basic block the WLS and LE should be targeting. Differential Revision: https://reviews.llvm.org/D64616 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (diff) | llvm.src/lib/Target/ARM/ARMISelDAGToDAG.cpp |
| /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (diff) | llvm.src/lib/Target/ARM/ARMISelLowering.cpp |
| /llvm/trunk/lib/Target/ARM/ARMISelLowering.h (diff) | llvm.src/lib/Target/ARM/ARMISelLowering.h |
| /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (diff) | llvm.src/lib/Target/ARM/ARMInstrInfo.td |
 | /llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll | llvm.src/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll |
Revision
366808
by rksimon:
Fix MSVC warning about extending a uint32_t shift result to uint64_t. NFCI. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (diff) | llvm.src/lib/Target/AMDGPU/AMDGPUISelLowering.cpp |
Revision
366807
by rksimon:
[SLPVectorizer] Revert local change that got accidently got committed in rL366799 This wasn't part of D63281 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Transforms/Vectorize/SLPVectorizer.cpp (diff) | llvm.src/lib/Transforms/Vectorize/SLPVectorizer.cpp |
Revision
366806
by lenary:
Revert [RISCV] Re-enable rv32i-aliases-invalid.s test This reverts r366797 (git commit 53f9fec8e8b58f5a904bbfb4a1d648cde65aa860) |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/test/MC/RISCV/rv32i-aliases-invalid.s (diff) | llvm.src/test/MC/RISCV/rv32i-aliases-invalid.s |
Revision
366805
by lei:
[NFC][ASAN] Add brackets around not command Under certain execution conditions, the `not` command binds to the command the output is piped to rather than the command piping the output. In this case, that flips the return code of the FileCheck invocation, causing a failure when FileCheck succeeds. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /compiler-rt/trunk/test/asan/TestCases/Linux/read_binary_name_regtest.c (diff) | compiler-rt.src/test/asan/TestCases/Linux/read_binary_name_regtest.c |
Revision
366802
by lebedevri:
[NFC][InstCombine] Fixup commutative/negative tests with icmp preds in @llvm.umul.with.overflow tests |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/test/Transforms/InstCombine/unsigned-mul-lack-of-overflow-check-via-udiv-of-allones.ll (diff) | llvm.src/test/Transforms/InstCombine/unsigned-mul-lack-of-overflow-check-via-udiv-of-allones.ll |
| /llvm/trunk/test/Transforms/InstCombine/unsigned-mul-overflow-check-via-udiv-of-allones.ll (diff) | llvm.src/test/Transforms/InstCombine/unsigned-mul-overflow-check-via-udiv-of-allones.ll |
Revision
366801
by lebedevri:
[InstSimplify][NFC] Tests for skipping 'div-by-0' checks before inverted @llvm.umul.with.overflow It would be already handled by the non-inverted case if we were hoisting the `not` in InstCombine, but we don't (granted, we don't sink it in this case either), so this is a separate case. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/test/Transforms/InstSimplify/div-by-0-guard-before-smul_ov-not.ll | llvm.src/test/Transforms/InstSimplify/div-by-0-guard-before-smul_ov-not.ll |
| /llvm/trunk/test/Transforms/InstSimplify/div-by-0-guard-before-umul_ov-not.ll | llvm.src/test/Transforms/InstSimplify/div-by-0-guard-before-umul_ov-not.ll |
Revision
366800
by lebedevri:
[NFC][PhaseOredering][SimplifyCFG] Add more runlines to umul.with.overflow tests This way it will be more obvious that the problem is both in cost threshold and in hardcoded benefit check, plus will show how the instsimplify cleans this all in the end. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/test/Transforms/PhaseOrdering/unsigned-multiply-overflow-check.ll (diff) | llvm.src/test/Transforms/PhaseOrdering/unsigned-multiply-overflow-check.ll |
| /llvm/trunk/test/Transforms/SimplifyCFG/unsigned-multiplication-will-overflow.ll (diff) | llvm.src/test/Transforms/SimplifyCFG/unsigned-multiplication-will-overflow.ll |
Revision
366799
by rksimon:
[TargetLowering] Add SimplifyMultipleUseDemandedBits This patch introduces the DAG version of SimplifyMultipleUseDemandedBits, which attempts to peek through ops (mainly and/or/xor so far) that don't contribute to the demandedbits/elts of a node - which means we can do this even in cases where we have multiple uses of an op, which normally requires us to demanded all bits/elts. The intention is to remove a similar instruction - SelectionDAG::GetDemandedBits - once SimplifyMultipleUseDemandedBits has matured. The InstCombine version of SimplifyMultipleUseDemandedBits can constant fold which I haven't added here yet, and so far I've only wired this up to some basic binops (and/or/xor/add/sub/mul) to demonstrate its use. We do see a couple of regressions that need to be addressed: AMDGPU unsigned dot product codegen retains an AND mask (for ZERO_EXTEND) that it previously removed (but otherwise the dotproduct codegen is a lot better). X86/AVX2 has poor handling of vector ANY_EXTEND/ANY_EXTEND_VECTOR_INREG - it prematurely gets converted to ZERO_EXTEND_VECTOR_INREG. The code owners have confirmed its ok for these cases to fixed up in future patches. Differential Revision: https://reviews.llvm.org/D63281 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/include/llvm/CodeGen/TargetLowering.h (diff) | llvm.src/include/llvm/CodeGen/TargetLowering.h |
| /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (diff) | llvm.src/lib/CodeGen/SelectionDAG/TargetLowering.cpp |
| /llvm/trunk/lib/Transforms/Vectorize/SLPVectorizer.cpp (diff) | llvm.src/lib/Transforms/Vectorize/SLPVectorizer.cpp |
| /llvm/trunk/test/CodeGen/AArch64/bitfield-insert.ll (diff) | llvm.src/test/CodeGen/AArch64/bitfield-insert.ll |
| /llvm/trunk/test/CodeGen/AMDGPU/idot4s.ll (diff) | llvm.src/test/CodeGen/AMDGPU/idot4s.ll |
| /llvm/trunk/test/CodeGen/AMDGPU/idot4u.ll (diff) | llvm.src/test/CodeGen/AMDGPU/idot4u.ll |
| /llvm/trunk/test/CodeGen/AMDGPU/idot8s.ll (diff) | llvm.src/test/CodeGen/AMDGPU/idot8s.ll |
| /llvm/trunk/test/CodeGen/AMDGPU/idot8u.ll (diff) | llvm.src/test/CodeGen/AMDGPU/idot8u.ll |
| /llvm/trunk/test/CodeGen/AMDGPU/sdiv.ll (diff) | llvm.src/test/CodeGen/AMDGPU/sdiv.ll |
| /llvm/trunk/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll (diff) | llvm.src/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll |
| /llvm/trunk/test/CodeGen/X86/2012-08-07-CmpISelBug.ll (diff) | llvm.src/test/CodeGen/X86/2012-08-07-CmpISelBug.ll |
| /llvm/trunk/test/CodeGen/X86/vector-fshl-128.ll (diff) | llvm.src/test/CodeGen/X86/vector-fshl-128.ll |
| /llvm/trunk/test/CodeGen/X86/vector-reduce-mul-widen.ll (diff) | llvm.src/test/CodeGen/X86/vector-reduce-mul-widen.ll |
| /llvm/trunk/test/CodeGen/X86/vector-reduce-mul.ll (diff) | llvm.src/test/CodeGen/X86/vector-reduce-mul.ll |
Revision
366797
by lenary:
[RISCV] Re-enable rv32i-aliases-invalid.s test We were getting test failures on some builders, which pointed to @LINE being an undefined variable. I think that these failures should have been fixed by https://reviews.llvm.org/rL366434, so I'm re-enabling the test. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/test/MC/RISCV/rv32i-aliases-invalid.s (diff) | llvm.src/test/MC/RISCV/rv32i-aliases-invalid.s |
Revision
366796
by grimar:
[Object/ELF.h] - Improve testing of the fields in ELFFile<ELFT>::sections(). This eliminates a one error untested and also introduces a error for one more possible case which lead to crash previously. Differential revision: https://reviews.llvm.org/D64987 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/include/llvm/Object/ELF.h (diff) | llvm.src/include/llvm/Object/ELF.h |
| /llvm/trunk/include/llvm/ObjectYAML/ELFYAML.h (diff) | llvm.src/include/llvm/ObjectYAML/ELFYAML.h |
| /llvm/trunk/test/Object/invalid.test (diff) | llvm.src/test/Object/invalid.test |
| /llvm/trunk/tools/yaml2obj/yaml2elf.cpp (diff) | llvm.src/tools/yaml2obj/yaml2elf.cpp |
Revision
366794
by grimar:
[yaml2obj] - Add a support for defining null sections in YAMLs. ELF spec shows (Figure 4-10: Section Header Table Entry:Index 0, http://www.sco.com/developers/gabi/latest/ch4.sheader.html) that section header at index 0 (null section) can have sh_size and sh_link fields set to non-zero values. It says (https://docs.oracle.com/cd/E19683-01/817-3677/6mj8mbtc9/index.html): "If the number of sections is greater than or equal to SHN_LORESERVE (0xff00), this member has the value zero and the actual number of section header table entries is contained in the sh_size field of the section header at index 0. Otherwise, the sh_size member of the initial entry contains 0." and: "If the section name string table section index is greater than or equal to SHN_LORESERVE (0xff00), this member has the value SHN_XINDEX (0xffff) and the actual index of the section name string table section is contained in the sh_link field of the section header at index 0. Otherwise, the sh_link member of the initial entry contains 0." At this moment it is not possible to create custom section headers at index 0 using yaml2obj. This patch implements this. Differential revision: https://reviews.llvm.org/D64913 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/test/tools/yaml2obj/elf-custom-null-section.yaml | llvm.src/test/tools/yaml2obj/elf-custom-null-section.yaml |
| /llvm/trunk/tools/yaml2obj/yaml2elf.cpp (diff) | llvm.src/tools/yaml2obj/yaml2elf.cpp |
Revision
366793
by rksimon:
[SLPVectorizer] Remove null-pointer test. NFCI. cast<CallInst> shouldn't return null and we dereference the pointer in a lot of other places, causing both MSVC + cppcheck to warn about dereferenced null pointers |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Transforms/Vectorize/SLPVectorizer.cpp (diff) | llvm.src/lib/Transforms/Vectorize/SLPVectorizer.cpp |
Revision
366792
by balazske:
PlistDiagnostics Fix for compile warning (NFC). |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /cfe/trunk/lib/StaticAnalyzer/Core/PlistDiagnostics.cpp (diff) | clang.src/lib/StaticAnalyzer/Core/PlistDiagnostics.cpp |
Revision
366790
by dmgreen:
[ARM] Rename NEONModImm to VMOVModImm. NFC Rename NEONModImm to VMOVModImm as it is used in both NEON and MVE. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (diff) | llvm.src/lib/Target/ARM/ARMISelLowering.cpp |
| /llvm/trunk/lib/Target/ARM/ARMISelLowering.h (diff) | llvm.src/lib/Target/ARM/ARMISelLowering.h |
| /llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (diff) | llvm.src/lib/Target/ARM/ARMInstrFormats.td |
| /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (diff) | llvm.src/lib/Target/ARM/ARMInstrNEON.td |
| /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (diff) | llvm.src/lib/Target/ARM/Disassembler/ARMDisassembler.cpp |
| /llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h (diff) | llvm.src/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h |
| /llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp (diff) | llvm.src/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp |
| /llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h (diff) | llvm.src/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h |
Revision
366789
by uenoku:
[Attributor][NFC] Re-run clang-format on the Attributor.cpp |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Transforms/IPO/Attributor.cpp (diff) | llvm.src/lib/Transforms/IPO/Attributor.cpp |
Revision
366788
by uenoku:
[Attributor] Deduce "dereferenceable" attribute Summary: Deduce dereferenceable attribute in Attributor. These will be added in a later patch. * dereferenceable(_or_null)_globally (D61652) * Deduction based on load instruction (similar to D64258) Reviewers: jdoerfert, sstefan1 Reviewed By: jdoerfert Subscribers: hiraditya, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64876 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/include/llvm/Transforms/IPO/Attributor.h (diff) | llvm.src/include/llvm/Transforms/IPO/Attributor.h |
| /llvm/trunk/lib/Transforms/IPO/Attributor.cpp (diff) | llvm.src/lib/Transforms/IPO/Attributor.cpp |
| /llvm/trunk/test/Transforms/FunctionAttrs/arg_nocapture.ll (diff) | llvm.src/test/Transforms/FunctionAttrs/arg_nocapture.ll |
| /llvm/trunk/test/Transforms/FunctionAttrs/dereferenceable.ll | llvm.src/test/Transforms/FunctionAttrs/dereferenceable.ll |
| /llvm/trunk/test/Transforms/FunctionAttrs/noalias_returned.ll (diff) | llvm.src/test/Transforms/FunctionAttrs/noalias_returned.ll |
| /llvm/trunk/test/Transforms/FunctionAttrs/nonnull.ll (diff) | llvm.src/test/Transforms/FunctionAttrs/nonnull.ll |
Revision
366787
by evgeny777:
[llvm-objcopy] Allow strip symtab in executables and DSOs Re-commit of the patch after addressing -Wl,--emit-relocs case. Differential revision: https://reviews.llvm.org/D61672 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/test/tools/llvm-objcopy/ELF/preserve-segment-contents-ehdr-phdrs.test (diff) | llvm.src/test/tools/llvm-objcopy/ELF/preserve-segment-contents-ehdr-phdrs.test |
| /llvm/trunk/test/tools/llvm-objcopy/ELF/remove-multiple-sections.test (diff) | llvm.src/test/tools/llvm-objcopy/ELF/remove-multiple-sections.test |
| /llvm/trunk/test/tools/llvm-objcopy/ELF/segment-shift-section-remove.test (diff) | llvm.src/test/tools/llvm-objcopy/ELF/segment-shift-section-remove.test |
| /llvm/trunk/test/tools/llvm-objcopy/ELF/segment-test-remove-section.test (diff) | llvm.src/test/tools/llvm-objcopy/ELF/segment-test-remove-section.test |
| /llvm/trunk/test/tools/llvm-objcopy/ELF/strip-unneeded-all-symbols.test | llvm.src/test/tools/llvm-objcopy/ELF/strip-unneeded-all-symbols.test |
| /llvm/trunk/tools/llvm-objcopy/ELF/ELFObjcopy.cpp (diff) | llvm.src/tools/llvm-objcopy/ELF/ELFObjcopy.cpp |
| /llvm/trunk/tools/llvm-objcopy/ELF/Object.cpp (diff) | llvm.src/tools/llvm-objcopy/ELF/Object.cpp |
| /llvm/trunk/tools/llvm-objcopy/ELF/Object.h (diff) | llvm.src/tools/llvm-objcopy/ELF/Object.h |
Revision
366786
by kongyi:
Fix gold-plugin Windows build r365588 missed one instance of integer file descriptor use in gold-plugin.cpp. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/tools/gold/gold-plugin.cpp (diff) | llvm.src/tools/gold/gold-plugin.cpp |
Revision
366785
by grimar:
[yaml2elf] - Treat the SHN_UNDEF section as kind of regular section. We have a logic that adds a few sections implicitly. Though the SHT_NULL section with section number 0 is an exception. In D64913 I want to teach yaml2obj to redefine the null section. And in this patch I add it to the sections list, to make it kind of a regular section. Differential revision: https://reviews.llvm.org/D65087 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/test/tools/yaml2obj/duplicate-section-names.test (diff) | llvm.src/test/tools/yaml2obj/duplicate-section-names.test |
| /llvm/trunk/tools/yaml2obj/yaml2elf.cpp (diff) | llvm.src/tools/yaml2obj/yaml2elf.cpp |
Revision
366784
by mstorsjo:
[test] Fix the test from the previous commit when run on windows. NFC. Apparently the escaped dollar sign didn't work the same way in "echo -e" on windows buildbots. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /lld/trunk/test/COFF/Inputs/tlssup.s | lld.src/test/COFF/Inputs/tlssup.s |
| /lld/trunk/test/COFF/tls_suffix_sorting.s (diff) | lld.src/test/COFF/tls_suffix_sorting.s |
Revision
366782
by balazske:
[CrossTU] Added CTU argument to diagnostic consumer create fn. Summary: The PListDiagnosticConsumer needs a new CTU parameter that is passed through the create functions. Reviewers: NoQ, Szelethus, xazax.hun, martong Reviewed By: Szelethus Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D64635 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /cfe/trunk/include/clang/StaticAnalyzer/Core/PathDiagnosticConsumers.h (diff) | clang.src/include/clang/StaticAnalyzer/Core/PathDiagnosticConsumers.h |
| /cfe/trunk/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp (diff) | clang.src/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp |
| /cfe/trunk/lib/StaticAnalyzer/Core/PlistDiagnostics.cpp (diff) | clang.src/lib/StaticAnalyzer/Core/PlistDiagnostics.cpp |
| /cfe/trunk/lib/StaticAnalyzer/Core/SarifDiagnostics.cpp (diff) | clang.src/lib/StaticAnalyzer/Core/SarifDiagnostics.cpp |
| /cfe/trunk/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp (diff) | clang.src/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp |
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