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Changes
Summary
- [llvm-mca] Remove redundant namespace prefixes. NFC We are already "using" namespace llvm in all the files modified by this change.
- [X86][Btver2] Fix BSF/BSR schedule Double throughput to account for 2 pipes + fix BSF's latency/uop counts Match AMD Fam16h SOG + llvm-exegesis tests
- Revert r343308: [LoopInterchange] Turn into a loop pass.
- [LoopInterchange] Turn into a loop pass. This patch turns LoopInterchange into a loop pass. It now only considers top-level loops and tries to move the innermost loop to the optimal position within the loop nest. By only looking at top-level loops, we might miss a few opportunities the function pass would get (e.g. if we have a loop nest of 3 loops, in the function pass we might process loops at level 1 and 2 and move the inner most loop to level 1, and then we process loops at levels 0, 1, 2 and interchange again, because we now have a different inner loop). But I think it would be better to handle such cases by picking the best inner loop from the start and avoid re-visiting the same loops again. The biggest advantage of it being a function pass is that it interacts nicely with the other loop passes. Without this patch, there are some performance regressions on AArch64 with loop interchanging enabled, where no loops were interchanged, but we missed out on some other loop optimizations. It also removes the SimplifyCFG run. We are just changing branches, so the CFG should not be more complicated, besides the additional 'unique' preheaders this pass might create. Reviewers: chandlerc, efriedma, mcrosier, javed.absar, xbolva00 Reviewed By: xbolva00 Differential Revision: https://reviews.llvm.org/D51702
- [llvm-mca] Teach how to track zero registers in class RegisterFile. This change is in preparation for a future work on improving support for optimizable register moves. We already know if a write is from a zero-idiom, so we can propagate that bit of information to the PRF. We use an APInt mask to identify registers that are set to zero.
| Change Type | Path in Repository | Path in Workspace |
|---|---|---|
 | /llvm/trunk/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp | trunk/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp |
| /llvm/trunk/tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpp | trunk/tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpp |
| /llvm/trunk/tools/llvm-mca/lib/HardwareUnits/RetireControlUnit.cpp | trunk/tools/llvm-mca/lib/HardwareUnits/RetireControlUnit.cpp |
| /llvm/trunk/tools/llvm-mca/lib/InstrBuilder.cpp | trunk/tools/llvm-mca/lib/InstrBuilder.cpp |
| /llvm/trunk/tools/llvm-mca/lib/Instruction.cpp | trunk/tools/llvm-mca/lib/Instruction.cpp |
| /llvm/trunk/tools/llvm-mca/lib/Pipeline.cpp | trunk/tools/llvm-mca/lib/Pipeline.cpp |
| /llvm/trunk/tools/llvm-mca/lib/Stages/DispatchStage.cpp | trunk/tools/llvm-mca/lib/Stages/DispatchStage.cpp |
| /llvm/trunk/tools/llvm-mca/lib/Stages/ExecuteStage.cpp | trunk/tools/llvm-mca/lib/Stages/ExecuteStage.cpp |
| Change Type | Path in Repository | Path in Workspace |
| /llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td | trunk/lib/Target/X86/X86ScheduleBtVer2.td |
| /llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll | trunk/test/CodeGen/X86/schedule-x86_64.ll |
| /llvm/trunk/test/tools/llvm-mca/X86/BtVer2/clear-super-register-1.s | trunk/test/tools/llvm-mca/X86/BtVer2/clear-super-register-1.s |
| /llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s | trunk/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s |
| Change Type | Path in Repository | Path in Workspace |
| /llvm/trunk/lib/Transforms/IPO/PassManagerBuilder.cpp | trunk/lib/Transforms/IPO/PassManagerBuilder.cpp |
| /llvm/trunk/lib/Transforms/Scalar/LoopInterchange.cpp | trunk/lib/Transforms/Scalar/LoopInterchange.cpp |
| Change Type | Path in Repository | Path in Workspace |
| /llvm/trunk/lib/Transforms/IPO/PassManagerBuilder.cpp | trunk/lib/Transforms/IPO/PassManagerBuilder.cpp |
| /llvm/trunk/lib/Transforms/Scalar/LoopInterchange.cpp | trunk/lib/Transforms/Scalar/LoopInterchange.cpp |
| Change Type | Path in Repository | Path in Workspace |
| /llvm/trunk/tools/llvm-mca/include/HardwareUnits/RegisterFile.h | trunk/tools/llvm-mca/include/HardwareUnits/RegisterFile.h |
| /llvm/trunk/tools/llvm-mca/include/Instruction.h | trunk/tools/llvm-mca/include/Instruction.h |
| /llvm/trunk/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp | trunk/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp |
Summary
- [ARM] Prevent DSP and SIM32 being set for v6m My previous change (rL340911) set the two features for architectures >= 6, which wrongly includes v6m. Now set to >= 6 and not Cortex-M. Differential Revision: https://reviews.llvm.org/D52644
- [ClangFormat] 'try' of function-try-block doesn't obey BraceWrapping It should respond to AfterFunction, not AfterControlStatement. Fixes PR39067
- [ARM] Alter test to account for change to armv6k default CPU Review D52594 will change the default in llvm for armv6k from the non-existent cpu arm1176jf-s to mpcore. The tests in arm-cortex-cpus.c need to be updated to account for this change. Differential Revision: https://reviews.llvm.org/D52595
| Change Type | Path in Repository | Path in Workspace |
|---|---|---|
| /cfe/trunk/lib/Basic/Targets/ARM.cpp | trunk/lib/Basic/Targets/ARM.cpp |
| /cfe/trunk/test/Preprocessor/arm-acle-6.4.c | trunk/test/Preprocessor/arm-acle-6.4.c |
| Change Type | Path in Repository | Path in Workspace |
| /cfe/trunk/lib/Format/UnwrappedLineParser.cpp | trunk/lib/Format/UnwrappedLineParser.cpp |
| /cfe/trunk/unittests/Format/FormatTest.cpp | trunk/unittests/Format/FormatTest.cpp |
| Change Type | Path in Repository | Path in Workspace |
| /cfe/trunk/test/Driver/arm-cortex-cpus.c | trunk/test/Driver/arm-cortex-cpus.c |
Summary
- [docs] Fix links in Clangd documentation Add missing `_` after each `external link <https://llvm.org>`_, as required by the reStructuredText specification.
| Change Type | Path in Repository | Path in Workspace |
|---|---|---|
| /clang-tools-extra/trunk/docs/clangd.rst | trunk/docs/clangd.rst |