FailedChanges

Summary

  1. [CodeGen][AArch64] Add TargetInstrInfo hook to modify the TailDuplicateSize default threshold (details)
  2. [RISCV] Use std::make_tuple to make some toolchains happy again (details)
  3. [DAG] visitVECTOR_SHUFFLE - move shuffle legality check into MergeInnerShuffle lamda. NFCI. (details)
  4. Introduce -print-changed=[diff | diff-quiet] which show changes in patch-like format (details)
  5. AArch64: use a constpool for blockaddress(...) on MachO (details)
  6. [libc++] Add a wait step in the BuildKite pipeline to shield macOS builders (details)
  7. [AArch64AsmParser] Fix type-limits warning for VectorIndex. (details)
  8. [OpenCL] Fix pipe type printing in arg info metadata (details)
  9. [FE] Manipulate the first byte of guard variable type in both load and store operation (details)
  10. [flang][fir] Update FIR's character type. (details)
  11. [llvm-objdump] Support PLT decoding for aarch64_be (details)
  12. [ELF] Support aarch64_be (details)
  13. [LLDB] Fix `Wunused-result` warning (details)
  14. [lldb] [Process/FreeBSDRemote] Introduce mips64 support (details)
  15. [AMDGPU] Use named unified buffer format constant. NFC. (details)
  16. [RISCV] Use SplatPat/SplatPat_simm5 to handle PseudoVMV_V_X_/PseudoVMV_V_I_ selection as well. (details)
  17. [Sanitizer] Fix failing sanitizer tests (details)
  18. [RISCV] Make scalable vector FMA commutable for register allocation. (details)
  19. [ConstraintElimination] Decompose a few more GEP indices. (details)
  20. [mlir] Drop deprecated syntax for LLVM dialect types (details)
  21. [ELF] Inspect -EL & -EB for OUTPUT_FORMAT(default, big, little) (details)
  22. [RISCV] Add initial support for converting fixed vectors to scalable vectors during lowering to use RVV instructions. (details)
  23. [lld-macho] Emit personalities in compact unwind (details)
  24. [lld-macho] Emit LSDA info in compact unwind (details)
  25. [mlir][Linalg] Fix padding related bugs. (details)
  26. [RISCV] Add support for fixed vector FMA. (details)
  27. [RISCV] Add support for splat fixed length build_vectors using RVV. (details)
  28. Revert "[Utils] Add a switch controlling prefix warnings in UpdateTestChecks" (details)
  29. [GWP-ASan] Add aligned allocations. (details)
  30. [RISCV] Use _COMMUTABLE fma pseudos for fixed vectors. (details)
  31. [lld-macho] Try to make ubsan happy (details)
  32. [dfsan] Refactor visitCallBase (details)
  33. [libomptarget][amdgcn] Fix language linkage post D95300, drop use of assert (details)
  34. [flang][NFC] Update comments. (details)
Commit cd880442ae66561e45257f2440321a0a671acae7 by nicholas.guy
[CodeGen][AArch64] Add TargetInstrInfo hook to modify the TailDuplicateSize default threshold

Different targets might handle branch performance differently, so this patch allows for
targets to specify the TailDuplicateSize threshold. Said threshold defines how small a branch
can be and still be duplicated to generate straight-line code instead.
This patch also specifies said override values for the AArch64 subtarget.

Differential Revision: https://reviews.llvm.org/D95631
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was addedllvm/test/CodeGen/AArch64/aarch64-tail-dup-size.ll
The file was modifiedllvm/lib/CodeGen/MachineBlockPlacement.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.h
Commit eb8c27c60c33448e3d376971e59b8eb674e9b1de by mikael.holmen
[RISCV] Use std::make_tuple to make some toolchains happy again

My toolchain (LLVM 8.0, libstdc++ 5.4.0) complained with:

12:38:19 ../lib/Target/RISCV/RISCVISelLowering.cpp:1717:12: error: chosen constructor is explicit in copy-initialization
12:38:19     return {RISCVISD::VECREDUCE_FADD, Op.getOperand(0),
12:38:19            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
12:38:19 /proj/flexasic/app/llvm/8.0/bin/../lib/gcc/x86_64-unknown-linux-gnu/5.4.0/../../../../include/c++/5.4.0/tuple:479:19: note: explicit constructor declared here
12:38:19         constexpr tuple(_UElements&&... __elements)
12:38:19                   ^
12:38:19 ../lib/Target/RISCV/RISCVISelLowering.cpp:1720:12: error: chosen constructor is explicit in copy-initialization
12:38:19     return {RISCVISD::VECREDUCE_SEQ_FADD, Op.getOperand(1), Op.getOperand(0)};
12:38:19            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
12:38:19 /proj/flexasic/app/llvm/8.0/bin/../lib/gcc/x86_64-unknown-linux-gnu/5.4.0/../../../../include/c++/5.4.0/tuple:479:19: note: explicit constructor declared here
12:38:19         constexpr tuple(_UElements&&... __elements)
12:38:19                   ^
12:38:19 2 errors generated.

This commit adds explicit calls to std::make_tuple to work around
the problem.
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit c5c690a835524c91b2650f3d577be56bab8093d2 by llvm-dev
[DAG] visitVECTOR_SHUFFLE - move shuffle legality check into MergeInnerShuffle lamda. NFCI.

This is going to be necessary for a future reuse of MergeInnerShuffle
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 4b661b4059b0b5fa8594a0717df208a122ea15da by schmeise
Introduce -print-changed=[diff | diff-quiet] which show changes in patch-like format
Summary:
Introduce base classes that hold a textual represent of the IR
based on basic blocks and a base class for comparing this
representation.  A new change printer is introduced that uses these
classes to save and compare representations of the IR before and after
each pass.  It only reports when changes are made by a pass (similar to
-print-changed) except that the changes are shown in a patch-like format
with those lines that are removed shown in red prefixed with '-' and those
added shown in green with '+'.  This functionality was introduced in my
tutorial at the 2020 virtual developer's meeting.

Author: Jamie Schmeiser <schmeise@ca.ibm.com>
Reviewed By: aeubanks (Arthur Eubanks)
Differential Revision: https://reviews.llvm.org/D91890
The file was addedllvm/test/Other/ChangePrinters/lit.local.cfg
The file was addedllvm/test/Other/ChangePrinters/print-changed-diff.ll
The file was modifiedllvm/include/llvm/Passes/StandardInstrumentations.h
The file was modifiedllvm/lib/Passes/StandardInstrumentations.cpp
Commit c93d50dd716879a7edb2c28f4bf9d435651f3766 by Tim Northover
AArch64: use a constpool for blockaddress(...) on MachO

More MachO madness for everyone. MachO relocations are only 32-bits, which
means the ARM64_RELOC_ADDEND one only actually has 24 (signed) bits for the
actual addend. This is a problem when calculating the address of a basic block;
because it has no symbol of its own, the sequence

adrp x0, Ltmp0@PAGE
add x0, x0, x0 Ltmp0@PAGEOFF

is represented by relocation with an addend that contains the offset from the
function start to Ltmp, and so the largest function where this is guaranteed to
work is 8MB. That's not quite big enough that we can call it user error (IMO).

So this patch puts the any blockaddress into a constant-pool, where the addend
is instead stored in the (x)word being relocated, which is obviously big enough
for any function.
The file was modifiedllvm/test/CodeGen/AArch64/arm64_32.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-blockaddress.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
Commit 73aa09704a4c85b097d5fab986ead27092ecc9f7 by Louis Dionne
[libc++] Add a wait step in the BuildKite pipeline to shield macOS builders

We don't have many of those and they are rather slow, so we'd rather not run
those jobs if we know other jobs in the pipeline failed anyway.
The file was modifiedlibcxx/utils/ci/buildkite-pipeline.yml
Commit 981a38baf43929c52829aa0e635710645a31b41d by sander.desmalen
[AArch64AsmParser] Fix type-limits warning for VectorIndex.

Making VectorIndex an `int` instead of `unsigned`, silences the warning:
  comparison of unsigned expression in ‘>= 0’ is always true

in:
  template <int Min, int Max>
  DiagnosticPredicate isVectorIndex() const {
    ...
    if (VectorIndex.Val >= Min && VectorIndex.Val <= Max)
      return DiagnosticPredicateTy::Match;
    ...
  }

when Min is 0.
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
Commit ecc8ac3f081b57c25b94a69a04b3088f22a2794f by anastasia.stulova
[OpenCL] Fix pipe type printing in arg info metadata

Pipe element type spelling for arg info metadata
should follow the same behavior as normal type spelling.

We should only use the canonical type spelling in the
base type field.

This patch also removed duplication in type handling.

Tags: #clang

Differential Revision: https://reviews.llvm.org/D96151
The file was modifiedclang/test/CodeGenOpenCL/kernel-arg-info.cl
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
Commit 6b1e2fc89327a64c9300d543e00f12435c32dfcf by Xiangling.Liao
[FE] Manipulate the first byte of guard variable type in both load and store operation

As Itanium ABI[http://itanium-cxx-abi.github.io/cxx-abi/abi.html#once-ctor]
points out:

"The size of the guard variable is 64 bits. The first byte (i.e. the byte at
the address of the full variable) shall contain the value 0 prior to
initialization of the associated variable, and 1 after initialization is complete."

Differential Revision: https://reviews.llvm.org/D95822
The file was modifiedclang/test/CodeGenCXX/aix-static-init-temp-spec-and-inline-var.cpp
The file was modifiedclang/test/CodeGenCXX/aix-static-init.cpp
The file was modifiedclang/test/CodeGenCXX/cxx11-thread-local.cpp
The file was modifiedclang/lib/CodeGen/ItaniumCXXABI.cpp
The file was modifiedclang/test/CodeGenCXX/static-data-member.cpp
The file was modifiedclang/test/CodeGenCXX/global-init.cpp
Commit 7e20a413483307c2f7df327074bc0b687335f3b1 by eschweitz
[flang][fir] Update FIR's character type.

Upstream the changes made to the !fir.char type.

https://github.com/flang-compiler/f18-llvm-project/pull/269
https://github.com/flang-compiler/f18-llvm-project/pull/557

Author: Eric Schweitz, Jean Perier

Differention Revision: https://reviews.llvm.org/D96183
The file was modifiedflang/test/Fir/fir-types.fir
The file was modifiedflang/lib/Lower/ConvertType.cpp
The file was modifiedflang/lib/Lower/IO.cpp
The file was modifiedflang/lib/Optimizer/Dialect/FIRType.cpp
The file was modifiedflang/lib/Lower/IntrinsicCall.cpp
The file was modifiedflang/include/flang/Optimizer/Dialect/FIRType.h
Commit 157ac423e004961341f26c1567087b8b53770a3d by i
[llvm-objdump] Support PLT decoding for aarch64_be

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D96211
The file was modifiedllvm/test/tools/llvm-objdump/ELF/AArch64/plt.test
The file was modifiedllvm/lib/Object/ELFObjectFile.cpp
Commit 7605a9a009b5fa3bdac07e3131c8d82f6d08feb7 by i
[ELF] Support aarch64_be

This patch adds

* Big-endian values for `R_AARCH64_{ABS,PREL}{16,32,64}` and `R_AARCH64_PLT32`
* aarch64elfb & aarch64linuxb BFD emulations
* elf64-bigaarch64 output format (bfdname)

Link: https://github.com/ClangBuiltLinux/linux/issues/1288

Differential Revision: https://reviews.llvm.org/D96188
The file was modifiedlld/test/ELF/aarch64-data-relocs.s
The file was modifiedlld/test/ELF/aarch64-prel16.s
The file was modifiedlld/test/ELF/aarch64-abs32.s
The file was modifiedlld/ELF/ScriptParser.cpp
The file was modifiedlld/test/ELF/aarch64-reloc-plt32.s
The file was modifiedlld/test/ELF/aarch64-gnu-ifunc-plt.s
The file was modifiedlld/test/ELF/emulation-aarch64.s
The file was modifiedlld/ELF/Arch/AArch64.cpp
The file was modifiedlld/ELF/InputFiles.cpp
The file was modifiedlld/test/ELF/aarch64-abs16.s
The file was modifiedlld/ELF/Driver.cpp
The file was addedlld/test/ELF/lto/aarch64.ll
The file was modifiedlld/test/ELF/aarch64-prel32.s
Commit 5a63045fe78834937785ed5081052e083a98077f by frgossen
[LLDB] Fix `Wunused-result` warning
The file was modifiedlldb/source/Interpreter/CommandInterpreter.cpp
Commit 8244fc505def67f1094713202a2345f0c39d33dd by mgorny
[lldb] [Process/FreeBSDRemote] Introduce mips64 support

Introduce mips64 support to match the legacy FreeBSD plugin. Similarly
to the legacy plugin, the code does not support FPU registers at the
moment.  The support for them will be submitted separately as it
requires changes to the register context shared by both plugins.

This also includes software single-stepping support that is moved from
the Linux plugin into a common Utility class.  The FreeBSD code also
starts explicitly ignoring EINVAL from PT_CLEARSTEP since this is easier
to implement than checking whether hardware single-stepping were used.

Differential Revision: https://reviews.llvm.org/D95802
The file was addedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_mips64.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/NativeProcessLinux.h
The file was modifiedlldb/source/Plugins/Process/FreeBSDRemote/NativeThreadFreeBSD.cpp
The file was addedlldb/source/Plugins/Process/Utility/NativeProcessSoftwareSingleStep.cpp
The file was modifiedlldb/source/Plugins/Process/FreeBSDRemote/CMakeLists.txt
The file was addedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_mips64.h
The file was addedlldb/source/Plugins/Process/Utility/NativeProcessSoftwareSingleStep.h
The file was modifiedlldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp
The file was modifiedlldb/source/Plugins/Platform/FreeBSD/PlatformFreeBSD.cpp
The file was modifiedlldb/source/Plugins/Process/FreeBSDRemote/NativeProcessFreeBSD.h
The file was modifiedlldb/source/Plugins/Process/Utility/CMakeLists.txt
The file was modifiedlldb/source/Plugins/Process/FreeBSDRemote/NativeProcessFreeBSD.cpp
The file was modifiedlldb/unittests/Process/Utility/RegisterContextFreeBSDTest.cpp
Commit a4b1df8af37236935427342f0d82f83b178f0842 by jay.foad
[AMDGPU] Use named unified buffer format constant. NFC.
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Commit cc2c45dc54b324727a00be7218f387fcb53dd6c7 by craig.topper
[RISCV] Use SplatPat/SplatPat_simm5 to handle PseudoVMV_V_X_/PseudoVMV_V_I_ selection as well.

This ensures that we'll match immediates consistently regardless
of whether we match them as a standalone splat or as part of
another operation.

While I was there I added complexities to the simm5/uimm5 patterns so
we didn't have to assume that the 1 on the non-immediate was lower
than what tablegen inferred.

I had to make a minor tweak to tablegen to fix one place that
didn't expect to see a ComplexPattern that wasn't a "leaf".

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D96199
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
The file was modifiedllvm/utils/TableGen/CodeGenDAGPatterns.cpp
Commit 04af72c5423eb5ff7c0deba2d08cb46d583bb9d4 by julian.lettner
[Sanitizer] Fix failing sanitizer tests

The new pass manager was enabled by default [1].

The commit message states the following relevant differences:
  * The inliner works slightly differently
  * -O1 does some amount of inlining

These tests are affected because they specify `-O1` and then check the
reported stack trace.

[1] https://reviews.llvm.org/D95380

Differential Revision: https://reviews.llvm.org/D96198
The file was modifiedcompiler-rt/test/tsan/longjmp3.cpp
The file was modifiedcompiler-rt/test/tsan/simple_stack.c
The file was modifiedcompiler-rt/test/tsan/blacklist2.cpp
The file was modifiedcompiler-rt/test/tsan/longjmp4.cpp
The file was modifiedcompiler-rt/test/tsan/sleep_sync.cpp
The file was modifiedcompiler-rt/test/tsan/race_top_suppression.cpp
The file was modifiedcompiler-rt/test/tsan/free_race.c
The file was modifiedcompiler-rt/test/tsan/race_on_heap.cpp
The file was modifiedcompiler-rt/test/ubsan/TestCases/Misc/missing_return.cpp
Commit b7b4f4cbc3a6d2a3ea49aa47ef600271dc4fb19f by craig.topper
[RISCV] Make scalable vector FMA commutable for register allocation.

This adds support for commuting operands and converting between
vfmadd and vfmacc to avoid register copies.

To avoid messing up intrinsic behavior, I've added new pseudo
instructions that have the isCommutable flag set. These pseudos also
force a tail agnostic policy. The intrinsic version still use
the tail undisturbed policy.

For best results it looks like we need to start with fmadd and only
pick fmacc if its beneficial. MachineCSE commutes without contraining
the operands and then commutes back if it didn't help with CSE. So
I've made sure that when the operand choice isn't constrained, we
will keep fmadd for MachineCSE and when it does the second commute,
we get back the original instruction.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D95800
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.h
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrFormats.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Commit 68dc90b3472de440118e76ed2e2cd99ae593b072 by flo
[ConstraintElimination] Decompose a few more GEP indices.

This patch adds handling for zero-extended GEP indices.
The file was modifiedllvm/test/Transforms/ConstraintElimination/loops-bottom-tested-pointer-cmps.ll
The file was modifiedllvm/lib/Transforms/Scalar/ConstraintElimination.cpp
The file was modifiedllvm/test/Transforms/ConstraintElimination/gep-arithmetic.ll
The file was modifiedllvm/test/Transforms/ConstraintElimination/loops-header-tested-pointer-cmps.ll
Commit 2b92f21c6e97bd40edec71bb085b06f67e078f59 by zinenko
[mlir] Drop deprecated syntax for LLVM dialect types

After the LLVM dialect types were ported to use built-in types, the parser kept
supporting the old syntax for LLVM dialect types to produce built-in types for
compatibility. Drop this support.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D96275
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
The file was modifiedmlir/test/Dialect/LLVMIR/types-invalid.mlir
The file was modifiedmlir/test/Target/llvmir-intrinsics.mlir
The file was modifiedmlir/test/Target/openmp-llvm.mlir
Commit eea34aae2e74e9b6fbdd5b95f479bc7f397bf387 by i
[ELF] Inspect -EL & -EB for OUTPUT_FORMAT(default, big, little)

Choose big if -EB is specified, little if -EL is specified, or default if neither is specified.
The new behavior matches GNU ld.

Fixes: https://github.com/ClangBuiltLinux/linux/issues/1025

Differential Revision: https://reviews.llvm.org/D96214
The file was modifiedlld/ELF/Options.td
The file was modifiedlld/test/ELF/invalid-linkerscript.test
The file was modifiedlld/docs/ld.lld.1
The file was modifiedlld/ELF/Config.h
The file was modifiedlld/ELF/Driver.cpp
The file was modifiedlld/ELF/ScriptParser.cpp
The file was modifiedlld/test/ELF/emulation-aarch64.s
Commit a719b667a9794ec0dc820d0c5a3fd18340521ad9 by craig.topper
[RISCV] Add initial support for converting fixed vectors to scalable vectors during lowering to use RVV instructions.

This is an alternative to D95563.

This is modeled after a similar feature for AArch64's SVE that uses
predicated scalable vector instructions.a

Rather than use predication, this patch uses an explicit VL operand.
I've limited it to always use LMUL=1 for now, but we can improve this
in the future.

This requires a bunch of new ISD opcodes to carry the VL operand.
I think we can probably lower intrinsics to these ISD opcodes to
cut down on the size of the isel table. Which is why I've added
patterns for all integer/float types and not just LMUL=1.

I'm only testing one vector width right now, but the width is
programmable via the command line.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D95705
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was addedllvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.h
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
Commit 525bfa10ec1d4e3dfa3932a299cd67ffe59a5827 by jezng
[lld-macho] Emit personalities in compact unwind

Note that there is a triple indirection involved with
personalities and compact unwind:

1. Two bits of each CU encoding are used as an offset into the
   personality array.
2. Each entry of the personality array is an offset from the image base.
   The resulting address (after adding the image base) should point within the
   GOT.
3. The corresponding GOT entry contains the actual pointer to the
   personality function.

To further complicate things, when the personality function is in the
object file (as opposed to a dylib), its references in
`__compact_unwind` may refer to it via a section + offset relocation
instead of a symbol relocation. Since our GOT implementation can only
create entries for symbols, we have to create a synthetic symbol at the
given section offset.

Reviewed By: clayborg

Differential Revision: https://reviews.llvm.org/D95809
The file was removedlld/test/MachO/compact-unwind-pie.s
The file was modifiedlld/test/MachO/tools/validate-unwind-info.py
The file was addedlld/test/MachO/compact-unwind-generated.test
The file was modifiedlld/MachO/SyntheticSections.cpp
The file was modifiedlld/MachO/UnwindInfoSection.cpp
The file was modifiedlld/MachO/Writer.cpp
The file was addedlld/test/MachO/compact-unwind.s
The file was modifiedlld/MachO/UnwindInfoSection.h
The file was removedlld/test/MachO/compact-unwind.test
The file was addedlld/test/MachO/invalid/compact-unwind-personalities.s
The file was addedlld/test/MachO/invalid/compact-unwind-bad-reloc.s
Commit 51120357510949fe33cec85b088e1e8a1f46de3f by jezng
[lld-macho] Emit LSDA info in compact unwind

The LSDA pointers are encoded as offsets from the image base,
and arranged in one big contiguous array. Each second-level page records
the offset within that LSDA array which corresponds to the LSDA for its
first CU entry.

Reviewed By: clayborg

Differential Revision: https://reviews.llvm.org/D95810
The file was modifiedlld/MachO/UnwindInfoSection.h
The file was modifiedlld/test/MachO/compact-unwind.s
The file was modifiedlld/MachO/UnwindInfoSection.cpp
Commit d57a305fdf312920e38500306b7a945c341f73d9 by nicolas.vasilache
[mlir][Linalg] Fix padding related bugs.

This revision fixes the fact that the padding transformation did not have enough information to set the proper type for the padding value.
Additionally, the verifier for Yield in the presence of PadTensorOp is fixed to properly report incorrect number of results or operands. Previously, the error would be silently ignored which made the core issue difficult to debug.

Differential Revision: https://reviews.llvm.org/D96264
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/test/lib/Transforms/TestLinalgTransforms.cpp
The file was modifiedmlir/test/Dialect/Linalg/invalid.mlir
The file was modifiedmlir/test/Dialect/Linalg/tile-and-pad-tensors.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
Commit b8d719fbe81c88ec9e8c9dbe406c1b7de4c1ba05 by craig.topper
[RISCV] Add support for fixed vector FMA.

Follow up to D95705. Does not include the commuting support from D95800.

Differential Revision: https://reviews.llvm.org/D96103
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
Commit 8d8cafa32e83e9557980b9906a71d0890b860c76 by craig.topper
[RISCV] Add support for splat fixed length build_vectors using RVV.

Building on the fixed vector support from D95705

I've added ISD nodes for vmv.v.x and vfmv.v.f and switched to
lowering the intrinsics to it. This allows us to share the same
isel patterns for both.

This doesn't handle splats of i64 on RV32 yet. The build_vector
gets converted to a vXi32 build_vector+bitcast during type
legalization. Not sure the best way to handle this at the moment.

Differential Revision: https://reviews.llvm.org/D96108
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat-rv64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Commit f31ea86c808cbd841a348e35eb548b0046c8fdf7 by mtrofin
Revert "[Utils] Add a switch controlling prefix warnings in UpdateTestChecks"

This reverts commit 87f8a08ce36e5bc72f11129d2cf36b5848f86f63.
The file was modifiedllvm/utils/UpdateTestChecks/common.py
The file was modifiedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/common-label-different-bodies.test
Commit 3d8823b8e48a3f064b1e2dd52881b3ac581f6f2b by 31459023+hctim
[GWP-ASan] Add aligned allocations.

Adds a new allocation API to GWP-ASan that handles size+alignment
restrictions.

Reviewed By: cryptoad, eugenis

Differential Revision: https://reviews.llvm.org/D94830
The file was modifiedcompiler-rt/lib/gwp_asan/common.cpp
The file was modifiedcompiler-rt/lib/gwp_asan/options.inc
The file was modifiedcompiler-rt/lib/gwp_asan/CMakeLists.txt
The file was modifiedcompiler-rt/lib/gwp_asan/guarded_pool_allocator.cpp
The file was modifiedcompiler-rt/lib/gwp_asan/utilities.h
The file was modifiedcompiler-rt/lib/gwp_asan/crash_handler.cpp
The file was modifiedcompiler-rt/lib/gwp_asan/tests/crash_handler_api.cpp
The file was removedcompiler-rt/lib/gwp_asan/utilities.cpp
The file was modifiedcompiler-rt/lib/gwp_asan/tests/alignment.cpp
The file was modifiedcompiler-rt/lib/gwp_asan/common.h
The file was modifiedcompiler-rt/lib/scudo/standalone/combined.h
The file was modifiedcompiler-rt/lib/gwp_asan/tests/basic.cpp
The file was modifiedcompiler-rt/lib/gwp_asan/guarded_pool_allocator.h
Commit b49aaed8c750c8e6c4ece9a7f2b76e14b32c5484 by craig.topper
[RISCV] Use _COMMUTABLE fma pseudos for fixed vectors.

This matches what we do in the VLMAX SDNode patterns.
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
Commit ac9dd247da5a54119851cd766e4e9aa3a2be8a19 by jezng
[lld-macho] Try to make ubsan happy

Summary: We should avoid passing a null pointer to memcpy.
The file was modifiedlld/MachO/UnwindInfoSection.cpp
Commit 64b448b983b130bb59b1328473da0e9289d2e39d by jianzhouzh
[dfsan] Refactor visitCallBase

To simplify the review of https://reviews.llvm.org/D95835.

Reviewed-by: morehouse

Differential Revision: https://reviews.llvm.org/D96177
The file was modifiedllvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
Commit 2fa4186d4e1c0c5ce05efb4275f94bb7c2538dda by jonathanchesterfield
[libomptarget][amdgcn] Fix language linkage post D95300, drop use of assert
The file was modifiedopenmp/libomptarget/deviceRTLs/amdgcn/src/target_impl.hip
Commit bdf3ad582e50b06863026b72a1371353a257fc56 by eschweitz
[flang][NFC] Update comments.
The file was modifiedflang/include/flang/Optimizer/Dialect/FIRDialect.h