Started 1 mo 5 days ago
Took 5 hr 21 min on green-dragon-02

Success Build #14662 (Sep 9, 2019 10:28:44 AM)

Revisions
  • http://llvm.org/svn/llvm-project/llvm/trunk : 371427
  • http://llvm.org/svn/llvm-project/cfe/trunk : 371410
  • http://llvm.org/svn/llvm-project/compiler-rt/trunk : 371400
  • http://llvm.org/svn/llvm-project/zorg/trunk : 371154
  • http://llvm.org/svn/llvm-project/libcxx/trunk : 371324
  • http://llvm.org/svn/llvm-project/clang-tools-extra/trunk : 371422
Changes
  1. AMDGPU: Move MnemonicAlias out of instruction def hierarchy

    Unfortunately MnemonicAlias defines a "Predicates" field just like an
    instruction or pattern, with a somewhat different interpretation.

    This ends up overriding the intended Predicates set by
    PredicateControl on the pseudoinstruction defintions with an empty
    list. This allowed incorrectly selecting instructions that should have
    been rejected due to the SubtargetPredicate from patterns on the
    instruction definition.

    This does remove the divergent predicate from the 64-bit shift
    patterns, which were already not used for the 32-bit shift, so I'm not
    sure what the point was. This also removes a second, redundant copy of
    the 64-bit divergent patterns. (detail)
    by arsenm
  2. [SLP] add test for over-vectorization (PR33958); NFC (detail)
    by spatel
  3. [GlobalISel][AArch64] Handle tail calls with non-void return types

    Just return once you emit the call, which is exactly what SelectionDAG does in
    this situation.

    Update call-translator-tail-call.ll.

    Also update dllimport.ll to show that we tail call here in GISel again. Add
    -verify-machineinstrs to the GISel line too, to defend against verifier
    failures.

    Differential revision: https://reviews.llvm.org/D67282 (detail)
    by paquette
  4. AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE

    Handle the simple case that lowers to a constant. (detail)
    by arsenm
  5. AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNC

    Treat this as legal on gfx9 since it can use S_PACK_* instructions for
    this.

    This isn't used by anything yet. The same will probably apply to
    16-bit G_BUILD_VECTOR without the trunc. (detail)
    by arsenm
  6. [clangd] Attempt to fix failing Windows buildbots.

    The assertion is failing on Windows, probably because path separator is different.

    For the failure see:
    http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/28072/steps/test/logs/stdio (detail)
    by ibiryukov
  7. Revert "[MachineCopyPropagation] Remove redundant copies after TailDup via machine-cp"

    This reverts commit 371359. I'm suspecting a miscompile, I posted a
    reproducer to https://reviews.llvm.org/D65267. (detail)
    by gribozavr
  8. [yaml2obj] Simplify p_filesz/p_memsz computing

    This fixes a bug as well. When "FileSize:" (p_filesz) is specified and
    different from the actual value, the following code probably should not
    use PHeader.p_filesz:

      if (SHeader->sh_offset == PHeader.p_offset + PHeader.p_filesz)
        PHeader.p_memsz += SHeader->sh_size;

    Reviewed By: jhenderson

    Differential Revision: https://reviews.llvm.org/D67256 (detail)
    by maskray
  9. [ARM] Fix loads and stores for predicate vectors

    These predicate vectors can usually be loaded and stored with a single
    instruction, a VSTR_P0. However this instruction will store the entire P0
    predicate, 16 bits, zeroextended to 32bits. Each lane of the the
    v4i1/v8i1/v16i1 representing 4/2/1 bits.

    As far as I understand, when llvm says "store this v4i1", it really does need
    to store 4 bits (or 8, that being the size of a byte, with this bottom 4 as the
    interesting bits). For example a bitcast from a v8i1 to a i8 is defined as a
    store followed by a load, which is how the code is expanded.

    So this instead lowers the v4i1/v8i1 load/store through some shuffles to get
    the bits into the correct positions. This, as you might imagine, is not as
    efficient as a single instruction. But I believe it is needed for correctness.
    v16i1 equally should not load/store 32bits, only storing the 16bits of data.
    Stack loads/stores are still using the VSTR_P0 (as can be seen by the test not
    changing). This is fine as they are self-consistent, it is only "externally
    observable loads/stores" (from our point of view) that need to be corrected.

    Differential revision: https://reviews.llvm.org/D67085 (detail)
    by dmgreen
  10. AMDGPU/GlobalISel: Select atomic loads

    A new check for an explicitly atomic MMO is needed to avoid
    incorrectly matching pattern for non-atomic loads (detail)
    by arsenm
  11. AMDGPU/GlobalISel: Fix RegBankSelect for unaligned, uniform constant loads (detail)
    by arsenm
  12. Fix typo in comment noticed in D60295. NFCI. (detail)
    by rksimon
  13. AMDGPU/GlobalISel: Fix regbankselect for uniform extloads

    There are no scalar extloads. (detail)
    by arsenm
  14. AMDGPU: Remove code address space predicates

    Fixes 8-byte, 8-byte aligned LDS loads. 16-byte case still broken due
    to not be reported as legal. (detail)
    by arsenm
  15. AMDGPU/GlobalISel: Select G_PTR_MASK (detail)
    by arsenm
  16. AMDGPU/GlobalISel: Fix reg bank for uniform LDS loads

    The pointer is always a VGPR. Also fix hardcoding the pointer size to
    64. (detail)
    by arsenm
  17. [NFC] Add aacps bitfields access test (detail)
    by dnsampaio
  18. AMDGPU/GlobalISel: Use known bits for selection (detail)
    by arsenm
  19. [clangd] Use pre-populated mappings for standard symbols

    Summary:
    This takes ~5% of time when running clangd unit tests.

    To achieve this, move mapping of system includes out of CanonicalIncludes
    and into a separate class

    Reviewers: sammccall, hokein

    Reviewed By: sammccall

    Subscribers: MaskRay, jkorous, arphaman, kadircet, jfb, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D67172 (detail)
    by ibiryukov
  20. AMDGPU/GlobalISel: Legalize wavefrontsize intrinsic (detail)
    by arsenm
  21. AMDGPU/GlobalISel: Try generated matcher before add/sub code

    This will allow optimization patterns which fold adds away to work. (detail)
    by arsenm
  22. [ARM] Remove some spurious MVE reduction instructions.

    The family of 'dual-accumulating' vector multiply-add instructions
    (VMLADAV, VMLALDAV and VRMLALDAVH) can all operate on both signed and
    unsigned integer types, and they all have an 'exchange' variant (with
    an X in the name) that modifies which pairs of vector lanes in the two
    inputs are multiplied together. But there's a clause in the spec that
    says that the X variants //don't// operate on unsigned integer types,
    only signed. You can have X, or unsigned, or neither, but not both.

    We didn't notice that clause when we implemented the MC support for
    these instructions, so LLVM believes that things like VMLADAVX.U8 do
    exist, contradicting the spec. Here I fix that by conditioning them
    out in Tablegen.

    In order to do that, I've reversed the nesting order of the Tablegen
    multiclasses for those instructions. Previously, the innermost
    multiclass generated the X and not-X variants, and the one outside
    that generated the A and not-A variants. Now X is done by the outer
    multiclass, which allows me to bypass that one when I only want the
    two not-X variants.

    Changing the multiclass nesting order also changes the names of the
    instruction ids unless I make a special effort not to. I decided that
    while I was changing them anyway I'd make them look nicer; so now the
    instructions have names like MVE_VMLADAVs32 or MVE_VMLADAVaxs32,
    instead of cumbersome _noacc_noexch suffixes.

    The corresponding multiply-subtract instructions are unaffected. Those
    don't accept unsigned types at all, either in the spec or in LLVM.

    Reviewers: ostannard, dmgreen

    Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D67214 (detail)
    by statham
  23. AMDGPU/GlobalISel: Remove dead patterns (detail)
    by arsenm
  24. Merge note_ovl_builtin_candidate diagnostics; NFC

    There is no difference between the unary and binary case, so
    merge them. (detail)
    by svenvh
  25. [clangd] Add a new highlighting kind for typedefs

    Summary:
    We still attempt to highlight them as underlying types, but fallback to
    the generic 'typedef' highlighting kind if the underlying type is too
    complicated.

    Reviewers: hokein

    Reviewed By: hokein

    Subscribers: nridge, MaskRay, jkorous, arphaman, kadircet, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D67290 (detail)
    by ibiryukov
  26. [NFC][InstCombine] Fixup test i added in rL371352. (detail)
    by lebedevri
  27. compiler-rt: use fp_t instead of long double, for consistency

    Most builtins accepting or returning long double use the fp_t typedef.
    Change the remaining few cases to do so.

    Differential Revision: https://reviews.llvm.org/D35034 (detail)
    by emaste
  28. [DFAPacketizer] Reapply: Track resources for packetized instructions

    Reapply with fix to reduce resources required by the compiler - use
    unsigned[2] instead of std::pair. This causes clang and gcc to compile
    the generated file multiple times faster, and hopefully will reduce
    the resource requirements on Visual Studio also. This fix is a little
    ugly but it's clearly the same issue the previous author of
    DFAPacketizer faced (the previous tables use unsigned[2] rather uglily
    too).

    This patch allows the DFAPacketizer to be queried after a packet is formed to work out which
    resources were allocated to the packetized instructions.

    This is particularly important for targets that do their own bundle packing - it's not
    sufficient to know simply that instructions can share a packet; which slots are used is
    also required for encoding.

    This extends the emitter to emit a side-table containing resource usage diffs for each
    state transition. The packetizer maintains a set of all possible resource states in its
    current state. After packetization is complete, all remaining resource states are
    possible packetization strategies.

    The sidetable is only ~500K for Hexagon, but the extra tracking is disabled by default
    (most uses of the packetizer like MachinePipeliner don't care and don't need the extra
    maintained state).

    Differential Revision: https://reviews.llvm.org/D66936 (detail)
    by jamesm
  29. [Inliner][NFC] Make test less brittle.

    Summary:
    This tests inlining size thresholds, but relies on the output of running
    the full O2 pipeline, making it brittle against changes in unrelated
    passes.

    Only run the inlining pass and set thresholds on the test RUN line
    instead.

    Found while investigating D60318.

    Reviewers: RKSimon, qcolombet

    Subscribers: llvm-commits

    Tags: #llvm

    Differential Revision: https://reviews.llvm.org/D67349 (detail)
    by courbet
  30. [clang-tidy] Fix bug in bugprone-use-after-move check

    Summary:
    The bugprone-use-after-move check exhibits false positives for certain uses of
    the C++17 if/switch init statements. These false positives are caused by a bug
    in the ExprSequence calculations.

    This revision adds tests for the false positives and fixes the corresponding
    sequence calculation.

    Reviewers: gribozavr

    Subscribers: xazax.hun, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D67292 (detail)
    by ymandel
  31. [ARM][MVE] VCTP instruction selection
       
    Add codegen support for vctp{8,16,32}.

    Differential Revision: https://reviews.llvm.org/D67344 (detail)
    by sam_parker
  32. [clang-doc] sys::fs::F_None -> OF_None. NFC

    F_None, F_Text and F_Append are kept for compatibility. (detail)
    by maskray
  33. Revert rL371198 from llvm/trunk: [DFAPacketizer] Track resources for packetized instructions

    This patch allows the DFAPacketizer to be queried after a packet is formed to work out which
    resources were allocated to the packetized instructions.

    This is particularly important for targets that do their own bundle packing - it's not
    sufficient to know simply that instructions can share a packet; which slots are used is
    also required for encoding.

    This extends the emitter to emit a side-table containing resource usage diffs for each
    state transition. The packetizer maintains a set of all possible resource states in its
    current state. After packetization is complete, all remaining resource states are
    possible packetization strategies.

    The sidetable is only ~500K for Hexagon, but the extra tracking is disabled by default
    (most uses of the packetizer like MachinePipeliner don't care and don't need the extra
    maintained state).

    Differential Revision: https://reviews.llvm.org/D66936
    ........
    Reverted as this is causing "compiler out of heap space" errors on MSVC 2017/19 NDEBUG builds (detail)
    by rksimon
  34. [clangd] Support multifile edits as output of Tweaks

    Summary:
    First patch for propogating multifile changes from tweak outputs to LSP
    WorkspaceEdits.

    Uses SM to convert tooling::Replacements to TextEdits.
    Errors out if there are any inconsistencies between the draft version and the
    version generated the edits.

    Reviewers: sammccall

    Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits

    Tags: #clang

    Differential Revision: https://reviews.llvm.org/D66637 (detail)
    by kadircet

Started by timer (6 times)

This run spent:

  • 5 hr 17 min waiting;
  • 5 hr 21 min build duration;
  • 10 hr total from scheduled to completion.
Test Result (no failures)