1. [HardwareLoops] LangRef Intrinsic descriptions (details)
  2. [VE] Implements minimum MC layer for VE (3/4) (details)
  3. [gn build] Port 5921782f744 (details)
  4. Harden MLIR detection of misconfiguration when missing dialect registration (details)
  5. [DebugInfo] Upgrade DISubrange to support Fortran dynamic arrays (details)
  6. [CodeGen] Specify meaning of ISD opcodes for scalable vectors (details)
Commit 880c35a554952c3a64483502f3278431f8f06516 by sjoerd.meijer
[HardwareLoops] LangRef Intrinsic descriptions

The HardwareLoop intrinsics were missing and not described in LangRef. This
adds these descriptions/definitions.

Differential Revision:
The file was modifiedllvm/docs/LangRef.rst
Commit 5921782f744deffb5f5bfd96f6a7932a4ff75666 by simon.moll
[VE] Implements minimum MC layer for VE (3/4)

Define ELF binary code for VE and modify code where should use this new code.

Depends on D79544.

Reviewed By: jhenderson

Differential Revision:
The file was modifiedllvm/lib/Object/ELF.cpp
The file was addedllvm/unittests/Object/ELFObjectFileTest.cpp
The file was modifiedllvm/include/llvm/BinaryFormat/ELF.h
The file was modifiedllvm/lib/ObjectYAML/ELFYAML.cpp
The file was modifiedllvm/unittests/ObjectYAML/CMakeLists.txt
The file was addedllvm/unittests/Object/ELFTest.cpp
The file was addedllvm/include/llvm/BinaryFormat/ELFRelocs/VE.def
The file was addedllvm/unittests/ObjectYAML/ELFYAMLTest.cpp
The file was addedllvm/test/tools/llvm-readobj/ELF/file-header-machine-types.test
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedllvm/unittests/Object/CMakeLists.txt
The file was modifiedllvm/include/llvm/Object/ELFObjectFile.h
Commit 4b94cee650ce9753214d562826b7f1b9663c2268 by llvmgnsyncbot
[gn build] Port 5921782f744
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/Object/
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/ObjectYAML/
Commit 213c6cdf2e7a30d722cee4cd66b7d48fc396d44b by joker.eph
Harden MLIR detection of misconfiguration when missing dialect registration

This changes will catch error where C++ op are used without being
registered, either through creation with the OpBuilder or when trying to
cast to the C++ op.

Differential Revision:
The file was modifiedmlir/include/mlir/IR/MLIRContext.h
The file was modifiedmlir/lib/IR/MLIRContext.cpp
The file was modifiedmlir/include/mlir/IR/Builders.h
The file was modifiedmlir/include/mlir/IR/OpDefinition.h
Commit d20bf5a7258d4b6a7f017a81b125275dac1aa166 by SourabhSingh.Tomar
[DebugInfo] Upgrade DISubrange to support Fortran dynamic arrays

This patch upgrades DISubrange to support fortran requirements.

Below are the updates/addition of fields.
lowerBound - Now accepts signed integer or DIVariable or DIExpression,
earlier it accepted only signed integer.
upperBound - This field is now added and accepts signed interger or
DIVariable or DIExpression.
stride - This field is now added and accepts signed interger or
DIVariable or DIExpression.
This is required to describe bounds of array which are known at runtime.

unit test cases added (hand-written)
check clang
check llvm
check debug-info

Reviewed By: aprantl

Differential Revision:
The file was addedllvm/test/Bitcode/fortranSubrangeBackward.ll.bc
The file was modifiedllvm/test/Assembler/disubrange-empty-array.ll
The file was modifiedllvm/test/Bindings/llvm-c/debug_info.ll
The file was modifiedllvm/include/llvm/IR/DIBuilder.h
The file was modifiedllvm/lib/AsmParser/LLParser.cpp
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedllvm/test/DebugInfo/X86/default-subrange-array.ll
The file was modifiedllvm/unittests/IR/MetadataTest.cpp
The file was modifiedllvm/lib/IR/DebugInfoMetadata.cpp
The file was addedllvm/test/Verifier/disubrange-count-upperBound.ll
The file was addedllvm/test/DebugInfo/fortranSubrangeInt.ll
The file was addedllvm/test/Verifier/disubrange-missing-upperBound.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
The file was modifiedllvm/lib/IR/AsmWriter.cpp
The file was addedllvm/test/Bitcode/fortranSubrange.ll
The file was addedllvm/test/Verifier/invalid-disubrange-stride.ll
The file was modifiedllvm/test/Assembler/debug-info.ll
The file was modifiedllvm/lib/IR/DIBuilder.cpp
The file was addedllvm/test/Bitcode/fortranSubrangeBackward.ll
The file was modifiedllvm/lib/IR/LLVMContextImpl.h
The file was modifiedllvm/lib/Bitcode/Writer/BitcodeWriter.cpp
The file was addedllvm/test/DebugInfo/fortranDefaultLower.ll
The file was modifiedllvm/test/DebugInfo/X86/nondefault-subrange-array.ll
The file was addedllvm/test/Verifier/invalid-disubrange-lowerBound.ll
The file was modifiedllvm/include/llvm/IR/DebugInfoMetadata.h
The file was addedllvm/test/DebugInfo/fortranSubrangeExpr.ll
The file was modifiedllvm/lib/Bitcode/Reader/MetadataLoader.cpp
The file was modifiedllvm/test/Assembler/invalid-disubrange-count-missing.ll
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
The file was addedllvm/test/DebugInfo/cDefaultLower.ll
The file was addedllvm/test/DebugInfo/fortranSubrangeVar.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
The file was addedllvm/test/Verifier/invalid-disubrange-upperBound.ll
Commit ec0b66c318ea42ec229fd3a9ef4ad92bf81d41cf by sander.desmalen
[CodeGen] Specify meaning of ISD opcodes for scalable vectors

This patch contains changes to the description of EXTRACT_SUBVECTOR,
CONCAT_VECTORS to specify their behaviour for scalable vectors.

For EXTRACT_SUBVECTOR it specifies that the IDX is scaled by the
same runtime scaling as the extracted (or inserted) vector. This
definition is the most natural extension to EXTRACT_SUBVECTOR for
scalable vectors, as most use-cases that work on fixed-width types
will have the same meaning for scalable types. For legalization for
example, it is common to split the vector operation to operate on
the LO and HI halfs of a vector.

For a fixed width vector <16 x i8> this would be expressed with:

  v16i8 %res = EXTRACT_SUBVECTOR v32i8 %v, i32 16

For a scalable vector, this would similarly be expressed as:

  nxv16i8 %res = EXTRACT_SUBVECTOR nxv32i8 %V, i32 16

By extending the meaning of IDX for scalable vectors, most existing
optimisations on EXTRACT/INSERT_SUBVECTOR work for scalable vectors
without any changes. This definition also allows extracting a
fixed-width subvector from a scalable vector, which is useful to
e.g. extract the low N lanes of a scalable vector.

This patch is not NFC because it sets the meaning of these nodes
for scalable vectors, which future patches will build upon.

Reviewers: efriedma, ctetreau, rogfer01, craig.topper

Reviewed By: efriedma

Tags: #llvm

Differential Revision:
The file was modifiedllvm/include/llvm/CodeGen/ISDOpcodes.h