SuccessChanges

Summary

  1. [Attributor][NFC] Use indexes instead of iterator (details)
  2. [Attributor][NFC] Format code (details)
  3. [NFC] Fix typo and variable names (details)
  4. AMDGPU: Remove SIFixupVectorISel pass (details)
  5. AMDGPU: Correct definitions for global saddr instructions (details)
  6. AMDGPU: Remove redundant FLAT complex patterns (details)
  7. AMDGPU: Fix matching wrong offsets for global atomic loads (details)
  8. AMDGPU: Remove slc from flat offset complex patterns (details)
  9. AMDGPU: Fix global atomic saddr operand class (details)
  10. AMDGPU: Remove register class params from flat memory patterns (details)
  11. GlobalISel: Remove unnecessary llvm:: (details)
  12. [gn build] Port 79298a50670 (details)
Commit b7448a348bb863365b3d4652010a29efedd8f2e7 by clfbbn
[Attributor][NFC] Use indexes instead of iterator

When adding elements when iterating, the iterator will become
valid, which could cause errors. This fixes the issue by using
indexes instead of iterator.
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
Commit 266949b2bc0c4c4f6958664aae6d4bdd14e819b5 by clfbbn
[Attributor][NFC] Format code
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
Commit 49a944af7f1980b54d8a2be0ef640f5a956bc423 by 1894981+hiraditya
[NFC] Fix typo and variable names
The file was modifiedllvm/include/llvm/Support/AtomicOrdering.h
Commit 79298a506707a2cfcffdd7b0346322e5d90776fc by Matthew.Arsenault
AMDGPU: Remove SIFixupVectorISel pass

This was only used for matching the saddr addressing mode of global
instructions, but this was not implemented correctly. The instruction
definitions aren't even correct, and are defined as using a 64-bit
VGPR component. Eliminate this pass to enable correcting the
instruction definitions. A new matching implementation can work in
GlobalISel or relying on DAG divergence information for the base
address.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.h
The file was modifiedllvm/test/CodeGen/AMDGPU/memory_clause.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/madak.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/ds_write2st64.ll
The file was removedllvm/test/CodeGen/AMDGPU/global-load-store-atomics.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-saddr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/disable_form_clauses.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
The file was removedllvm/test/CodeGen/AMDGPU/global-saddr.ll
The file was modifiedllvm/lib/Target/AMDGPU/CMakeLists.txt
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-store.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was removedllvm/lib/Target/AMDGPU/SIFixupVectorISel.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/ds_write2.ll
Commit 47af1ac69af90f87ad6e365310db6d1e2b28be9e by Matthew.Arsenault
AMDGPU: Correct definitions for global saddr instructions

The VGPR component is a 32-bit offset, not 64-bits.

I'm not sure what the correct syntax is for this. This maintains the
vaddr position and leaves saddr in the end "off" position. This is
particularly terrible for stores, since the operand order is now <vgpr
offset>, <data>, <sgpr base>, splitting the pointer operands. I
suppose this is a logical consequence from the mistake of not putting
the data operand first. I'm not sure what sp3 does.
The file was modifiedllvm/lib/Target/AMDGPU/FLATInstructions.td
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
The file was modifiedllvm/test/CodeGen/AMDGPU/sdwa-ops.mir
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/flat_gfx9.txt
The file was modifiedllvm/test/MC/AMDGPU/flat-global.s
The file was modifiedllvm/test/MC/AMDGPU/gfx1030_new.s
Commit 8cb022982a3c64c04511dec7d1e74be00a922c31 by Matthew.Arsenault
AMDGPU: Remove redundant FLAT complex patterns

These were identical to the non-atomic cases. I'm not sure why these
were ever separated.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AMDGPU/FLATInstructions.td
Commit e5077b5c2ade470405721982f897352d611910bd by Matthew.Arsenault
AMDGPU: Fix matching wrong offsets for global atomic loads

These used signed offsets with a different size.
The file was modifiedllvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
The file was modifiedllvm/lib/Target/AMDGPU/FLATInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/global_atomics.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
Commit 625db2fe5b242cb1a0888dc5a588b2de90ceef71 by Matthew.Arsenault
AMDGPU: Remove slc from flat offset complex patterns

This was always set to 0. Use a default value of 0 in this context to
satisfy the instruction definition patterns. We can't unconditionally
use SLC with a default value of 0 due to limitations in TableGen's
handling of defaulted operands when followed by non-default operands.
The file was modifiedllvm/lib/Target/AMDGPU/FLATInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
Commit a7455652c04c927bc967d7c3f7bda90620d5d546 by Matthew.Arsenault
AMDGPU: Fix global atomic saddr operand class
The file was modifiedllvm/test/MC/AMDGPU/gfx1030_new.s
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/flat_gfx9.txt
The file was modifiedllvm/lib/Target/AMDGPU/FLATInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt
Commit f0af434b79e8b67ebcdcd1bdc526e27cd068f669 by Matthew.Arsenault
AMDGPU: Remove register class params from flat memory patterns
The file was modifiedllvm/lib/Target/AMDGPU/FLATInstructions.td
Commit 04a288f0f0205dfe4c8a20a4fdbdbe7dd19a8844 by Matthew.Arsenault
GlobalISel: Remove unnecessary llvm::
The file was modifiedllvm/lib/CodeGen/GlobalISel/Utils.cpp
Commit 160c133be5e12899e7c86af9604bddd08a9a2681 by llvmgnsyncbot
[gn build] Port 79298a50670
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn