SuccessChanges

Summary

  1. [Attributor][NFC] Add tests to range.ll (details)
  2. [X86][Driver] Remove code that forced a core2 mtune from MachO::TranslateArgs. (details)
  3. [SVE][CodeGen] Fix scalable vector issues in DAGTypeLegalizer::GenWidenVectorLoads (details)
  4. [AST] Fix a crash on mangling a binding decl from a DeclRefExpr. (details)
  5. Convert SVE macros into c++ constants and inlines (details)
Commit 21e4b9b204b4cc54a53e4fbe1e56d0828fc93d39 by okuraofvegetable
[Attributor][NFC] Add tests to range.ll

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D86128
The file was modifiedllvm/test/Transforms/Attributor/range.ll
Commit b32f203edc8579d4c0023007880293c3f9404fb7 by craig.topper
[X86][Driver] Remove code that forced a core2 mtune from MachO::TranslateArgs.

mtune was previously ignored by the compiler so I'm not sure this
did anything. But after D85384 we're starting to support mtune
and this code is now causing a couple test failures on MacOS.
The file was modifiedclang/lib/Driver/ToolChains/Darwin.cpp
Commit 3f36561f69fd62c3f96e3575835e86187889859d by david.sherwood
[SVE][CodeGen] Fix scalable vector issues in DAGTypeLegalizer::GenWidenVectorLoads

In DAGTypeLegalizer::GenWidenVectorLoads the algorithm assumes it only
ever deals with fixed width types, hence the offsets for each individual
store never take 'vscale' into account. I've changed the code in that
function to use TypeSize instead of unsigned for tracking the remaining
load amount. In addition, I've changed the load loop to use the new
IncrementPointer helper function for updating the addresses in each
iteration, since this handles scalable vector types.

Also, I've added report_fatal_errors in GenWidenVectorExtLoads,
TargetLowering::scalarizeVectorLoad and TargetLowering::scalarizeVectorStores,
since these functions currently use a sequence of element-by-element
scalar loads/stores. In a similar vein, I've also added a fatal error
report in FindMemType for the case when we decide to return the element
type for a scalable vector type.

I've added new tests in

  CodeGen/AArch64/sve-split-load.ll
  CodeGen/AArch64/sve-ld-addressing-mode-reg-imm.ll

for the changes in GenWidenVectorLoads.

Differential Revision: https://reviews.llvm.org/D85909
The file was modifiedllvm/include/llvm/Support/TypeSize.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-split-load.ll
Commit 5b797eb5b4db1e5695f314b916ab3a79f3eda1e6 by hokein.wu
[AST] Fix a crash on mangling a binding decl from a DeclRefExpr.

Differential Revision: https://reviews.llvm.org/D86130
The file was modifiedclang/test/CodeGenCXX/mangle.cpp
The file was modifiedclang/lib/AST/ItaniumMangle.cpp
Commit 090306fc80dbf3e524d0ce4a7c39e0852f0ba144 by omair.javaid
Convert SVE macros into c++ constants and inlines

This patch updates LLDB's in house version of SVE ptrace/sig macros by
converting them into constants and inlines. They are housed under sve
namespace and are used by process elf-core for reading SVE register data.

Reviewed By: labath

Differential Revision: https://reviews.llvm.org/D85641
The file was modifiedlldb/source/Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h
The file was modifiedlldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp