FailedChanges

Summary

  1. [GlobalISel] Untabify InstructionSelectorImpl.h. NFC (details)
  2. [Clang][SVE] NFC: Move info about ACLE types into separate function. (details)
  3. [X86][AVX] Fold store(extract_element(vtrunc)) to truncated store (details)
  4. [LLDB] Add ptrace register access for AArch64 SVE registers (details)
  5. [SVE] Add tests for fixed length vector integer operations with immediate operands. (details)
  6. [X86][AVX] computeKnownBitsForTargetNode - add VTRUNC/VTRUNCS/VTRUNCUS known zero upper elements handling. (details)
  7. [LLDB] Minor fix in TestSVERegisters.py for AArch64/Linux buildbot (details)
  8. [ARM] Change target triple to arm-none-none-eabi. NFC (details)
  9. [lldb] Make error messages in TestQueues more helpfull (details)
  10. [InstCombine] Lower infinite combine loop detection thresholds (details)
  11. [InstCombine] update stale comments in test files; NFC (details)
  12. [X86][AVX] getAVX512TruncNode - don't truncate from illegal vector widths. (details)
Commit 54105d635d18aa40a59230591d9f6dd255049c6c by bjorn.a.pettersson
[GlobalISel] Untabify InstructionSelectorImpl.h. NFC
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
Commit 0353848cc94f0fc23a953f8f420be7ee3342c8dc by sander.desmalen
[Clang][SVE] NFC: Move info about ACLE types into separate function.

This function returns a struct `BuiltinVectorTypeInfo` that contains
the builtin vector's element type, element count and number of vectors
(used for vector tuples).

Reviewed By: c-rhodes

Differential Revision: https://reviews.llvm.org/D86100
The file was modifiedclang/lib/CodeGen/CodeGenTypes.cpp
The file was modifiedclang/lib/AST/ASTContext.cpp
The file was modifiedclang/include/clang/AST/ASTContext.h
Commit 46fc9a0dfc0cdd092bbcbd7ca141decb74362053 by llvm-dev
[X86][AVX] Fold store(extract_element(vtrunc)) to truncated store

Add handling for storing the extracted lower (truncated bits) element from a X86ISD::VTRUNC node - this can be lowered to a generic truncated store directly.

Differential Revision: https://reviews.llvm.org/D86158
The file was modifiedllvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll
The file was modifiedllvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll
The file was modifiedllvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 567ba6c468b93accefed944e5a44b1052d3597de by omair.javaid
[LLDB] Add ptrace register access for AArch64 SVE registers

This patch adds NativeRegisterContext_arm64 ptrace routines to access
AArch64 SVE register set. This patch also adds a test-case to test
AArch64 SVE register access and dynamic size configuration capability.

Reviewed By: labath

Differential Revision: https://reviews.llvm.org/D79699
The file was addedlldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
The file was modifiedlldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
The file was modifiedlldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h
The file was addedlldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/Makefile
The file was addedlldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
The file was modifiedlldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
Commit 08ba4f112d551028c4a4f96d65774487cec35511 by paul.walker
[SVE] Add tests for fixed length vector integer operations with immediate operands.
The file was addedllvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll
Commit 80a0dc59b7a42561ac487d7e590853905164ce23 by llvm-dev
[X86][AVX] computeKnownBitsForTargetNode - add VTRUNC/VTRUNCS/VTRUNCUS known zero upper elements handling.

Like many of the AVX512 conversion ops, the VTRUNC ops guarantee the upper destination elements are zero.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
The file was modifiedllvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll
The file was modifiedllvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll
Commit bd791e97f8bb0e4bb507bf51850183515ecc6743 by omair.javaid
[LLDB] Minor fix in TestSVERegisters.py for AArch64/Linux buildbot

This adds a minor test case fix to previously submitted AArch64 SVE
ptrace support. This was failing on LLDB/AArch64 Linux buildbot.

Differential Revision: https://reviews.llvm.org/D79699
The file was modifiedlldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
Commit 41495dd57a0e98123dab997f69346468fb258965 by david.green
[ARM] Change target triple to arm-none-none-eabi. NFC
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll
Commit c1b1868f35bbb4d6e63515c00eb74d5aeac1aecc by Raphael Isemann
[lldb] Make error messages in TestQueues more helpfull
The file was modifiedlldb/test/API/macosx/queues/TestQueues.py
Commit 71e0b82c9f5039cb3987c91075e78733ef044c07 by lebedev.ri
[InstCombine] Lower infinite combine loop detection thresholds

It's been a month since 2f3862eb9f21e8a0d48505637fefe6e5e295c18c,
and no new bug reports about the threshold were filled,
so let's bump it again and wait again.
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp
Commit 92bcd240f2565a79f94e0e9ac926b9135f03cbd6 by spatel
[InstCombine] update stale comments in test files; NFC

I missed updating these with:
rG23bd33c6acc4
The file was modifiedllvm/test/Transforms/InstCombine/and-xor-or.ll
The file was modifiedllvm/test/Transforms/InstCombine/xor.ll
Commit b61cef3a921bb21ca0e2dc4b1f079a8f1a91d65e by llvm-dev
[X86][AVX] getAVX512TruncNode - don't truncate from illegal vector widths.

Thanks to @fhahn for the test case.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was addedllvm/test/CodeGen/X86/trunc-vector-width.ll