SuccessChanges

Summary

  1. [MLIR][SPIRVToLLVM] Added a hook for descriptor set / binding encoding (details)
  2. [lld-macho] Fix objc.s test (details)
  3. [gn build] Port 7394460d875 (details)
  4. [gn build] Port cf918c809bb (details)
  5. [ARM] Make MachineVerifier more strict about terminators (details)
  6. [RISCV] add the MC layer support of riscv vector Zvamo extension (details)
  7. [MLIR][GPUToSPIRV] Passing gpu module name to SPIR-V module (details)
  8. [mlir] NFC: fix trivial typo under test and tools (details)
  9. Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain" (details)
  10. [ARM] Enable outliner at -Oz for M-class (details)
  11. [Attributor] Add flag for undef value to the state of AAPotentialValues (details)
Commit e850558cdc673edc82d13e602d1c819141ce9b3f by georgemitenk0v
[MLIR][SPIRVToLLVM] Added a hook for descriptor set / binding encoding

This patch introduces a hook to encode descriptor set
and binding number into `spv.globalVariable`'s symbolic name. This
allows to preserve this information, and at the same time legalize
the global variable for the conversion to LLVM dialect.

This is required for `mlir-spirv-cpu-runner` to convert kernel
arguments into LLVM.

Also, a couple of some nits added:
- removed unused comment
- changed to a capital letter in the comment

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D86515
The file was modifiedmlir/lib/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.cpp
The file was modifiedmlir/include/mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.h
The file was modifiedmlir/test/Conversion/SPIRVToLLVM/memory-ops-to-llvm.mlir
The file was modifiedmlir/lib/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVMPass.cpp
Commit eec3500e50796865126d877889a436952238092c by jezng
[lld-macho] Fix objc.s test

Summary: It was passing on my local machine due to previously-written
files cached in the test output folder.
The file was modifiedlld/test/MachO/objc.s
Commit a6b95b287f7798ea5d40bc50f91c3bdfda63321d by llvmgnsyncbot
[gn build] Port 7394460d875
The file was modifiedllvm/utils/gn/secondary/lld/MachO/BUILD.gn
Commit 176f26f7da46c3a2f1330417d48dc43da579af78 by llvmgnsyncbot
[gn build] Port cf918c809bb
The file was modifiedllvm/utils/gn/secondary/lld/MachO/BUILD.gn
Commit a3e41d45813092c91c2ccef97afd996750241069 by sam.parker
[ARM] Make MachineVerifier more strict about terminators

Fix the ARM backend's analyzeBranch so it doesn't ignore predicated
return instructions, and make the MachineVerifier rule more strict.

Differential Revision: https://reviews.llvm.org/D40061
The file was modifiedllvm/test/CodeGen/ARM/codesize-ifcvt.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/extending-loads.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
The file was modifiedllvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir
The file was modifiedllvm/test/CodeGen/ARM/atomic-cmpxchg.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-float32regloops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-sub-sat.ll
The file was modifiedllvm/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-fabs.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-gather-tailpred.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
The file was modifiedllvm/test/CodeGen/ARM/code-placement.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-add-sat.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-retaining.mir
The file was removedllvm/test/CodeGen/ARM/sched-it-debug-nodes.mir
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-float16regloops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/constant-hoisting.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-gather-increment.ll
The file was modifiedllvm/test/DebugInfo/MIR/ARM/subregister-full-piece.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir
The file was modifiedllvm/test/CodeGen/ARM/cmpxchg-weak.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-reorder.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-pattern-fail.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir
The file was modifiedllvm/test/CodeGen/ARM/cmp-bool.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-vcmp.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir
The file was modifiedllvm/test/CodeGen/Thumb2/mve-pred-threshold.ll
The file was modifiedllvm/test/CodeGen/ARM/csr-split.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/exitcount.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir
The file was modifiedllvm/test/CodeGen/ARM/machine-sink-multidef.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-fma-loops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-selectcc.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir
The file was modifiedllvm/test/CodeGen/ARM/peephole-bitcast.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir
The file was modifiedllvm/test/CodeGen/ARM/reg_sequence.ll
The file was modifiedllvm/test/CodeGen/ARM/call-tc.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredicated-max.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/ctlz-non-zeros.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-retaining.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/basic-tail-pred.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-cond-iter-count.mir
The file was modifiedllvm/test/CodeGen/ARM/constant-islands-split-IT.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir
The file was removedllvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir
Commit 888c02deee2610682b8de5e0a8f8eb1671d71a7a by 932494295
[RISCV] add the MC layer support of riscv vector Zvamo extension

Implements the assemble and disassemble support of RISCV Vector
extension zvamo instructions, base on the 0.9 spec version.

Reviewed  by HsiangKai

Differential Revision: https://reviews.llvm.org/D85069
The file was modifiedllvm/lib/Target/RISCV/RISCVSchedRocket32.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoV.td
The file was addedllvm/test/MC/RISCV/rvv/zvamo.s
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrFormatsV.td
The file was modifiedllvm/lib/Target/RISCV/RISCVSchedRocket64.td
The file was modifiedllvm/lib/Target/RISCV/RISCV.td
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.h
Commit d48b84eb8a902a00866ef5c26dc05a7df830dbee by georgemitenk0v
[MLIR][GPUToSPIRV] Passing gpu module name to SPIR-V module

This patch allows to pass the gpu module name to SPIR-V
module during conversion. This has many benefits as we can lookup
converted to SPIR-V kernel in the symbol table.

In order to avoid symbol conflicts, `"__spv__"` is added to the
gpu module name to form the new one.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D86384
The file was modifiedmlir/test/Conversion/GPUToSPIRV/load-store.mlir
The file was modifiedmlir/test/Conversion/GPUToSPIRV/builtins.mlir
The file was modifiedmlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp
The file was modifiedmlir/test/Conversion/GPUToSPIRV/module-structure-opencl.mlir
The file was modifiedmlir/test/Conversion/GPUToSPIRV/simple.mlir
Commit a23d055912c447dcfa54049b5a06b663560e3827 by ishizaki
[mlir] NFC: fix trivial typo under test and tools

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D86648
The file was modifiedmlir/test/Transforms/test-legalizer.mlir
The file was modifiedmlir/test/lib/Transforms/TestConvertCallOp.cpp
The file was modifiedmlir/test/lib/Transforms/TestMemRefBoundCheck.cpp
The file was modifiedmlir/test/Dialect/LLVMIR/invalid.mlir
The file was modifiedmlir/test/lib/Dialect/Test/TestPatterns.cpp
The file was modifiedmlir/unittests/TableGen/OpBuildGen.cpp
The file was modifiedmlir/test/Target/llvmir-types.mlir
The file was modifiedmlir/tools/mlir-vulkan-runner/CMakeLists.txt
The file was modifiedmlir/test/Dialect/Affine/loop-tiling.mlir
The file was modifiedmlir/test/Target/llvmir.mlir
The file was modifiedmlir/test/Transforms/buffer-placement.mlir
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
The file was modifiedmlir/test/lib/Dialect/Test/TestOps.td
The file was modifiedmlir/tools/mlir-tblgen/OpInterfacesGen.cpp
The file was modifiedmlir/test/lib/IR/TestTypes.cpp
The file was modifiedmlir/integration_test/lit.cfg.py
The file was modifiedmlir/unittests/Analysis/AffineStructuresTest.cpp
The file was modifiedmlir/test/Dialect/Affine/simplify-affine-structures.mlir
The file was modifiedmlir/test/Transforms/test-merge-blocks.mlir
The file was modifiedmlir/tools/mlir-reduce/Passes/OpReducer.cpp
The file was modifiedmlir/test/Dialect/Linalg/tensors-to-buffers.mlir
The file was modifiedmlir/test/IR/pretty-attributes.mlir
The file was modifiedmlir/test/mlir-reduce/dce-test.mlir
Commit 04879086b44348cad600a0a1ccbe1f7776cc3cf9 by martin
Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain"

This reverts commit 9936455204fd6ab72715cc9d67385ddc93e072ed.

That commit caused failed assertions e.g. like this:

$ cat alloca.c
a;
b() {
  float c;
  d();
  a = __builtin_alloca(d);
  c = e();
  f(a);
  return c;
}
$ clang -target aarch64-linux-gnu -c alloca.c -O2
clang: ../lib/Target/AArch64/AArch64InstrInfo.cpp:3446: void
llvm::emitFrameOffset(llvm::MachineBasicBlock&,
llvm::MachineBasicBlock::iterator, const llvm::DebugLoc&, unsigned int,
unsigned int, llvm::StackOffset, const llvm::TargetInstrInfo*,
llvm::MachineInstr::MIFlag, bool, bool, bool*):
Assertion `(DestReg != AArch64::SP || Bytes % 16 == 0) &&
"SP increment/decrement not 16-byte aligned"' failed.
The file was modifiedllvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
The file was removedllvm/test/CodeGen/AArch64/framelayout-fp-csr.ll
The file was removedllvm/test/CodeGen/AArch64/framelayout-frame-record.mir
Commit 03141aa04acb2481652125c974bf3cfd125f4ce9 by sam.parker
[ARM] Enable outliner at -Oz for M-class

Enable default outlining when the function has the minsize attribute
and we're targeting an m-class core.

Differential Revision: https://reviews.llvm.org/D82951
The file was modifiedllvm/test/CodeGen/ARM/machine-outliner-thunk.ll
The file was modifiedllvm/lib/Target/ARM/ARMTargetMachine.cpp
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.h
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was modifiedllvm/test/CodeGen/ARM/machine-outliner-tail.ll
The file was modifiedllvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
Commit 6c25eca6142cec0695016b6fd012df56b50ee01b by okuraofvegetable
[Attributor] Add flag for undef value to the state of AAPotentialValues

Currently, an undef value is reduced to 0 when it is added to a set of potential values.
This patch introduces a flag for under values. By this, for example, we can merge two states `{undef}`, `{1}` to `{1}` (because we can reduce the undef to 1).

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D85592
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
The file was modifiedllvm/test/Transforms/Attributor/value-simplify.ll
The file was modifiedllvm/lib/Transforms/IPO/AttributorAttributes.cpp
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h
The file was modifiedllvm/test/Transforms/Attributor/potential.ll