FailedChanges

Summary

  1. fixed compiler argument (details)
Commit afcad9888264b073d5a16d0efe57792de51c2627 by kuhnel
fixed compiler argument

Otherwise MSVC would have been used...
The file was modifiedzorg/buildbot/builders/ClangBuilder.py (diff)

Summary

  1. [AMDGPU] Set DS alignment requirements to be more strict (details)
  2. [SLP] Allow reordering of vectorization trees with reused instructions. (details)
  3. Revert "[amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel." (details)
  4. emacs: Add nofree and willreturn to list of attributes (details)
  5. IR: Move denormal mode parsing from MachineFunction to Function (details)
  6. [InstSimplify] fix fmin/fmax miscompile for partial undef vectors (PR47567) (details)
  7. [mlir][StandardToSPIRV] Handle vector of i1 case for lowering zexti to SPIR-V. (details)
  8. [clangd] Add option for disabling AddUsing tweak on some namespaces. (details)
  9. [AIX] Enable large code model when building with clang (details)
  10. [DAG] BuildVectorSDNode::getSplatValue - pull out repeated getNumOperands() calls. NFCI. (details)
  11. [X86][AVX] Add missing i686 broadcastm test coverage (details)
Commit ae36c02ad0cb0a618c8715404dcfab4cf49c6612 by Mirko.Brkusanin
[AMDGPU] Set DS alignment requirements to be more strict

Alignment requirements for ds_read/write_b96/b128 for gfx9 and onward are
now the same as for other GCN subtargets. This way we can avoid any
unintentional use of these instructions on systems that do not support dword
alignment and instead require natural alignment.
This also makes 'SH_MEM_CONFIG.alignment_mode == STRICT' the default.

Differential Revision: https://reviews.llvm.org/D87821
The file was modifiedllvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/load-local.128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/ds_write2.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/load-local.96.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/store-local.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/ds_read2.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/store-local.96.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/store-local.128.ll
Commit 455ca0ebb69210046928fedffe292420a30f89ad by a.bataev
[SLP] Allow reordering of vectorization trees with reused instructions.

If some leaves have the same instructions to be vectorized, we may
incorrectly evaluate the best order for the root node (it is built for the
vector of instructions without repeated instructions and, thus, has less
elements than the root node). In this case we just can not try to reorder
the tree + we may calculate the wrong number of nodes that requre the
same reordering.
For example, if the root node is \<a+b, a+c, a+d, f+e\>, then the leaves
are \<a, a, a, f\> and \<b, c, d, e\>. When we try to vectorize the first
leaf, it will be shrink to \<a, b\>. If instructions in this leaf should
be reordered, the best order will be \<1, 0\>. We need to extend this
order for the root node. For the root node this order should look like
\<3, 0, 1, 2\>. This patch allows extension of the orders of the nodes
with the reused instructions.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D45263
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/jumbled_store_crash.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 27df1652709ba83d6b07f313297e7c796e36dce1 by Matthew.Arsenault
Revert "[amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel."

This reverts commit c3492a1aa1b98c8d81b0969d52cea7681f0624c2.

I think this is the wrong strategy and wrong place to do this
transform anyway. Also reverts follow up commit
7d593d0d6905b55ca1124fca5e4d1ebb17203138.
The file was modifiedllvm/lib/Target/AMDGPU/SIFoldOperands.cpp
The file was removedllvm/test/CodeGen/AMDGPU/sgpr-copy-cse.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wqm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fabs.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/fneg-fabs.ll
Commit 05c02eda4552076dc08ce34866b3d8ee33bbf842 by Matthew.Arsenault
emacs: Add nofree and willreturn to list of attributes
The file was modifiedllvm/utils/emacs/llvm-mode.el
Commit 751a6c5760b8de591cf241effbdad1b1cae67814 by Matthew.Arsenault
IR: Move denormal mode parsing from MachineFunction to Function

This was just inspecting the IR to begin with, and is useful to check
in some places in the IR.
The file was modifiedllvm/lib/IR/Function.cpp
The file was modifiedllvm/include/llvm/IR/Function.h
The file was modifiedllvm/lib/CodeGen/MachineFunction.cpp
Commit 3f100e64b429b6468e9a2c5b3e7ef7757a06dc48 by spatel
[InstSimplify] fix fmin/fmax miscompile for partial undef vectors (PR47567)

It would also be correct to return the variable operand in these cases,
but eliminating a variable use is probably better for optimization.
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
The file was modifiedllvm/test/Transforms/InstSimplify/fminmax-folds.ll
Commit 1909b6ac0dbc2f1306103a5ea7f5e59f2232b133 by hanchung
[mlir][StandardToSPIRV] Handle vector of i1 case for lowering zexti to SPIR-V.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D87887
The file was modifiedmlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp
Commit c894bfd1f580e5807fc98cc353b0834e0c5ddc21 by adamcz
[clangd] Add option for disabling AddUsing tweak on some namespaces.

For style guides forbid "using" declarations for namespaces like "std".
With this new config option, AddUsing can be selectively disabled on
those.

Differential Revision: https://reviews.llvm.org/D87775
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/AddUsing.cpp
The file was modifiedclang-tools-extra/clangd/ConfigYAML.cpp
The file was modifiedclang-tools-extra/clangd/unittests/TweakTests.cpp
The file was modifiedclang-tools-extra/clangd/ConfigFragment.h
The file was modifiedclang-tools-extra/clangd/Config.h
The file was modifiedclang-tools-extra/clangd/ConfigCompile.cpp
Commit 5d1f8395be94bdf6915ebeb4e51a4290c9497165 by daltenty
[AIX] Enable large code model when building with clang
The file was modifiedllvm/cmake/modules/HandleLLVMOptions.cmake
Commit d967aaa8fa801e2ed355058db98fd43e4b05edb6 by llvm-dev
[DAG] BuildVectorSDNode::getSplatValue - pull out repeated getNumOperands() calls. NFCI.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit 81dce71acfaccbeea5dfc28c4bc0431952d8d9ca by llvm-dev
[X86][AVX] Add missing i686 broadcastm test coverage
The file was modifiedllvm/test/CodeGen/X86/broadcastm-lowering.ll

Summary

  1. fixed compiler argument (details)
Commit afcad9888264b073d5a16d0efe57792de51c2627 by kuhnel
fixed compiler argument

Otherwise MSVC would have been used...
The file was modifiedzorg/buildbot/builders/ClangBuilder.py