FailedChanges

Summary

  1. [zorg] Add lldb-x86_64-debian builder Summary: Initially, the builder will be silent, because I expect noise from flaky tests. Once those have been dealt with, I'd like to switch on breakage notifications. Reviewers: jankratochvil, stella.stamenova, zturner, gkistanova Subscribers: jgorbe, lldb-commits Differential Revision: https://reviews.llvm.org/D60458
  2. Add lld to the list of dependencies for the lldb_scheduler Summary: lld is currently not on the list of dependencies for the lldb_scheduler, so lld commits are not added to the blamelist for lldb builds Reviewers: asmith, labath, gkistanova Reviewed By: gkistanova Subscribers: ruiu, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60230
  3. [green-dragon] Fix lldb-cmake-standalone warning LLVM_EXTERNAL_LIT path does not exist
  4. [LLDB] Remove all abandoned LLDB bots Summary: All of these bots have been broken for months -- in some cases years. Removing them from the waterfall. Reviewers: gkistanova, labath, serge-sans-paille, stella.stamenova, srhines Reviewed By: gkistanova, labath, stella.stamenova, srhines Subscribers: javed.absar, jdoerfert, jankratochvil, srhines, stella.stamenova, echristo, llvm-commits Differential Revision: https://reviews.llvm.org/D57911
Revision 358054 by labath:
[zorg] Add lldb-x86_64-debian builder

Summary:
Initially, the builder will be silent, because I expect noise from flaky
tests. Once those have been dealt with, I'd like to switch on breakage
notifications.

Reviewers: jankratochvil, stella.stamenova, zturner, gkistanova

Subscribers: jgorbe, lldb-commits

Differential Revision: https://reviews.llvm.org/D60458
Change TypePath in RepositoryPath in Workspace
The file was modified/zorg/trunk/buildbot/osuosl/master/config/builders.pybuildbot/osuosl/master/config/builders.py
The file was modified/zorg/trunk/buildbot/osuosl/master/config/slaves.pybuildbot/osuosl/master/config/slaves.py
The file was modified/zorg/trunk/buildbot/osuosl/master/config/status.pybuildbot/osuosl/master/config/status.py
Revision 357785 by stella.stamenova:
Add lld to the list of dependencies for the lldb_scheduler

Summary: lld is currently not on the list of dependencies for the lldb_scheduler, so lld commits are not added to the blamelist for lldb builds

Reviewers: asmith, labath, gkistanova

Reviewed By: gkistanova

Subscribers: ruiu, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60230
Change TypePath in RepositoryPath in Workspace
The file was modified/zorg/trunk/buildbot/osuosl/master/master.cfgbuildbot/osuosl/master/master.cfg
Revision 357766 by stefan.graenitz:
[green-dragon] Fix lldb-cmake-standalone warning LLVM_EXTERNAL_LIT path does not exist
Change TypePath in RepositoryPath in Workspace
The file was modified/zorg/trunk/zorg/jenkins/jobs/jobs/lldb-cmake-standalonezorg/jenkins/jobs/jobs/lldb-cmake-standalone
Revision 357721 by rnk:
[LLDB] Remove all abandoned LLDB bots

Summary: All of these bots have been broken for months -- in some cases years.  Removing them from the waterfall.

Reviewers: gkistanova, labath, serge-sans-paille, stella.stamenova, srhines

Reviewed By: gkistanova, labath, stella.stamenova, srhines

Subscribers: javed.absar, jdoerfert, jankratochvil, srhines, stella.stamenova, echristo, llvm-commits

Differential Revision: https://reviews.llvm.org/D57911
Change TypePath in RepositoryPath in Workspace
The file was modified/zorg/trunk/buildbot/osuosl/master/config/builders.pybuildbot/osuosl/master/config/builders.py
The file was modified/zorg/trunk/buildbot/osuosl/master/config/slaves.pybuildbot/osuosl/master/config/slaves.py
The file was modified/zorg/trunk/buildbot/osuosl/master/config/status.pybuildbot/osuosl/master/config/status.py
The file was modified/zorg/trunk/buildbot/osuosl/master/master.cfgbuildbot/osuosl/master/master.cfg
The file was removed/zorg/trunk/zorg/buildbot/schedulers/LLDBTriggerable.pyzorg/buildbot/schedulers/LLDBTriggerable.py

Summary

  1. llvm-undname: Fix another crash-on-invalid found by oss-fuzz
  2. [X86] Redefine KUNPCK instructions to take a narrower source register class than destination register class. Remove copies from the isel output pattern. There's no reason for the inputs to be the destination register class. This just forces an unnecessary copy in the output patterns.
  3. [X86] Put the locked mi8 instrutions above the locked mi/mi32 so they will be prefered. We want 64mi8 to be prefered over 64mi32. The order for 16mi/32mi doesn't really matter.
  4. [X86] Change IMUL with immediate instruction order to ri8 instructions come before ri/ri32 instructions. This will ensure IMUL64ri8 is tried before IMUL64ri32. For IMUL32 and IMUL16 the order doesn't really matter because only the ri8 versions use a predicate. That automatically gives them priority.
  5. [X86] Move VPTESTM matching from the isel table to custom code in X86ISelDAGToDAG. We had many tablegen patterns for these instructions. And due to the commutability of the patterns, tablegen expands them to even more patterns. All together VPTESTMD patterns accounted for more the 50K of the 610K isel table. This had gotten bad when we stopped canonicalizing AND to vXi64. This required a pattern for every combination of bitcast input type. This change moves the matching to custom code where it is easier to look through the bitcasts without being concerned with the specific types. The test changes are because we are now stricter with one use checks as its required to make load folding legal. We now require the AND and any BITCAST to only have a single use. This prevents forming VPTESTM and a VPAND with the same inputs. We now support broadcast loads for 128/256 patterns without VLX. We'll widen to 512-bit like and still fold the broadcast since the amount of memory read doesn't change. There are a few tests that got slightly longer because are now prefering load + VPTESTM over XOR+VPCMPEQ for (seteq (load), allzeros). Previously we were able to share the XOR with multiple VPTESTM instructions.
  6. [X86] Don't form masked vpcmp/vcmp/vptestm operations if the setcc node has more than one use. We're better of emitting a single compare + kand rather than a compare for the other use and a masked compare. I'm looking into using custom instruction selection for VPTESTM to reduce the ridiculous number of permutations of patterns in the isel table. Putting a one use check on all masked compare folding makes load fold matching in the custom code easier.
  7. [ConstantRange] Simplify unittests after getSetSize was removed Reviewers: lebedev.ri, nikic Reviewed By: nikic Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60662
  8. [Mem2Reg] Delete unused PointerAllocaValues It is unused after AliasSetTracker support was removed.
  9. [Mem2Reg] Simplify and micro optimize * Rearrange continu/break * BBNumbers.lookup(A) -> BBNumbers.find(A)->second BBNumbers has been computed, thus we can assume the value exists in the predicate.
  10. [Mem2Reg] Don't call LBI.deleteValue on AllocInst/DbgVariableIntrinsic Only StoreInst/LoadInst are assigned numbers. Other types of instructions are not in LBI.
  11. [Mem2Reg] Simplify rewriteSingleStoreAlloca
  12. [ConstantRange] Fix unittest after rL358347
  13. [ConstantRange] Delete unused getSetSize getSetSize returns an APInt that is 1 bit wider. The APInt is typically 65-bit and requires memory allocation. isSizeStrictlySmallerThan and isSizeLargerThan are preferred. The last use of this helper method was removed by rL302385.
  14. [X86] Update bool_reduction_v8f32 test cases from vector-compare-any_of.ll and vector-compare-all_of.ll to be proper reductions. One of the shuffles was used twice. While the intended shuffle wasn't connected.
  15. [X86] Remove some unused tablegen multiclasses. NFC
  16. [Tests] Add tests for D60659, and make adjustments to others to make diff clear Three related changes: 1) auto-gen several test files 2) Add the new tests at the bottom of said files 3) Adjust a couple of other test files not to use stores to constants when trying to test constexpr address handling
  17. [X86] Use PC-relative mode for the kernel code model Summary: The Linux kernel uses PC-relative mode, so allow that when the code model is "kernel". Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits, kees, nickdesaulniers Tags: #llvm Differential Revision: https://reviews.llvm.org/D60643
  18. [CVP] Add tests for range of with.overflow result; NFC Test range of with.overflow result in the no-overflow branch.
  19. [ConstantRange] Disallow NUW | NSW in makeGuaranteedNoWrapRegion() As motivated in D60598, this drops support for specifying both NUW and NSW in makeGuaranteedNoWrapRegion(). None of the users of this function currently make use of this. When both NUW and NSW are specified, the exact nowrap region has two disjoint parts and makeGNWR() returns one of them. This result doesn't seem to be useful for anything, but makes the semantics of the function fuzzier. Differential Revision: https://reviews.llvm.org/D60632
  20. [InstCombine] Remove redundant/bogus mul_with_overflow combines As pointed out in D60518 folding mulo(%x, undef) to {undef, undef} isn't correct. As a correct version of this already exists in InstructionSimplify (https://github.com/llvm-mirror/llvm/blob/bd8056ef326e075cc500f3f0cfcd1193bc200594/lib/Analysis/InstructionSimplify.cpp#L4750-L4757) this is just dead code though. Drop it together with the mul(%x, 0) -> {0, false} fold that is also already handled by InstSimplify. Differential Revision: https://reviews.llvm.org/D60649
  21. [X86] Use int64_t and isInt<N> instead of APInt operations in foldLoadStoreIntoMemOperand. NFC We know all our values are limited to 64 bits here so we don't need an APInt. This should save some generated code checking between large and small size.
  22. [CommandLineParser] Add DefaultOption flag Summary: Add DefaultOption flag to CommandLineParser which provides a default option or alias, but allows users to override it for some other purpose as needed. Also, add `-h` as a default alias to `-help`, which can be seamlessly overridden by applications like llvm-objdump and llvm-readobj which use `-h` as an alias for other options. Reviewers: alexfh, klimek Reviewed By: klimek Subscribers: MaskRay, mehdi_amini, inglorion, dexonsmith, hiraditya, llvm-commits, jhenderson, arphaman, cfe-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D59746
  23. [WebAssembly] Use Function::hasOptSize() (NFC) Summary: Use member function. Reviewers: aheejin Subscribers: sunfish, hiraditya, sbc100, jgravelle-google, dschuff, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60651 Patch by Hideto Ueno (uenoku)
  24. [CallingConvLower] Use SmallVectorImpl::swap
  25. [Mem2Reg] Delete unused AllocaPointerVal It is no longer used after the AliasSetTracker updating logic was removed.
  26. [ADT] Fix OwningArrayRef's move ctor
  27. [CVP] Fix inverted predicates in test; NFC Checked the wrong direction in the umul tests... fix predicated to line up with the test name.
  28. [CVP] Add tests for with.overflow used as condition; NFC
  29. [InstCombine] Canonicalize (-X srem Y) to -(X srem Y). Differential Revision: https://reviews.llvm.org/D60647
  30. [InstCombine] [NFC] add testcases for canonicalizing (-X srem Y) to -(X srem Y).
  31. [StackMaps] Update llvm-readobj to parse V3 Stackmaps This updates the StackMap parser in the llvm-readobj tool to parse version 3 StackMaps, which were bumped in https://reviews.llvm.org/D32629. Version 3 StackMaps differ in that they have a uint16 sized "location size" field which was added to the Location block in a StackMap record. The record has additional padding for alignment. This was a backwards incompatible change resulting in a StackMap version bump. Patch By: jacob.hughes@kcl.ac.uk (with a rewrite of tests by me) Differential Revision: https://reviews.llvm.org/D59020
  32. [StackMaps] Add location size to llvm-readobj -stackmap output The size field of a location can be different for each entry, so it is useful to have this displayed in the output of llvm-readobj -stackmap. Below is an example of how the output would look: Record ID: 2882400000, instruction offset: 16 3 locations: #1: Constant 1, size: 8 #2: Constant 2, size: 8 #3: Constant 3, size: 8 0 live-outs: [ ] Patch By: jacob.hughes@kcl.ac.uk (with heavy modification by me) Differential Revision: https://reviews.llvm.org/D59169
  33. [llvm-readobj] Minor style tweak for consistency sake [NFC]
  34. [StackMaps] Remove format version from the class name [NFC] Motivation is to reduce silly diffs when we change the format. For instance, this causes most of D59020 to disappear.
  35. [StackMaps] Add explicit location size accessor to the stackmap parser The reserved uint8 field in the location block of the stackmap record is used to denote the size of the location. Patch By: jacob.hughes@kcl.ac.uk Differential Revision: https://reviews.llvm.org/D59167
  36. [AArch64][GlobalISel] Enable copy elision in the pre-legalizer combine and fix a crash. This enables the simple copy combine that already exists in the CombinerHelper. However, it exposed a bug in the GISelChangeObserver where it wouldn't clear a set of MIs to process, and so would end up causing a crash when deleted MIs were being added to the combiner worklist again. Differential Revision: https://reviews.llvm.org/D60579
  37. [WebAssembly] Add DataCount section to object files Summary: This ensures that object files will continue to validate as WebAssembly modules in the presence of bulk memory operations. Engines that don't support bulk memory operations will not recognize the DataCount section and will report validation errors, but that's ok because object files aren't supposed to be run directly anyway. Reviewers: aheejin, dschuff, sbc100 Subscribers: jgravelle-google, hiraditya, sunfish, rupprecht, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60623
  38. [GlobalISel] Fix a crash when handling an invalid MVT during call lowering. This crash was introduced in r358032 as we try to construct an EVT from an MVT in order to find the register type for the calling conv. Fall back instead of trying to do this with an invalid MVT coming from i256.
  39. [MemorySSA] Add previous def to cache when found, even if trivial. Summary: When inserting a new Def, MemorySSA may be have non-minimal number of Phis. While inserting, the walk to find the previous definition may cleanup minimal Phis. When the last definition is trivial to obtain, we do not cache it. It is possible while getting the previous definition for a Def to get two different answers: - one that was straight-forward to find when walking the first path (a trivial phi in this case), and - another that follows a cleanup of the trivial phi, it determines it may need additional Phi nodes, it inserts them and returns a new phi in the same position as the former trivial one. While the Phis added for the second path are all redundant, they are not complete (the walk is only done upwards), and they are not properly cleaned up afterwards. A way to fix this problem is to cache the straight-forward answer we got on the first walk. The caching is only kept for the duration of a getPreviousDef call, and for Phis we use TrackingVH, so removing the trivial phi will lead to replacing it with the next dominating phi in the cache. Resolves PR40749. Reviewers: george.burgess.iv Subscribers: jlebar, Prazek, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60634
  40. [AArch64][GlobalISel] Fix a crash when selecting shufflevectors with an undef mask element. If a shufflevector's mask vector has an element with "undef" then the generic instruction defining that element register is a G_IMPLICT_DEF instead of G_CONSTANT. This fixes the selector to handle this case, and for now assumes that undef just means zero. In future we'll optimize this case properly.
  41. [WebAssembly] Add mutable-globals to bleeding-edge CPU Summary: This brings the backend in line with Clang. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60594
  42. [ConstantRange] Clarify makeGuaranteedNoWrapRegion() guarantees; NFC makeGuaranteedNoWrapRegion() is actually makeExactNoWrapRegion() as long as only one of NUW or NSW is specified. This is not obvious from the current documentation, and some code seems to think that it is only exact for single-element ranges. Clarify docs and add tests to be more confident this really holds. There are currently no users of makeGuaranteedNoWrapRegion() that pass both NUW and NSW. I think it would be best to drop support for this entirely and then rename the function to makeExactNoWrapRegion(). Knowing that the no-wrap region is exact is useful, because we can backwards-constrain values. What I have in mind in particular is that LVI should be able to constrain values on edges where the with.overflow overflow flag is false. Differential Revision: https://reviews.llvm.org/D60598
  43. [SCEV] Add option to forget everything in SCEV. Summary: Create a method to forget everything in SCEV. Add a cl::opt and PassManagerBuilder option to use this in LoopUnroll. Motivation: Certain Halide applications spend a very long time compiling in forgetLoop, and prefer to forget everything and rebuild SCEV from scratch. Sample difference in compile time reduction: 21.04 to 14.78 using current ToT release build. Testcase showcasing this cannot be opensourced and is fairly large. The option disabled by default, but it may be desirable to enable by default. Evidence in favor (two difference runs on different days/ToT state): File Before (s) After (s) clang-9.bc 7267.91 6639.14 llvm-as.bc 194.12 194.12 llvm-dis.bc 62.50 62.50 opt.bc 1855.85 1857.53 File Before (s) After (s) clang-9.bc 8588.70 7812.83 llvm-as.bc 196.20 194.78 llvm-dis.bc 61.55 61.97 opt.bc 1739.78 1886.26 Reviewers: sanjoy Subscribers: mehdi_amini, jlebar, zzheng, javed.absar, dmgreen, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60144
  44. [MemorySSA] Small fix for the clobber limit. Summary: After introducing the limit for clobber walking, `walkToPhiOrClobber` would assert that the limit is at least 1 on entry. The test included triggered that assert. The callsite in `tryOptimizePhi` making the calls to `walkToPhiOrClobber` is structured like this: ``` while (true) { if (getBlockingAccess()) { // calls walkToPhiOrClobber } for (...) { walkToPhiOrClobber(); } } ``` The cleanest fix is to check if the limit was reached inside `walkToPhiOrClobber`, and give an allowence of 1. This approach not make any alias() calls (no calls to instructionClobbersQuery), so the performance condition is enforced. The limit is set back to 0 if not used, as this provides info on the fact that we stopped before reaching a true clobber. Reviewers: george.burgess.iv Subscribers: jlebar, Prazek, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60479
  45. [InstCombine] Fix a nasty miscompile introduced w/masked.gather demanded elts This fixes a miscompile which was introduced in r356510 (https://reviews.llvm.org/D57372). The problem is that the original patch removed pointer operands where the load results we're demanded, but without considering the legality of the load itself. If the masked.gather had active, but undemanded, lanes, then we could end up creating a load which loaded from an undef address. The result could be a segfault, or, in theory, an arbitrary read from a random memory location into an used register.
  46. [CVP] Set NSW/NUW flags when simplifying with.overflow When CVP determines that a with.overflow intrinsic cannot overflow, it currently inserts a simple add/sub. As we already determined that there can be no overflow, we should add the appropriate NUW/NSW flag. Differential Revision: https://reviews.llvm.org/D60585
  47. [KnownBits] Add computeForAddCarry() This is for D60460. computeForAddSub() essentially already supports carries because it has to deal with subtractions. This revision extracts a lower-level computeForAddCarry() function, which allows computing the known bits for add (carry known zero), sub (carry known one) and addcarry (carry unknown). As we don't seem to have any yet, I've added a unit test file for KnownBits and exhaustive tests for the new computeForAddCarry() functionality, as well the existing computeForAddSub() function. Differential Revision: https://reviews.llvm.org/D60522
  48. [Tests] Checkin a test demonstrating a miscompile so that patch which fixes it shows a clear diff
  49. Simplify decoupling between RuntimeDyld/RuntimeDyldChecker, add 'got_addr' util. This patch reduces the number of functions in the interface between RuntimeDyld and RuntimeDyldChecker by combining "GetXAddress" and "GetXContent" functions into "GetXInfo" functions that return a struct describing both the address and content. The GetStubOffset function is also replaced with a pair of utilities, GetStubInfo and GetGOTInfo, that fit the new scheme. For RuntimeDyld both of these functions will return the same result, but for the new JITLink linker (https://reviews.llvm.org/D58704) these will provide the addresses of PLT stubs and GOT entries respectively. For JITLink's use, a 'got_addr' utility has been added to the rtdyld-check language, and the syntax of 'got_addr' and 'stub_addr' has been changed: both functions now take two arguments, a 'stub container name' and a target symbol name. For llvm-rtdyld/RuntimeDyld the stub container name is the object file name and section name, separated by a slash. E.g.: rtdyld-check: *{8}(stub_addr(foo.o/__text, y)) = y For the upcoming llvm-jitlink utility, which creates stubs on a per-file basis rather than a per-section basis, the container name is just the file name. E.g.: jitlink-check: *{8}(got_addr(foo.o, y)) = y
  50. [Hexagon] Fix reuse bug in Vector Loop Carried Reuse pass The Hexagon Vector Loop Carried Reuse pass was allowing reuse between two shufflevectors with different masks. The reason is that the masks are not instruction objects, so the code that checks each operand just skipped over the operands. This patch fixes the bug by checking if the operands are the same when they are not instruction objects. If the objects are not the same, then the code assumes that reuse cannot occur. Differential Revision: https://reviews.llvm.org/D60019
  51. [DAGCombiner] narrow shuffle of concatenated vectors // shuffle (concat X, undef), (concat Y, undef), Mask --> // concat (shuffle X, Y, Mask0), (shuffle X, Y, Mask1) The ARM changes with 'vtrn' and narrowed 'vuzp' are improvements. The x86 changes look neutral or better. There's one test with an extra instruction, but that could be reversed for a subtarget with the right attributes. But by default, we want to avoid the 256-bit op when possible (in my motivating benchmark, a handful of ymm ops sprinkled into a sequence of xmm ops are triggering frequency throttling on Haswell resulting in significantly worse perf). Differential Revision: https://reviews.llvm.org/D60545
  52. [PDB Docs] Add some prose describing public and global symbols.
  53. Add options for MaxLoadsPerMemcmp(OptSize). Reviewers: davidxl Reviewed By: davidxl Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60587
  54. [X86][SSE] Recognise vXi1 boolean anyof/allof reduction patterns Currently combineHorizontalPredicateResult only handles anyof/allof reduction patterns of legal types, which can be tricky to match as type legalization of bools can introduce bitcasts/truncs/extensions. This patch extends combineHorizontalPredicateResult to recognise vXi1 bool reductions as well and uses the existing combineBitcastvxi1 helper to create the MOVMSK necessary to then compare the signmask result. This ensures the accuracy of the reduction costs added in D60403 which assume the MOVMSK generation. Differential Revision: https://reviews.llvm.org/D60610
  55. Revert r358268 "[DebugInfo] DW_OP_deref_size in PrologEpilogInserter." It causes clang to crash while building Chromium. See https://crbug.com/952230 for reproducer. > The PrologEpilogInserter need to insert a DW_OP_deref_size before > prepending a memory location expression to an already implicit > expression to avoid having the existing expression act on the memory > address instead of the value behind it. > > The reason for using DW_OP_deref_size and not plain DW_OP_deref is that > big-endian targets need to read the right size as simply truncating a > larger read would yield the wrong result (LSB bytes are not at the lower > address). > > Differential Revision: https://reviews.llvm.org/D59687
  56. [llvm-objcopy] Fill .symtab_shndx section correctly Differential revision: https://reviews.llvm.org/D60555
  57. Use llvm::upper_bound. NFC
  58. [PowerPC] Add initialization for some ppc passes Summary: Some llc debug options need pass-name as the parameters. But if we use the pass-name ppc-early-ret, we will get below error: llc test.ll -stop-after ppc-early-ret LLVM ERROR: "ppc-early-ret" pass is not registered. Below pass-names have the pass is not registered error: ppc-ctr-loops ppc-ctr-loops-verify ppc-loop-preinc-prep ppc-toc-reg-deps ppc-vsx-copy ppc-early-ret ppc-vsx-fma-mutate ppc-vsx-swaps ppc-reduce-cr-ops ppc-qpx-load-splat ppc-branch-coalescing ppc-branch-select Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D60248
  59. [DebugInfo] Fix pr41175 Dead Store Elimination missing debug loc Bug: https://bugs.llvm.org/show_bug.cgi?id=41175 In the bug test case the DSE pass is shortening the range of memory that a memset is working on. A getelementptr is generated so that the new starting address can be passed to memset. This instruction was not given a DebugLoc. To fix the bug, copy the DebugLoc from the memset instruction. Patch by Orlando Cazalet-Hyams! Differential Revision: https://reviews.llvm.org/D60556
  60. [DebugInfo] DW_OP_deref_size in PrologEpilogInserter. The PrologEpilogInserter need to insert a DW_OP_deref_size before prepending a memory location expression to an already implicit expression to avoid having the existing expression act on the memory address instead of the value behind it. The reason for using DW_OP_deref_size and not plain DW_OP_deref is that big-endian targets need to read the right size as simply truncating a larger read would yield the wrong result (LSB bytes are not at the lower address). Differential Revision: https://reviews.llvm.org/D59687
  61. Fix missing arguments in tutorial In tutorial "8. Kaleidoscope: Compiling to Object Code" a call to TargetMachine->addPassesToEmitFile(pass, dest, FileType) is missing nullptr as its 3rd value. Patch by Sajjad Heydari! Differential revision: https://reviews.llvm.org/D60369
  62. Move getNumFrameInfos and getDwarfFrameInfos out of line and remove the MCDwarf.h include. This removes 50 transitive dependencies for a modification of MCDwarf.h in a build of llc for a pair of out of line functions and reduces the build overhead of 'touch MCDwarf.h" by 15% without impacting test time of check-llvm.
  63. Add explicit dependencies on MCSection.h and MCDwarf.h to the .cpp files rather than rely on transitive includes from MCStreamer.h.
  64. [ConstantFold] Don't evaluate FP or FP vector casts or truncations when simplifying icmp Fix PR41476
  65. Revert "[PowerPC] Add initialization for some ppc passes" This reverts commit 6f8f98ce8de7c0e4ebd7fa2e1fd9507fe8d1c317 as it is breaking nearly every bot.
  66. [llvm-readobj] Change variables' name to match LLVM-style. NFC.
  67. Move addInitialFrameState out of line and remove the MCDwarf.h include. This removes 50 transitive dependencies for a modification of MCDwarf.h in a build of llc for a single out of line function and reduces the build overhead by 20% without impacting test time of check-llvm.
  68. [TargetLowering][X86] Teach SimplifyDemandedBits to use ShrinkDemandedOp on ISD::SHL nodes. If the upper bits of the SHL result aren't used, we might be able to use a narrower shift. For example, on X86 this can turn a 64-bit into 32-bit enabling a smaller encoding. Differential Revision: https://reviews.llvm.org/D60358
  69. [PowerPC] Add initialization for some ppc passes Summary: Some llc debug options need pass-name as the parameters. But if we use the pass-name ppc-early-ret, we will get below error: llc test.ll -stop-after ppc-early-ret LLVM ERROR: "ppc-early-ret" pass is not registered. Below pass-names have the pass is not registered error: ppc-ctr-loops ppc-ctr-loops-verify ppc-loop-preinc-prep ppc-toc-reg-deps ppc-vsx-copy ppc-early-ret ppc-vsx-fma-mutate ppc-vsx-swaps ppc-reduce-cr-ops ppc-qpx-load-splat ppc-branch-coalescing ppc-branch-select Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D60248
  70. Move addFrameInst out of line and remove the MCDwarf.h include. This removes 500 transitive dependencies for a modification of MCDwarf.h in a build of llc for a single out of line function and reduces the build overhead by more than half without impacting test time of check-llvm.
  71. Include what's used in a few cpp files - these were getting transitive includes from MCDwarf.h.
  72. [PowerPC] More precise exploitation of P9 maddld instruction when operands are constant There are 3 operands of maddld, (add (mul %1, %2), %3) and sometimes they are constant. If there is constant operand, it takes extra li to materialize the operand, and one more extra register too. So it's not profitable to use maddld to optimize mul-add pattern. Differential Revision: https://reviews.llvm.org/D60181
  73. MCDwarfLineTableheader::tryGetFile : replace a loop with llvm::find Note, `DirIndex++` below is incorrect for DWARF 5, but it can be fixed later after the file index is fixed.
  74. Move a couple of optional references to just optional to make the forwarding APIs look similar.
  75. [MC] Fix typo: .symtab_shndxr -> .symtab_shndx This special section is named .symtab_shndx, according to gABI Chapter 4 Sections, and the name is used by some other tools. Though the section type SHT_SYMTAB_SHNDX is what really matters, let's fix the typo introduced in rL204769 :)
  76. Use llvm::lower_bound. NFC This reapplies rL358161. That commit inadvertently reverted an exegesis file to an old version.
  77. Remove a parameter that was being passed around that we had at the local callsite. NFC.
  78. llvm-undname: Use UNREACHABLE after exhaustive switch returning everywhere No behavior change.
  79. llvm-undname: Name a bool param, no behavior change
  80. llvm-undname: Fix out-of-bounds read on invalid intrinsic function code Found by inspection.
  81. llvm-undname: Don't crash on incomplete enum tag manglings Found by inspection.
  82. llvm-undname: Fix crash on incomplete virtual this adjusts Found by oss-fuzz. Also remove an else-after-return, this part has no behavior change.
  83. [X86AsmPrinter] refactor static functions into private methods. NFC Summary: A lot of the code for printing special cases of operands in this translation unit are static functions. While I too have suffered many years of abuse at the hands of C, we should prefer private methods, particularly when you start passing around *this as your first argument, which is a code smell. This will help make generic vs arch specific asm printing easier, as it brings X86AsmPrinter more in line with other arch's derived AsmPrinters. We will then be able to more easily move architecture generic code to the base class, and architecture specific code to the derived classes. Some other small refactorings while we're here: - the parameter Op is now consistently OpNo - add spaces around binary expressions. I know we're not millionaires but c'mon. Reviewers: echristo Reviewed By: echristo Subscribers: smeenai, hiraditya, llvm-commits, srhines, craig.topper Tags: #llvm Differential Revision: https://reviews.llvm.org/D60577
  84. llvm-undname: Fix crash on invalid name in a template parameter pointer to member arg Found by oss-fuzz.
  85. [Pipeliner] Fix incorrect loop carried dependence calculation The isLoopCarriedDep function does not correctly compute loop carried dependences when the array index offset is negative or the stride is smallar than the access size. Patch by Denis Antrushin. Differential Revision: https://reviews.llvm.org/D60135
  86. [CVP] Generate full test checks for overflows.ll; NFC
  87. [ConstantRange] Add unsignedMulMayOverflow() Same as the other ConstantRange overflow checking methods, but for unsigned mul. In this case there is no cheap overflow criterion, so using umul_ov for the implementation. Differential Revision: https://reviews.llvm.org/D60574
  88. [ConstantRangeTest] Fix typos in test names; NFC
  89. [cmake] Fix dependency issue in TableGen Summary: There is a bug in add_tablegen which causes cmake to fail with the following error message if LLVM_TABLEGEN is set. CMake Error at cmake/modules/TableGen.cmake:147 (add_dependencies): The dependency target "LLVM-tablegen-host" of target "CLANG-tablegen-host" does not exist. Call Stack (most recent call first): tools/clang/utils/TableGen/CMakeLists.txt:3 (add_tablegen) The issue happens because setting LLVM_TABLEGEN causes cmake to skip generating the LLVM-tablegen-host target. As a result, a non-existent target was added for CLANG-tablegen-host causing cmake to fail. In order to fix this issue, this patch adds a guard to check the validity of the dependency target before adding it as a dependency. Reviewers: aganea, smeenai Reviewed By: aganea Subscribers: mgorny, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60576
  90. [PGO] Better handling of profile hash mismatch We currently assume profile hash conflicts will be caught by an upfront check and we assert for the cases that escape the check. The assumption is not always true as there are chances of conflict. This patch prints a warning and skips annotating the function for the escaped cases,. Differential Revision: https://reviews.llvm.org/D60154
  91. [AArch64][GlobalISel] Flesh out vector load/store support for more types. Some of these were legalizing into smaller vector types unnecessarily, others were simply not supported yet.
  92. [AArch64][GlobalISel] Legalization and ISel support for load/stores of vectors of pointers. Loads and store of values with type like <2 x p0> currently don't get imported because SelectionDAG has no knowledge of pointer types. To leverage the existing support for vector load/stores, we can bitcast the value to have s64 element types instead. We do this as a custom legalization. This patch also adds support for general loads of <2 x s64>, and relaxes some type conditions on selecting G_BITCAST. Differential Revision: https://reviews.llvm.org/D60534
  93. [DebugInfo] Combine Trivial and NonTrivial flags Summary: Companion to https://reviews.llvm.org/D59347 Reviewers: rnk, zturner, probinson, dblaikie, deadalnix Subscribers: aprantl, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59348
  94. [X86] Restrict vselect handling in scalarizeExtEltFP to only case to pre type legalization where the setcc result type is vXi1. If the vector setcc has been legalized then we will need to convert a vector boolean of 0 or -1 to a scalar boolean of 0 or 1. The added test case previously crashed in 32-bit mode by creating a setcc with an i64 condition that type legalization couldn't expand.
  95. [X86] Add 32-bit command line to extractelement-fp.ll so I can add a test case for a 32-bit only crasher. NFC This is a bit ugly for ABI reasons about how floats/doubles are returned.
  96. [X86] Add patterns for using movss/movsd for atomic load/store of f32/64. Remove atomic fadd pseudos use isel patterns instead. This patch adds patterns for turning bitcasted atomic load/store into movss/sd. It also removes the pseudo instructions for atomic RMW fadd. Instead just adding isel patterns for folding an atomic load into addss/sd. And relying on the new movss/sd store pattern to handle the write part. This also makes the fadd patterns use VEX and EVEX instructions when AVX or AVX512F are enabled. Differential Revision: https://reviews.llvm.org/D60394
  97. Recommit r358211 "[X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87, but no SSE2" With correct test checks this time. If we have X87, but not SSE2 we can atomicaly load an i64 value into the significand of an 80-bit extended precision x87 register using fild. We can then use a fist instruction to convert it back to an i64 integ This matches what gcc and icc do for this case and removes an existing FIXME.
  98. Revert r358211 "[X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87, but no SSE2" I seem to have messed up the test checks.
  99. [X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87, but no SSE2 If we have X87, but not SSE2 we can atomicaly load an i64 value into the significand of an 80-bit extended precision x87 register using fild. We can then use a fist instruction to convert it back to an i64 integer and store it to a stack temporary. From there we can do two 32-bit loads to get the value into integer registers without worrying about atomicness. This matches what gcc and icc do for this case and removes an existing FIXME. Differential Revision: https://reviews.llvm.org/D60156
  100. [X86] Pre-commit i64 volatile test case for D60156. NFC
  101. Revert "Use llvm::lower_bound. NFC" This reverts commit rL358161. This patch have broken the test: llvm/test/tools/llvm-exegesis/X86/uops-CMOV16rm-noreg.s
  102. Fix sphinx documentation warning.
  103. [PDB Docs] Add skeleton of documentation for CodeView symbols.
  104. New document skeleton describing how to add a constrained floating-point intrinsic. Reviewed by: andrew.w.kaylor, cameron.mcinally Differential Revision: https://reviews.llvm.org/D59833
  105. [ConstantFold] ExtractConstantBytes - handle shifts on large integer types Use APInt instead of getZExtValue from the ConstantInt until we can confirm that the shift amount is in range. Reduced from OSS-Fuzz #14169 - https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=14169
  106. [DAGCombiner] refactor narrowing of extracted vector binop; NFC There's a TODO comment about handling patterns with insert_subvector, and we do want to match that.
  107. [X86] SimplifyDemandedVectorElts - add X86ISD::VPERMV3 mask support Completes SimplifyDemandedVectorElts's basic variable shuffle mask support which should help D60512 + D60562
  108. Make llvm-nm -help great again Only display help from the llvm-nm category instead of all llvm options, which make it much more usable. There's still an issue with -s, which is probably a bug in llvm::cl and worth another commit. Differential Revision: https://reviews.llvm.org/D60411
  109. [RISCV] Diagnose invalid second input register operand when using %tprel_add RISCVMCCodeEmitter::expandAddTPRel asserts that the second operand must be x4/tp. As we are not currently checking this in the RISCVAsmParser, the assert is easy to trigger due to wrong assembly input. This patch does a late check of this constraint. An alternative could be using a singleton register class for x4/tp similar to the current one for sp. Unfortunately it does not result in a good diagnostic. Because add is an overloaded mnemonic, if no matching is possible, the diagnostic of the first failing alternative seems to be used as the diagnostic itself. This means that this case the %tprel_add is diagnosed as an invalid operand (because the real add instruction only has 3 operands). Differential Revision: https://reviews.llvm.org/D60528
  110. [X86][AVX] Tweak X86ISD::VPERMV3 demandedelts test Original test was too dependent on the order of the combines that could cause the inserted element being demanded after all
  111. [X86] Add MM register mapping from CodeView to MC register id Differential Revision: https://reviews.llvm.org/D60437 Change-Id: I2183a6d825d0284b22705d423b88882992b236c5
  112. [llvm] [lit] Add target-x86* features Add a 'target-x86' and 'target-x86_64' feature sthat indicates that the default target is 32-bit or 64-bit x86, appropriately. Combined with 'native' feature, we're going to use this to control x86-specific LLDB native process tests. Differential Revision: https://reviews.llvm.org/D60474
  113. YAMLIO: Fix serialization of strings with embedded nuls Summary: A bug/typo in Output::scalarString caused us to round-trip a StringRef through a const char *. This meant that any strings with embedded nuls were unintentionally cut short at the first such character. (It also could have caused accidental buffer overruns, but it seems that all StringRefs coming into this functions were formed from null-terminated strings.) This patch fixes the bug and adds an appropriate test. Reviewers: sammccall, jhenderson Subscribers: kristina, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60505
  114. [X86][AVX] Add X86ISD::VPERMV3 demandedelts test
  115. [X86] SimplifyDemandedVectorElts - add X86ISD::VPERMV mask support
  116. [X86][AVX] Add X86ISD::VPERMV demandedelts test
  117. [DAGCombiner][x86] scalarize inserted vector FP ops // bo (build_vec ...undef, x, undef...), (build_vec ...undef, y, undef...) --> // build_vec ...undef, (bo x, y), undef... The lifetime of the nodes in these examples is different for variables versus constants, but they are all build vectors briefly, so I'm proposing to catch them in this form to handle all of the leading examples in the motivating test file. Before we have build vectors, we might have insert_vector_element. After that, we might have scalar_to_vector and constant pool loads. It's going to take more work to ensure that FP vector operands are getting simplified with undef elements, so this transform can apply more widely. In a non-loose FP environment, we are likely simplifying FP elements to NaN values rather than undefs. We also need to allow more opcodes down this path. Eg, we don't handle FP min/max flavors yet. Differential Revision: https://reviews.llvm.org/D60514
  118. [AArch64] Add lowering pattern for llvm.aarch64.neon.vcvtfxs2fp.f16.i64 Summary: Add lowering pattern for llvm.aarch64.neon.vcvtfxs2fp.f16.i64 Reviewers: pbarrio, DavidSpickett, LukeGeeson Reviewed By: LukeGeeson Subscribers: javed.absar, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60259
  119. [X86] SimplifyDemandedVectorElts - add X86ISD::VPERMILPV mask support
  120. [X86][AVX] Add X86ISD::VPERMILPV demandedelts tests
  121. [X86] SimplifyDemandedVectorElts - add X86ISD::VPERMIL2 mask support
  122. [X86][XOP] Add X86ISD::VPERMIL2 demandedelts test
  123. [X86] SimplifyDemandedVectorElts - add VPPERM support We need to add support for all variable shuffle mask ops, but VPPERM is the only one that already has test coverage.
  124. [ValueTracking] Change if-else chain into switch in computeKnownBitsFromAssume This is a follow-up patch to D60504 to further improve performance issues in computeKnownBitsFromAssume. The patch is NFC, but may improve compile-time performance if the compiler isn't clever enough to do the optimization itself.
  125. Test commit access
  126. Use llvm::lower_bound. NFC
  127. [MCA] Remove wrong comments from a test. NFC
  128. [ADT] Fix template parameter names of llvm::{upper|lower}_bound Summary: Rename template parameter for a search value from 'ForwardIt' to 'T'. While here, also use perfect forwarding to pass the value to STL algos. Reviewers: sammccall Reviewed By: sammccall Subscribers: dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60510
  129. try to fix the sphinx build some more
  130. Try to fix the shpinx build
  131. [llvm-exegesis] Fix serialization/deserialization of special NoRegister register (PR41448) Summary: A *lot* of instructions have this special register. It seems this never really worked, but i finally noticed it only because it happened to break for `CMOV16rm` instruction. We serialized that register as "" (empty string), which is naturally 'ignored' during deserialization, so we re-create a `MCInst` with too few operands. And when we then happened to try to resolve variant sched class for this mis-serialized instruction, and the variant predicate tried to read an operand that was out of bounds since we got less operands, we crashed. Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=41448 | PR41448 ]]. Reviewers: craig.topper, courbet Reviewed By: courbet Subscribers: tschuett, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60517
  132. [RISCV] Put data smaller than eight bytes to small data section Because of gp = sdata_start_address + 0x800, gp with signed twelve-bit offset could covert most of the small data section. Linker relaxation could transfer the multiple data accessing instructions to a gp base with signed twelve-bit offset instruction. Differential Revision: https://reviews.llvm.org/D57493
  133. [DWARF] Set discriminator to 0 for DW_LNS_copy Summary: Make DW_LNS_copy set the discriminator register to 0, to conform to DWARF 4 & 5: "Then it sets the discriminator register to 0, and sets the basic_block, prologue_end and epilogue_begin registers to false." Because all of DW_LNE_end_sequence, DN_LNS_copy, and special opcodes reset discriminator to 0, we can move discriminator=0 to appendRowToMatrix. Also, make DW_LNS_copy print before appending the row, as it is similar to a address+=0,line+=0 special opcode, which prints before appending the row. Reviewers: dblaikie, probinson, aprantl Reviewed By: dblaikie Subscribers: danielcdh, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60364
  134. Fix a hang when lowering __builtin_dynamic_object_size If the ObjectSizeOffsetEvaluator fails to fold the object size call, then it may litter some unused instructions in the function. When done repeatably in InstCombine, this results in an infinite loop. Fix this by tracking the set of instructions that were inserted, then removing them on failure. rdar://49172227 Differential revision: https://reviews.llvm.org/D60298
  135. [AArch64][GlobalISel] Make <2 x p0> = G_BUILD_VECTOR legal. The existing isel support already works for p0 once the legalizer accepts it.
  136. [AArch64][GlobalISel] Add legalizer support for <8 x s16> and <16 x s8> G_ADD.
  137. [AArch64][GlobalISel] Scalarize vector SDIV.
  138. [X86] Add SSE1 command line to atomic-fp.ll and atomic-non-integer.ll. NFC
  139. [X86] Autogenerate complete checks. NFC
  140. [X86] Teach foldMaskedShiftToScaledMask to look through an any_extend from i32 to i64 between the and & shl foldMaskedShiftToScaledMask tries to reorder and & shl to enable the shl to fold into an LEA. But if there is an any_extend between them it doesn't work. This patch modifies the code to look through any_extend from i32 to i64 when the and mask only uses bits that weren't from the extended part. This will prevent a regression from D60358 caused by 64-bit SHL being narrowed to 32-bits when their upper bits aren't demanded. Differential Revision: https://reviews.llvm.org/D60532
  141. [X86] Make _Int instructions the preferred instructon for the assembly parser and disassembly parser to remove inconsistencies between VEX and EVEX. Many of our instructions have both a _Int form used by intrinsics and a form used by other IR constructs. In the EVEX space the _Int versions usually cover all the capabilities include broadcasting and rounding. While the other version only covers simple register/register or register/load forms. For this reason in EVEX, the non intrinsic form is usually marked isCodeGenOnly=1. In the VEX encoding space we were less consistent, but usually the _Int version was the isCodeGenOnly version. This commit makes the VEX instructions match the EVEX instructions. This was done by manually studying the AsmMatcher table so its possible I missed some cases, but we should be closer now. I'm thinking about using the isCodeGenOnly bit to simplify the EVEX2VEX tablegen code that disambiguates the _Int and non _Int versions. Currently it checks register class sizes and Record the memory operands come from. I have some other changes I was looking into for D59266 that may break the memory check. I had to make a few scheduler hacks to keep the _Int versions from being treated differently than the non _Int version. Differential Revision: https://reviews.llvm.org/D60441
  142. [ARM] Add an extra test for constant hoist. NFC
  143. [X86] Add test case for LEA formation regression seen with D60358. NFC If we have an (add X, (and (aext (shl Y, C1)), C2)), we can pull the shift through and+aext to fold into an LEA with the. Assuming C1 is small enough and C2 masks off all of the extend bits. This pattern showed up in D60358. And we need to handle it to prevent a regression.
  144. [X86] Replace some if statements in isel address matching that should never be true with asserts. And move them earlier before we looked through operands that don't change size. NFC These ifs were ensuring we don't have to handle types larger than 64 bits probably because we use getZExtValue in several places below them. None of the callers of this code pass types larger than 64-bits so we can just assert instead of branching in release code. I've also moved them earlier since we're just looking through operations that don't effect bit width. This is prep work for some refactoring I plan to do to the (and (shl)) handling code.
  145. [X86AsmPrinter] refactor to limit use of Modifier. NFC Summary: The Modifier memory operands is used in 2 cases of memory references (H & P ExtraCodes). Rather than pass around the likely nullptr Modifier, refactor the handling of the Modifier out from printOperand(). The refactorings in this patch: - Don't forward declare printOperand, move its definition up. - The diff makes it look like there's a change to printPCRelImm (narrator: there's not). - Create printModifiedOperand() - Move logic for Modifier to there from printOperand - Use printModifiedOperand in 3 call sites that actually create Modifiers. - Remove now unused Modifier parameter from printOperand - Remove default parameter from printLeaMemReference as it only has 1 call site that explicitly passes a parameter. - Remove default parameter from printMemReference, make call lone call site explicitly pass nullptr. - Drop Modifier parameter from printIntelMemReference, as Intel style memory references don't support the Modifiers in question. This will allow future changes to printOperand() to make it a pure virtual method on the base AsmPrinter class, allowing for more generic handling of some architecture generic constraints. X86AsmPrinter was the only derived class of AsmPrinter to have additional parameters on its printOperand function. Reviewers: craig.topper, echristo Reviewed By: echristo Subscribers: hiraditya, llvm-commits, srhines Tags: #llvm Differential Revision: https://reviews.llvm.org/D60526
  146. [llvm] Non-functional change: declared a local variable as const.
  147. [PDB Docs] Start documenting CodeView Type Records. This puts the general layout of the document in place and fully describes 1 simple type record. Followups will fill out more pieces.
  148. [X86] X86ScheduleBdVer2: use !listsplat operator to cleanup loadres calculation The problem is that one can't concatenate an empty list (implied all-ones) with non-empty list here. The result will be the non-empty list, and it won't match the length of the ExePorts list. The problems begin when LoadRes != 1 here, which is the case in PdWriteResYMMPair, and more importantly i think it will be the case for PdWriteResExPair.
  149. [TableGen] Introduce !listsplat 'binary' operator Summary: ``` ``!listsplat(a, size)`` A list value that contains the value ``a`` ``size`` times. Example: ``!listsplat(0, 2)`` results in ``[0, 0]``. ``` I plan to use this in X86ScheduleBdVer2.td for LoadRes handling. This is a little bit controversial because unlike every other binary operator the types aren't identical. Reviewers: stoklund, javed.absar, nhaehnle, craig.topper Reviewed By: javed.absar Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60367
  150. [kate] Add '!mul' operator that was introduced in D58775
  151. [ARM] Add an extra constant hoisting test. NFC This adds a simple extra test for constant hoisting to show it's usefulness with constant addresses like those seen in memory mapped registers in embedded systems.
  152. Revert rL357745: [SelectionDAG] Compute known bits of CopyFromReg Certain optimisations from ConstantHoisting and CGP rely on Selection DAG not seeing through to the constant in other blocks. Revert this patch while we come up with a better way to handle that. I will try to follow this up with some better tests.
  153. llvm-undname: Fix another crash-on-invalid This fixes a regression from https://reviews.llvm.org/D60354. We used to SymbolNode *Symbol = demangleEncodedSymbol(MangledName, QN); if (Symbol) { Symbol->Name = QN; } but changed that to SymbolNode *Symbol = demangleEncodedSymbol(MangledName, QN); if (Error) return nullptr; Symbol->Name = QN; and one branch somewhere returned a nullptr without setting Error. Looking at the code changed in r340083 and r340710 that branch looks like a remnant from an earlier attempt to demangle RTTI descriptors that has since been rewritten -- so just remove this branch. It shouldn't change behavior for correctly mangled symbols.
  154. GlobalISel: Move computeValueLLTs Call lowering should use this directly instead of going through the EVT version, but more work is needed to deal with this (mostly the passing of the IR type pointer instead of the relevant properties in ArgInfo).
  155. GlobalISel: Fix invoke lowering creating invalid type registers Unlike the call handling, this wasn't checking for void results and creating a register with the invalid LLT
  156. GlobalISel: Support legalizing G_CONSTANT with irregular breakdown
  157. [AArch64] Teach getTestBitOperand to look through ANY_EXTENDS This patch teach getTestBitOperand to look through ANY_EXTENDs when the extended bits aren't used. The test case changed here is based what D60358 did to test16 in tbz-tbnz.ll. So this patch will avoid that regression. Differential Revision: https://reviews.llvm.org/D60482
  158. GlobalISel: Handle odd breakdowns for bit ops
  159. add FIXME: as per echristo
  160. [AsmPrinter] refactor to remove remove AsmVariant. NFC Summary: The InlineAsm::AsmDialect is only required for X86; no architecture makes use of it and as such it gets passed around between arch-specific and general code while being unused for all architectures but X86. Since the AsmDialect is queried from a MachineInstr, which we also pass around, remove the additional AsmDialect parameter and query for it deep in the X86AsmPrinter only when needed/as late as possible. This refactor should help later planned refactors to AsmPrinter, as this difference in the X86AsmPrinter makes it harder to make AsmPrinter more generic. Reviewers: craig.topper Subscribers: jholewinski, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, sbc100, jgravelle-google, eraman, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, llvm-commits, peter.smith, srhines Tags: #llvm Differential Revision: https://reviews.llvm.org/D60488
  161. [InstCombine] Handle ssubo always overflow Following D60483 and D60497, this adds support for AlwaysOverflows handling for ssubo. This is the last case we can handle right now. Differential Revision: https://reviews.llvm.org/D60518
  162. [InstCombine] ssubo X, C -> saddo X, -C ssubo X, C is equivalent to saddo X, -C. Make the transformation in InstCombine and allow the logic implemented for saddo to fold prior usages of add nsw or sub nsw with constants. Patch by Dan Robertson. Differential Revision: https://reviews.llvm.org/D60061
  163. Improve compile-time performance in computeKnownBitsFromAssume. This patch changes the order of pattern matching by first testing a compare instruction's predicate, before doing the pattern match for the whole expression tree. Patch by Paul Walker. Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D60504
  164. [X86][AVX] getTargetConstantBitsFromNode - extract bits from X86ISD::SUBV_BROADCAST
  165. [InstCombine] Handle saddo always overflow Followup to D60483: Handle AlwaysOverflow conditions for saddo as well. Differential Revision: https://reviews.llvm.org/D60497
  166. Fix a typo
  167. [MachineOutliner] Replace ostringstream based string concatenation with Twine This makes my libLLVMCodeGen.so.9svn 4936 bytes smaller. While here, delete unused #include <map>
  168. [LLVM-C] Correct The Current Debug Location Accessors (Again) Summary: Resubmitting D60484 with the conflicting Go bindings renamed to avoid collisions. Reviewers: whitequark, deadalnix Subscribers: hiraditya, llvm-commits, sammccall Tags: #llvm Differential Revision: https://reviews.llvm.org/D60511
  169. [AArch64] Add lowering pattern for scalar fp16 facge and facgt Summary: The fp16 scalar version of facge and facgt requires a custom patter matching, as the result type is not the same width of the operands. Reviewers: olista01, javed.absar, pbarrio Reviewed By: javed.absar Subscribers: kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60212
  170. Revert "[LLVM-C] Correct The Current Debug Location Accessors" This reverts commit r358039, which added symbols that conflict with the Go bindings.
  171. [ARM] [FIX] Add missing f16 vector operations lowering Summary: Add missing <8xhalf> shufflevectors pattern, when using concat_vector dag node. As well, allows <8xhalf> and <4xhalf> vldup1 operations. These instructions are required for v8.2a fp16 lowering of vmul_n_f16, vmulq_n_f16 and vmulq_lane_f16 intrinsics. Reviewers: olista01, pbarrio, LukeGeeson, efriedma Reviewed By: efriedma Subscribers: efriedma, javed.absar, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60319
  172. [NFC] Fix unused variable warning.
  173. [llvm-exegesis] Pacify bots - don't std::move() - prevents copy elision
  174. [llvm-readobj] Should declare `ListScope` for `verneed` entries. Summary: YAML mappings require keys to be unique. See: https://yaml.org/spec/1.2/spec.html#id2764652 Reviewers: jhenderson, grimar, rupprecht, espindola, ruiu Reviewed By: ruiu Subscribers: ruiu, emaste, arichardson, MaskRay, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60438
  175. [llvm-exegesis] YamlContext: fix some missing spaces/quotes/newlines in error strings
  176. [llvm-exegesis] Fix error propagation from yaml writing (from serialization) Investigating https://bugs.llvm.org/show_bug.cgi?id=41448
  177. [DebugInfo] Track multiple registers in DbgEntityHistoryCalculator Summary: When calculating the debug value history, DbgEntityHistoryCalculator would only keep track of register clobbering for the latest debug value per inlined entity. This meant that preceding register-described debug value fragments would live on until the next overlapping debug value, ignoring any potential clobbering. This patch amends DbgEntityHistoryCalculator so that it keeps track of all registers that a inlined entity's currently live debug values are described by. The DebugInfo/COFF/pieces.ll test case has had to be changed since previously a register-described fragment would incorrectly outlive its basic block. The parent patch D59941 is expected to increase the coverage slightly, as it makes sure that location list entries are inserted after clobbered fragments, and this patch is expected to decrease it, as it stops preceding register-described from living longer than they should. All in all, this patch and the preceding patch has a negligible effect on the output from `llvm-dwarfdump -statistics' for a clang-3.4 binary built using the RelWithDebInfo build profile. "Scope bytes covered" increases by 0.5%, and "variables with location" increases from 2212083 to 2212088, but it should improve the accuracy quite a bit. This fixes PR40283. Reviewers: aprantl, probinson, dblaikie, rnk, bjope Reviewed By: aprantl Subscribers: llvm-commits Tags: #debug-info, #llvm Differential Revision: https://reviews.llvm.org/D59942
  178. [DebugInfo] Improve handling of clobbered fragments Summary: Currently the DbgValueHistorymap only keeps track of clobbered registers for the last debug value that it has encountered. This could lead to preceding register-described debug values living on longer in the location lists than they should. See PR40283 for an example. This patch does not introduce tracking of multiple registers, but changes the DbgValueHistoryMap structure to allow for that in a follow-up patch. This patch is not NFC, as it at least fixes two bugs in DwarfDebug (both are covered in the new clobbered-fragments.mir test): * If a debug value was clobbered (its End pointer set), the value would still be added to OpenRanges, meaning that the succeeding location list entries could potentially contain stale values. * If a debug value was clobbered, and there were non-overlapping fragments that were still live after the clobbering, DwarfDebug would not create a location list entry starting directly after the clobbering instruction. This meant that the location list could have a gap until the next debug value for the variable was encountered. Before this patch, the history map was represented by <Begin, End> pairs, where a new pair was created for each new debug value. When dealing with partially overlapping register-described debug values, such as in the following example: DBG_VALUE $reg2, $noreg, !1, !DIExpression(DW_OP_LLVM_fragment, 32, 32) [...] DBG_VALUE $reg3, $noreg, !1, !DIExpression(DW_OP_LLVM_fragment, 64, 32) [...] $reg2 = insn1 [...] $reg3 = insn2 the history map would then contain the entries `[<DV1, insn1>, [<DV2, insn2>]`. This would leave it up to the users of the map to be aware of the relative order of the instructions, which e.g. could make DwarfDebug::buildLocationList() needlessly complex. Instead, this patch makes the history map structure monotonically increasing by dropping the End pointer, and replacing that with explicit clobbering entries in the vector. Each debug value has an "end index", which if set, points to the entry in the vector that ends the debug value. The ending entry can either be an overlapping debug value, or an instruction which clobbers the register that the debug value is described by. The ending entry's instruction can thus either be excluded or included in the debug value's range. If the end index is not set, the debug value that the entry introduces is valid until the end of the function. Changes to test cases: * DebugInfo/X86/pieces-3.ll: The range of the first DBG_VALUE, which describes that the fragment (0, 64) is located in RDI, was incorrectly ended by the clobbering of RAX, which the second (non-overlapping) DBG_VALUE was described by. With this patch we get a second entry that only describes RDI after that clobbering. * DebugInfo/ARM/partial-subreg.ll: This test seems to indiciate a bug in LiveDebugValues that is caused by it not being aware of fragments. I have added some comments in the test case about that. Also, before this patch DwarfDebug would incorrectly include a register-described debug value from a preceding block in a location list entry. Reviewers: aprantl, probinson, dblaikie, rnk, bjope Reviewed By: aprantl Subscribers: javed.absar, kristof.beyls, jdoerfert, llvm-commits Tags: #debug-info, #llvm Differential Revision: https://reviews.llvm.org/D59941
  179. [TargetLowering] Move shouldFoldShiftPairToMask next to preferShiftsToClearExtremeBits. NFCI. As discussed on PR41359, we're probably going to keep both of these but we need to make it more explicit how they complement each other.
  180. [AsmPrinter] Delete unused RangeSpanList::addRange
  181. MCSymbolicELF: simplify. (Flags & (x << s)) >> s is equivalent to Flags >> s & x
  182. MCDwarf: use write_zeroes for MCDwarfLineAddr::FixedEncode This is more efficient than allocating a std::vector<uint8_t>.
  183. Fixup r358063 Fix warning/error about mixed signedness.
  184. [ARM GlobalISel] Add some asserts. NFC. Make sure some arm opcodes don't unintentionally sneak into thumb mode.
  185. [ARM GlobalISel] Select G_FCONSTANT for VFP3 Make it possible to TableGen code for FCONSTS and FCONSTD. We need to make two changes to the TableGen descriptions of vfp_f32imm and vfp_f64imm respectively: * add GISelPredicateCode to check that the immediate fits in 8 bits; * extract the SDNodeXForms into separate definitions and create a GISDNodeXFormEquiv and a custom renderer function for each of them. There's a lot of boilerplate to get the actual value of the immediate, but it basically just boils down to calling ARM_AM::getFP32Imm or ARM_AM::getFP64Imm.
  186. [ARM GlobalISel] Select G_FCONSTANT into pools Put all floating point constants into constant pools and load their values from there.
  187. [ARM GlobalISel] Map G_FCONSTANT
  188. [DebugInfo] Rename DbgValueHistoryMap::{InstrRange -> Entry}, NFC Summary: In an upcoming commit the history map will be changed so that it contains explicit entries for instructions that clobber preceding debug values, rather than Begin- End range pairs, so generalize the name to "Entry". Also, prefix the iterator variable names in buildLocationList() with "E". In an upcoming commit the entry will have query functions such as "isD(e)b(u)gValue", which could at a glance make one confuse it for iterations over MachineInstrs, so make the iterator names a bit more distinct to avoid that. Reviewers: aprantl Reviewed By: aprantl Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59939
  189. [DebugInfo] Make InstrRange into a class, NFC Summary: Replace use of std::pair by creating a class for the debug value instruction ranges instead. This is a preparatory refactoring for improving handling of clobbered fragments. In an upcoming commit the Begin pointer will become a PointerIntPair, so it will be cleaner to have a getter for that. Reviewers: aprantl Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59938
  190. [ScheduleDAG] Add statistics for maintaining the topological order. This is helpful to measure the impact of D60125 on maintaining topological orders. Reviewers: MatzeB, atrick, efriedma, niravd Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D60187
  191. Add REQUIRES: asserts to test using -debug-only
  192. [VPLAN] Minor improvement to testing and debug messages. 1. Use computed VF for stress testing. 2. If the computed VF does not produce vector code (VF smaller than 2), force VF to be 4. 3. Test vectorization of i64 data on AArch64 to make sure we generate VF != 4 (on X86 that was already tested on AVX). Patch by Francesco Petrogalli <francesco.petrogalli@arm.com> Differential Revision: https://reviews.llvm.org/D59952
  193. [DWARF] Simplify LineTable::findRowInSeq We want the last row whose address is less than or equal to Address. This can be computed as upper_bound - 1, which is simpler than lower_bound followed by skipping equal rows in a loop. Since FirstRow (LowPC) does not satisfy the predicate (OrderByAddress) while LastRow-1 (HighPC) satisfies the predicate. We can decrease the search range by two, i.e. upper_bound [FirstRow,LastRow) = upper_bound [FirstRow+1,LastRow-1)
  194. [InstCombine] Handle usubo always overflow Check AlwaysOverflow condition for usubo. The implementation is the same as the existing handling for uaddo and umulo. Handling for saddo and ssubo will follow (smulo doesn't have the necessary ValueTracking support). Differential Revision: https://reviews.llvm.org/D60483
  195. [InstCombine] Directly call computeOverflow methods in OptimizeOverflowCheck; NFC Instead of using the willOverflow helpers. This makes it easier to extend handling of AlwaysOverflows.
  196. [InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y). Differential Revision: https://reviews.llvm.org/D60395
  197. [ObjC][ARC] Convert the retainRV marker that is passed as a named metadata into a module flag in the auto-upgrader and make the ARC contract pass read the marker as a module flag. This is needed to fix a bug where ARC contract wasn't inserting the retainRV marker when LTO was enabled, which caused objects returned from a function to be auto-released. rdar://problem/49464214 Differential Revision: https://reviews.llvm.org/D60303
  198. [X86] Move the 2 byte VEX optimization for MOV instructions back to the X86AsmParser::processInstruction where it used to be. Block when {vex3} prefix is present. Years ago I moved this to an InstAlias using VR128H/VR128L. But now that we support {vex3} pseudo prefix, we need to block the optimization when it is set to match gas behavior.
  199. [llvm-objdump] Don't print trailing space in dumpBytes In disassembly output, dumpBytes prints a space, followed by a tab printed by printInstr. Remove the extra space.
  200. [llvm-objdump] Accept and ignore --wide/-w This is similar to what we do for llvm-readobj (--wide/-W is for GNU readelf compatibility). The test will be added in D60376.
  201. [Sparc] Fix incorrect MI insertion position for spilling f128. Summary: Obviously, new built MI (sethi+add or sethi+xor+add) for constructing large offset should be inserted before new created MI for storing even register into memory. So the insertion position should be *StMI instead of II. before fixed: std %f0, [%g1+80] sethi 4, %g1 <<< add %g1, %sp, %g1 <<< this two instructions should be put before "std %f0, [%g1+80]". sethi 4, %g1 add %g1, %sp, %g1 std %f2, [%g1+88] after fixed: sethi 4, %g1 add %g1, %sp, %g1 std %f0, [%g1+80] sethi 4, %g1 add %g1, %sp, %g1 std %f2, [%g1+88] Reviewers: venkatra, jyknight Reviewed By: jyknight Subscribers: jyknight, fedor.sergeev, jrtc27, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60397
  202. [X86] Support the EVEX versions vcvt(t)ss2si and vcvt(t)sd2si with the {evex} pseudo prefix in the assembler. The EVEX versions are ambiguous with the VEX versions based on operands alone so we had explicitly dropped them from the AsmMatcher table. Unfortunately, when we add them they incorrectly show in the table before their VEX counterparts. This is different how the prioritization normally works. To fix this we have to explicitly reject the instructions unless the {evex} prefix has been seen.
  203. [X86] Add VEX_LIG to scalar VEX/EVEX instructions that were missing it. Scalar VEX/EVEX instructions don't use the L bit and don't look at it for decoding either. So we should ignore it in our disassembler. The missing instructions here were found by grepping the raw tablegen class definitions in the tablegen debug output.
  204. [LLVM-C] Correct The Current Debug Location Accessors Summary: Deprecate the existing accessors for the "current debug location" of an IRBuilder. The setter could not handle being reset to NULL, and the getter would create bogus metadata if the NULL location was returned. Provide direct metadata-based accessors instead. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60484
  205. [LLVM-C] Add Bindings to Access an Instruction's DebugLoc Summary: Provide direct accessors to supplement LLVMSetInstDebugLocation. In addition, properly accept and return the NULL location. The old accessors provided no way to do this, so the current debug location cannot currently be cleared. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60481
  206. [LLVM-C] Add Section and Symbol Iterator Accessors for Object File Binaries Summary: This brings us to full feature parity with the old API, so I've deprecated it and updated the tests. I'll do a follow-up patch to do some more cleanup and documentation work in this header. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60407
  207. [X86] Fix a dangling StringRef issue introduced in r358029. I was attempting to convert mnemonics to lower case after processing a pseudo prefix. But the ParseOperands just hold a StringRef for tokens so there is no where to allocate the memory. Add FIXMEs for the lower case issue which also exists in the prefix parsing code.
  208. [AArch64][GlobalISel] Add isel support for vector G_ICMP and G_ASHR & G_SHL The selection for G_ICMP is unfortunately not currently importable from SDAG due to the use of custom SDNodes. To support this, this selection method has an opcode table which has been generated by a script, indexed by various instruction properties. Ideally in future we will have a GISel native selection patterns that we can write in tablegen to improve on this. For selection of some types we also need support for G_ASHR and G_SHL which are generated as a result of legalization. This patch also adds support for them, generating the same code as SelectionDAG currently does. Differential Revision: https://reviews.llvm.org/D60436
  209. [AArch64][GlobalISel] Legalize vector G_ICMP. Selection support will be coming in a later patch. Differential Revision: https://reviews.llvm.org/D60435
  210. [AArch64][GlobalISel] Add legalization for some vector G_SHL and G_ASHR. This is needed for some future support for vector ICMP. Differential Revision: https://reviews.llvm.org/D60433
  211. [GlobalISel][AArch64] Allow CallLowering to handle types which are normally required to be passed as different register types. E.g. <2 x i16> may need to be passed as a larger <2 x i32> type, so formal arg lowering needs to be able truncate it back. Likewise, when dealing with returns of these types, they need to be widened in the appropriate way back. Differential Revision: https://reviews.llvm.org/D60425
  212. [InstCombine] Add with.overflow always overflow tests; NFC The uadd and umul cases are currently handled, the usub, sadd, ssub and smul cases are not. usub, sadd and ssub already have the necessary ValueTracking support, smul doesn't.
  213. [AArch64] Add test case to show missed opportunity to remove a shift before tbnz when the shift has been zero extended from i32 to i64. NFC This pattern showed up in D60358 and it was suggested I had a test and fix that separately.
  214. [X86] Add support for {vex2}, {vex3}, and {evex} to the assembler to match gas. Use {evex} to improve the one our 32-bit AVX512 tests. These can be used to force the encoding used for instructions. {vex2} will fail if the instruction is not VEX encoded, but otherwise won't do anything since we prefer vex2 when possible. Might need to skip use of the _REV MOV instructions for this too, but I haven't done that yet. {vex3} will force the instruction to use the 3 byte VEX encoding or fail if there is no VEX form. {evex} will force the instruction to use the EVEX version or fail if there is no EVEX version. Differential Revision: https://reviews.llvm.org/D59266
  215. [DAGCombiner][X86][SystemZ] Canonicalize SSUBO with immediate RHS to SADDO by negating the immediate. This lines up with what we do for regular subtract and it matches up better with X86 assumptions in isel patterns that add with immediate is more canonical than sub with immediate. Differential Revision: https://reviews.llvm.org/D60020
  216. Revert "[InstCombine] [InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y)." This reverts commit 1383a9168948aabfd827220c9445ce0ce5765800. sdiv-canonicalize.ll fails after this revision. The fold needs to be moved outside the branch handling constant operands. However when this is done there are further test changes, so I'm reverting this in the meantime.
  217. [InstCombine] Restructure OptimizeOverflowCheck; NFC Change the code to always handle the unsigned+signed cases together with the same basic structure for add/sub/mul. The simple folds are always handled first and then the ValueTracking overflow checks are used.
  218. Remove the unit at a time option Removes the code from opt and the pass manager builder. The code was unused - even by the C library code that was supposed to set it and had been removed previously.
  219. [PDB Docs] Clarifications and fixes for DBI Stream.
  220. Update modulemaps for Analysis/VecFuncs.def. Avoid a warning while building modular LLVM due to a new textual header missing in the modulemap: TargetLibraryInfo.cpp:1485:6: warning: missing submodule 'LLVM_Analysis.VecFuncs' [-Wincomplete-umbrella] Added VecFuncs.def as a textual header in LLVM_Analysis.
  221. [ValueTracking] Use computeConstantRange() for signed sub overflow determination This is the same change as D60420 but for signed sub rather than signed add: Range information is intersected into the known bits result, allows to detect more no/always overflow conditions. Differential Revision: https://reviews.llvm.org/D60469
  222. [TargetLowering] SimplifyDemandedBits - add ISD::INSERT_SUBVECTOR support
  223. [InstCombine] [InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y). Differential Revision: https://reviews.llvm.org/D60395
  224. Revert LIS handling in MachineDCE One of out of tree targets has regressed with this patch. Reverting it for now and let liveness to be fully reconstructed in case pass was used after the LIS is created to resolve the regression. Differential Revision: https://reviews.llvm.org/D60466
  225. [ValueTracking] Use computeConstantRange() in signed add overflow determination This is D59386 for the signed add case. The computeConstantRange() result is now intersected into the existing known bits information, allowing to detect additional no-overflow/always-overflow conditions (though the latter isn't used yet). This (finally...) covers the motivating case from D59071. Differential Revision: https://reviews.llvm.org/D60420
  226. [InstCombine] prevent possible miscompile with sdiv+negate of vector op Similar to: rL358005 Forego folding arbitrary vector constants to fix a possible miscompile bug. We can enhance the transform if we do want to handle the more complicated vector case.
  227. [DWARF] DWARFDebugLine: replace Sequence::orderByLowPC with orderByHighPC In a sorted list of non-overlapping [LowPC,HighPC) ranges, locating an address with upper_bound on HighPC is simpler than lower_bound on LowPC.
  228. [InstCombine] add tests for sdiv with negated dividend and constant divisor; NFC
  229. [InstCombine] add tests for sdiv-by-int-min; NFC
  230. [InstCombine] auto-generate complete test checks; NFC
  231. [InstCombine] prevent possible miscompile with negate+sdiv of vector op // 0 - (X sdiv C) -> (X sdiv -C) provided the negation doesn't overflow. This fold has been around for many years and nobody noticed the potential vector miscompile from overflow until recently... So it seems unlikely that there's much demand for a vector sdiv optimization on arbitrary vector constants, so just limit the matching to splat constants to avoid the possible bug. Differential Revision: https://reviews.llvm.org/D60426
  232. gn build: Fix Windows builds after r357797
  233. [InstCombine] add tests/comments for negate+sdiv; NFC
  234. NFC: Refactor library-specific mappings of scalar maths functions to their vector counterparts This patch factors out mappings of scalar maths functions to their vector counterparts from TargetLibraryInfo.cpp to a separate VecFuncs.def file. Such mappings are currently available for Accelerate framework, and SVML library. This is in support of the follow-up: https://reviews.llvm.org/D59881 Patch by pjeeva01 Differential revision: https://reviews.llvm.org/D60211
  235. [InstCombine] add more testcases for canonicalize (-X s/ Y) to -(X s/ Y).
  236. [TargetLowering] SimplifyDemandedBits - Remove GetDemandedSrcMask lambda. NFCI. An older version of this could return false but now that this always succeeds we can just inline and simplify it.
  237. Improve hashing for time profiler Summary: Use optimized hashing while writing time trace by join two hashes to one. Used for -ftime-trace option. Reviewers: rnk, takuto.ikuta Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60404
  238. [TargetLowering] SimplifyDemandedBits - call SimplifyDemandedBits in bitcast handling When bitcasting from a source op to a larger bitwidth op, split the demanded bits and OR them on top of one another and demand those merged bits in the SimplifyDemandedBits call on the source op.
  239. [llvm-rtdyld] Fix missing include on MSVC builds.
  240. [DebugInfo] Pass all values in DebugLocEntry's constructor, NFC Summary: With MergeValues() removed, amend DebugLocEntry's constructor so that it takes multiple values rather than a single, and keep non-fragment values in OpenRanges, as this allows some cleanup of the code in buildLocationList(). Reviewers: aprantl, dblaikie, loladiro Reviewed By: aprantl Subscribers: hiraditya, llvm-commits Tags: #debug-info, #llvm Differential Revision: https://reviews.llvm.org/D59303
  241. Fix Wdocumentation warning. NFCI.
  242. [PowerPC] fix trivial typos in comment, NFC
  243. [CMake] Fix accidentally swapped input/output parameters of string(REPLACE) for mingw
  244. [CMake] Move configuration of LLVM_CXX_STD to HandleLLVMOptions.cmake Standalone builds of projects other than llvm itself (lldb, libcxx, etc) include HandleLLVMOptions but not the top level llvm CMakeLists, so we need to set this variable here to ensure that it always has a value. This should fix the build issues some folks have been seeing.
  245. [DebugInfo] Remove redundant DebugLocEntry::MergeValues() function, NFC Summary: The MergeValues() function would try to merge two entries if they shared the same beginning label. Having the same beginning label means that the former entry's range would be empty; however, after D55919 we no longer create entries for empty ranges, so we can no longer land in a situation where that check in MergeValues would succeed. Instead, the "merging" is done by keeping the live values from the preceding empty ranges in OpenRanges, and adding them to the first non-empty range. Reviewers: aprantl, dblaikie, loladiro Reviewed By: aprantl Subscribers: llvm-commits Tags: #debug-info, #llvm Differential Revision: https://reviews.llvm.org/D59301
  246. [X86] Remove check on isAsmParserOnly from EVEX2VEX tablegenerator. NFCI There are no instructions VEX or EVEX instructions that set this field.
  247. [X86] Have EVEX2VEX tablegenerator use HasVEX_L and HasEVEX_L2 fields instead of the composite EVEX_LL field. Remove the EVEX_LL field. NFCI The composite existed to simplify some other tablegen code and not really in an important way. Remove the combined field and just calculate the vector size using two ifs.
  248. [X86] Use VEX_WIG for VPINSRB/W and VPEXTRB/W to match what is done for EVEX. The instruction's document this as W0 for the VEX encoding. But there's a footnote mentioning that VEX.W is ignored in 64-bit mode. And the main VEX encoding description says the VEX.W bit is ignored for instructions that are equivalent to a legacy SSE instruction that uses REX.W to select a GPR which would apply here. By making this match EVEX we can remove a special case of allowing EVEX2VEX to turn an EVEX.WIG instruction into VEX.W0.
  249. [X86] Split the VEX_WPrefix in X86Inst tablegen class into 3 separate fields with clear meanings.
  250. [ValueTracking] Use ConstantRange methods; NFC Switch part of the computeOverflowForSignedAdd() implementation to use Range.isAllNegative() rather than KnownBits.isNegative() and similar. They do the same thing, but using the ConstantRange methods allows dropping the KnownBits variables more easily in D60420.
  251. [ValueTracking] Explicitly specify intersection type; NFC Preparation for D60420.
  252. Include omitted word in comment.
  253. [llvm-objdump] Migrate some functions from std::error_code to Error
  254. AMDGPU/GlobalISel: Implement call lowering for shaders returning values Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, jvesely, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, volkan, llvm-commits Differential Revision: https://reviews.llvm.org/D57166
  255. [PowerPC] initialize SchedModel according to platform. Differential Revision: https://reviews.llvm.org/D60177
  256. hwasan: Enable -hwasan-allow-ifunc by default. It's been on in Android for a while without causing problems, so it's time to make it the default and remove the flag. Differential Revision: https://reviews.llvm.org/D60355
  257. [X86] Derive ssmem and sdmem from X86MemOperand. NFCI This changes the operand type from v4f32/v2f64 to iPTR which seems more correct. But that doesn't seem to do anything other than change the comments in X86GenDAGISel.inc. Probably because we use a ComplexPattern to do the matching so there's no autogenerated code to change.
  258. [InstCombine] add tests for negate+sdiv; NFC PR41425: https://bugs.llvm.org/show_bug.cgi?id=41425
  259. [RuntimeDyld] Fix an ambiguous make_unique call.
  260. [RuntimeDyld] Decouple RuntimeDyldChecker from RuntimeDyld. This will allow RuntimeDyldChecker (and rtdyld-check tests) to test a new JIT linker: JITLink (https://reviews.llvm.org/D58704).
  261. [BinaryFormat] Update Mach-O ARM64E CPU subtype and dumping The new value is taken from <mach/machine.h> in the MacOSX10.14 SDK from Xcode 10.1. Update llvm-objdump and llvm-readobj accordingly. Differential Revision: https://reviews.llvm.org/D58636
  262. [InstCombine] peek through fdiv to find a squared sqrt A more general canonicalization between fdiv and fmul would not handle this case because that would have to be limited by uses to prevent 2 values from becoming 3 values: (x/y) * (x/y) --> (x*x) / (y*y) (But we probably should still have that limited -- but more general -- canonicalization independently of this change.)
  263. [TargetLowering] SimplifyDemandedBits - use DemandedElts in bitcast handling Be more selective in the SimplifyDemandedBits -> SimplifyDemandedVectorElts bitcast call based on the demanded elts.
  264. [InstCombine] add extra-use tests for fmul+sqrt; NFC
  265. [InstCombine] Add more tests for signed saturing math overflow; NFC Overflow conditions for sadd.sat and ssub.sat which can be determined based on constant ranges, but not necessarily known bits.
  266. llvm-undname: Fix more crashes and asserts on invalid inputs For functions whose callers don't check that enough input is present, add checks at the start of the function that enough input is there and set Error otherwise. For functions that return AST objects, return nullptr instead of incomplete AST objects with nullptr fields if an error occurred during the function. Introduce a new function demangleDeclarator() for the sequence demangleFullyQualifiedSymbolName(); demangleEncodedSymbol() and use it in the two places that had this sequence. Let this new function check that ConversionOperatorIdentifiers have a valid TargetType. Some of the bad inputs found by oss-fuzz, others by inspection. Differential Revision: https://reviews.llvm.org/D60354
  267. [X86] Fix a couple lowering functions that called ReplaceAllUsesOfValueWith for the newly created code and then return SDValue(). Use MERGE_VALUES instead. Returning SDValue() makes the caller think custom lowering was unsuccessful and then it will fall back to trying to expand the original node. This expanded code will end up with no users and end up being pruned later. But it was useless unnecessary work to create it. Instead return a MERGE_VALUES with all the results so the caller knows something changed. The caller can handle the replacements. For one of the cases I had to use UNDEF has a dummy value for a result we know is unused. This should get pruned later.
  268. Add LLVM IR debug info support for Fortran COMMON blocks COMMON blocks are a feature of Fortran that has no direct analog in C languages, but they are similar to data sections in assembly language programming. A COMMON block is a named area of memory that holds a collection of variables. Fortran subprograms may map the COMMON block memory area to their own, possibly distinct, non-empty list of variables. A Fortran COMMON block might look like the following example. COMMON /ALPHA/ I, J For this construct, the compiler generates a new scope-like DI construct (!DICommonBlock) into which variables (see I, J above) can be placed. As the common block implies a range of storage with global lifetime, the !DICommonBlock refers to a !DIGlobalVariable. The Fortran variable that comprise the COMMON block are also linked via metadata to offsets within the global variable that stands for the entire common block. @alpha_ = common global %alphabytes_ zeroinitializer, align 64, !dbg !27, !dbg !30, !dbg !33 !14 = distinct !DISubprogram(…) !20 = distinct !DICommonBlock(scope: !14, declaration: !25, name: "alpha") !25 = distinct !DIGlobalVariable(scope: !20, name: "common alpha", type: !24) !27 = !DIGlobalVariableExpression(var: !25, expr: !DIExpression()) !29 = distinct !DIGlobalVariable(scope: !20, name: "i", file: !3, type: !28) !30 = !DIGlobalVariableExpression(var: !29, expr: !DIExpression()) !31 = distinct !DIGlobalVariable(scope: !20, name: "j", file: !3, type: !28) !32 = !DIExpression(DW_OP_plus_uconst, 4) !33 = !DIGlobalVariableExpression(var: !31, expr: !32) The DWARF generated for this is as follows. DW_TAG_common_block: DW_AT_name: alpha DW_AT_location: @alpha_+0 DW_TAG_variable: DW_AT_name: common alpha DW_AT_type: array of 8 bytes DW_AT_location: @alpha_+0 DW_TAG_variable: DW_AT_name: i DW_AT_type: integer*4 DW_AT_location: @Alpha+0 DW_TAG_variable: DW_AT_name: j DW_AT_type: integer*4 DW_AT_location: @Alpha+4 Patch by Eric Schweitz! Differential Revision: https://reviews.llvm.org/D54327
  269. Revert [ThinLTO] Fix ThinLTOCodegenerator to export llvm.used symbols This reverts r357931 (git commit 8b70a5c11e08116955a875b9085433f14737bcaf)
  270. [ThinLTO] Fix ThinLTOCodegenerator to export llvm.used symbols Summary: ThinLTOCodeGenerator currently does not preserve llvm.used symbols and it can internalize them. In order to pass the necessary information to the legacy ThinLTOCodeGenerator, the input to the code generator is rewritten to be based on lto::InputFile. This fixes: PR41236 rdar://problem/49293439 Reviewers: tejohnson, pcc, dexonsmith Reviewed By: tejohnson Subscribers: mehdi_amini, inglorion, eraman, hiraditya, jkorous, dang, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60226
  271. [JumpThreading] Fix incorrect fold conditional after indirectbr/callbr Fixes bug 40992: https://bugs.llvm.org/show_bug.cgi?id=40992 There is potential for miscompiled code emitted from JumpThreading when analyzing a block with one or more indirectbr or callbr predecessors. The ProcessThreadableEdges() function incorrectly folds conditional branches into an unconditional branch. This patch prevents incorrect branch folding without fully pessimizing other potential threading opportunities through the same basic block. This IR shape was manually fed in via opt and is unclear if clang and the full pass pipeline will ever emit similar code shapes. Thanks to Matthias Liedtke for the bug report and simplified IR example. Differential Revision: https://reviews.llvm.org/D60284
  272. [llvm-objdump] Migrate relocation handling functions from error_code to Error
  273. [llvm-mca][scheduler-stats] Print issued micro opcodes per cycle. NFCI It makes more sense to print out the number of micro opcodes that are issued every cycle rather than the number of instructions issued per cycle. This behavior is also consistent with the dispatch-stats: numbers from the two views can now be easily compared.
  274. [X86][AVX] Add PR34380 shuffle test cases
  275. [x86] make 8-bit shl undesirable I was looking at a potential DAGCombiner fix for 1 of the regressions in D60278, and it caused severe regression test pain because x86 TLI lies about the desirability of 8-bit shift ops. We've hinted at making all 8-bit ops undesirable for the reason in the code comment: // TODO: Almost no 8-bit ops are desirable because they have no actual // size/speed advantages vs. 32-bit ops, but they do have a major // potential disadvantage by causing partial register stalls. ...but that leads to massive diffs and exposes all kinds of optimization holes itself. Differential Revision: https://reviews.llvm.org/D60286
  276. Use llvm::crc32 instead of crc32. NFC
  277. [InstCombine] remove overzealous assert for shuffles (PR41419) As the TODO indicates, instsimplify could be improved. Should fix: https://bugs.llvm.org/show_bug.cgi?id=41419
  278. [InstCombine][X86] Expand MOVMSK to generic IR (PR39927) First step towards removing the MOVMSK intrinsics completely - this patch expands MOVMSK to the pattern: e.g. PMOVMSKB(v16i8 x): %cmp = icmp slt <16 x i8> %x, zeroinitializer %int = bitcast <16 x i8> %cmp to i16 %res = zext i16 %int to i32 Which is correctly handled by ISel and FastIsel (give or take an annoying movzx move....): https://godbolt.org/z/rkrSFW Differential Revision: https://reviews.llvm.org/D60256
  279. gn build: Merge r357905
  280. gn-build: Re-run `git ls-files '*.gn' '*.gni' | xargs llvm/utils/gn/gn.py format`
  281. Attempt to recommit r357901
  282. [InstCombine] sdiv exact flag fixup. Differential Revision: https://reviews.llvm.org/D60396
  283. [llvm-readobj] Use `reinterpret_cast` instead of C-style casting. NFC.
  284. Reverting r357901 as fails to build on some of the buildbots
  285. [Support] Add zlib independent CRC32 Differential revision: https://reviews.llvm.org/D59816
  286. [llvm-exegesis] benchmarkMain(): less cryptic error if built w/o libpfm Wanted to check if inablility to measure latency of CMOV32rm is a regression from D60041 / D60138, but unable to do that because the llvm-exegesis-{8,9} from debian sid fails with that cryptic, unhelpful error. I suspect this will be a better error.
  287. [CMake] Replace LLVM_ENABLE_CXX1Y and friends with LLVM_CXX_STD Simplify building with particular C++ standards by replacing the specific "enable standard X" flags with a flag that allows specifying the standard you want directly. We preserve compatibility with the existing flags so that anyone with those flags in existing caches won't break mysteriously. Differential Revision: https://reviews.llvm.org/D60399
  288. [llvm-exegesis][X86] Randomize CMOVcc/SETcc OPERAND_COND_CODE CondCodes Reviewers: courbet, gchatelet Reviewed By: gchatelet Subscribers: tschuett, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60066
  289. Object/Minidump: Add support for reading the ModuleList stream Summary: The ModuleList stream consists of an integer giving the number of entries in the list, followed by the list itself. Each entry in the list describes a module (dynamically loaded objects which were loaded in the process when it crashed (or when the minidump was generated). The code for reading the list is relatively straight-forward, with a single gotcha. Some minidump writers are emitting padding after the "count" field in order to align the subsequent list on 8 byte boundary (this depends on how their ModuleList type was defined and the native alignment of various types on their platform). Fortunately, the minidump format contains enough redundancy (in the form of the stream length field in the stream directory), which allows us to detect this situation and correct it. This patch just adds the ability to parse the stream. Code for conversion to/from yaml will come in a follow-up patch. Reviewers: zturner, amccarth, jhenderson, clayborg Subscribers: jdoerfert, markmentovai, lldb-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60121
  290. [InstCombine] add more testcases for sdiv exact flag fixup.
  291. [X86] Make LowerOperationWrapper more robust. Remove now unnecessary ReplaceAllUsesWith from LowerMSCATTER. Previously LowerOperationWrapper took the number of results from the original node and counted that many results from the new node. This was intended to drop chain operands from FP_TO_SINT lowering that uses X87 with memory operations to stack temporaries. The final load had an extra chain output that needs to be ignored. Unfortunately, it didn't work with scatter which has 2 result operands, the mask output which is discarded and a chain output. The chain output is the one that is needed but it comes second and it would be dropped by the previous logic here. To workaround this we were doing a ReplaceAllUses in the lowering code so that the generic legalization code wouldn't see any uses to replace since it had been given the wrong result/type. After this change we take the LowerOperation result directly if the original node has one result. This allows us to directly return the chain from scatter or the load data from the FP_TO_SINT case. When the original node has multiple results we'll ensure the returned node has the same number and copy them over. For cases where the original node has multiple results and the new code for some reason has even more results, MERGE_VALUES can be used to pass only the needed results.
  292. [ConstantRange] Delete redundnt {z,s}extOrSelf for multiplication These calls are redundant because the quotients have the same BitWidth as MinValue/MaxValue.
  293. [InstCombine] add testcases for sdiv exact flag fixing - NFC.
  294. [InstCombine]add testcase for sdiv canonicalizetion - NFC
  295. [X86] Split floating point tests out of atomic-mi.ll into atomic-fp.ll. Add avx and avx512f command lines. NFC
  296. [X86] Add avx and avx512f command lines to atomic-non-integer.ll. NFC
  297. [llvm-objdump] Fix MC/ARM/arm-macho-calls.s
  298. [ConstantRange] Add signed/unsigned unionWith() This extends D59959 to unionWith(), allowing to specify that a non-wrapping unsigned/signed range is preferred. This is somewhat less useful than the intersect case, because union operations are rarer. An example use would the the phi union computed in SCEV. The implementation is mostly a straightforward use of getPreferredRange(), but I also had to adjust some <=/< checks to make sure that no ranges with lower==upper get constructed before they're passed to getPreferredRange(), as these have additional constraints. Differential Revision: https://reviews.llvm.org/D60377
  299. [X86] Use (SUBREG_TO_REG (MOV32rm)) for extloadi64i8/extloadi64i16 when the load is 4 byte aligned or better and not volatile. Summary: Previously we would use MOVZXrm8/MOVZXrm16, but those are longer encodings. This is similar to what we do in the loadi32 predicate. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60341
  300. [ConstantRangeTest] Generalize intersection testing code; NFC Extract the exhaustive intersection tests into a separate function, so that it may be reused for unions as well.
  301. [ConstantRange] Add unsigned and signed intersection types The intersection of two ConstantRanges may consist of two disjoint ranges. As we can only return one range as the result, we need to return one of the two possible ranges that cover both. Currently the result is picked based on set size. However, this is not always optimal: If we're in an unsigned context, we'd prefer to get a large unsigned range over a small signed range -- the latter effectively becomes a full set in the unsigned domain. This revision adds a PreferredRangeType, which can be either Smallest, Unsigned or Signed. Smallest is the current behavior and Unsigned and Signed are new variants that prefer not to wrap the unsigned/signed domain. The new type isn't used anywhere yet (but SCEV will be a good first user, see D60035). I've also added some comments to illustrate the various cases in intersectWith(), which should hopefully make it more obvious what is going on. Differential Revision: https://reviews.llvm.org/D59959
  302. [LLVM-C] Allow Access to the Type of a Binary Summary: Add an accessor for the type of a binary file. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: hiraditya, aheejin, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60366
  303. [ConstantRange] Add isAllNegative() and isAllNonNegative() methods Add isAllNegative() and isAllNonNegative() methods to ConstantRange, which determine whether all values in the constant range are negative/non-negative. This is useful for replacing KnownBits isNegative() and isNonNegative() calls when changing code to use constant ranges. Differential Revision: https://reviews.llvm.org/D60264
  304. Reapply [ValueTracking] Support min/max selects in computeConstantRange() Add support for min/max flavor selects in computeConstantRange(), which allows us to fold comparisons of a min/max against a constant in InstSimplify. This fixes an infinite InstCombine loop, with the test case taken from D59378. Relative to the previous iteration, this contains some adjustments for AMDGPU med3 tests: The AMDGPU target runs InstSimplify prior to codegen, which ends up constant folding some existing med3 tests after this change. To preserve these tests a hidden -amdgpu-scalar-ir-passes option is added, which allows disabling scalar IR passes (that use InstSimplify) for testing purposes. Differential Revision: https://reviews.llvm.org/D59506
  305. [llvm-objdump] Split disassembleObject and simplify --{start,stop}-address handling The main disassembly loop is hard to read due to special handling of ARM ELF data & ELF data. Split off the logic into two functions dumpARMELFData and dumpELFData. Hoist some checks outside of the loop. --start-address --stop-address have redundant checks and minor off-by-1 issues. Fix them.
  306. last changes for now
  307. various improvements in wording, also unbreak the bot
  308. [DWARF] DWARFDebugLine: delete unused parameter `Offset`
  309. make a bunch of cleanups in wording and tone
  310. [CostModel][X86] Masked load legalization requires an binary-shuffle not a select (PR39812) Expansion/truncation is better described by SK_PermuteTwoSrc than SK_Select
  311. remove some unhelpful language from the tutorial
  312. Copy the C++ kaleidoscope tutorial into a subdirectory and clean up various things, aligning with the direction of the WiCT workshop, and Meike Baumgärtner's view of how this should work. The old version of the documentation is unmodified, this is an experiment.
  313. [DAG] Pull out ComputeNumSignBits call to make debugging easier. NFCI.
  314. [X86][SSE] SimplifyDemandedBitsForTargetNode - Add initial PACKSS support In the case where we only want the sign bit (e.g. when using PACKSS truncation of comparison results for MOVMSK) then we can just demand the sign bit of the source operands. This makes use of the fact that PACKSS saturates out of range values to the min/max int values - so the sign bit is always preserved. Differential Revision: https://reviews.llvm.org/D60333
  315. [llvm-objdump] Fix split of source lines; don't ltrim source lines If the file does not end with a newline, it may be dropped. Fix the splitting algorithm. Also delete an unnecessary SourceCache lookup.
  316. [llvm-objdump] Simplify some ELF typename: ELFFile<ELFT>::Elf_xxx -> ELFT::xxx
  317. .
  318. [llvm-objdump] Simplify Expected<T> handling with unwrapOrError
  319. [ConstantRange] Shl considers full-set shifting to last bit position. if we do SHL of two 16-bit ranges like [0, 30000) with [1,2) we get "full-set" instead of what I would have expected [0, 60000) which is still in the 16-bit unsigned range. This patch changes the SHL algorithm to allow getting a usable range even in this case. Differential Revision: https://reviews.llvm.org/D57983
  320. [llvm-objdump] Simplify disassembleObject * Use std::binary_search to replace some std::lower_bound * Use llvm::upper_bound to replace some std::upper_bound * Use format_hex and support::endian::read{16,32}
  321. Change some StringRef::data() reinterpret_cast to bytes_begin() or arrayRefFromStringRef()
  322. [gn] Support for per-target runtime directory layout This change also introduces the clang_enable_per_target_runtime_dir to enable the use of per-target runtime directory layout which is the equivalent of LLVM_ENABLE_PER_TARGET_RUNTIME_DIR CMake option. Differential Revision: https://reviews.llvm.org/D60332
  323. [NFC] Fix typo in comment.
  324. [X86] When converting (x << C1) AND C2 to (x AND (C2>>C1)) << C1 during isel, try using andl over andq by favoring 32-bit unsigned immediates.
  325. [X86] combineBitcastvxi1 - provide dst VT and src SDValue directly. NFCI. Prep work to make it easier to reuse the BITCAST->MOVSMK combine in other cases.
  326. [X86] Use a signed mask in foldMaskedShiftToScaledMask to enable a shorter immediate encoding. This function reorders AND and SHL to enable the SHL to fold into an LEA. The upper bits of the AND will be shifted out by the SHL so it doesn't matter what mask value we use for these bits. By using sign bits from the original mask in these upper bits we might enable a shorter immediate encoding to be used.
  327. [X86] Add test cases to show missed opportunities to use a sign extended 8 or 32 bit immediate AND when reversing SHL+AND to form an LEA. When we shift the AND mask over we should shift in sign bits instead of zero bits. The scale in the LEA will shift these bits out so it doesn't matter whether we mask the bits off or not. Using sign bits will potentially allow a sign extended immediate to be used. Also add some other test cases for cases that are currently optimal.
  328. [X86] Autogenerate complete checks. NFC
  329. Fix spelling mistake. NFCI.
  330. [X86] Add AVX-target expandload and compressstore tests
  331. [llvm-exegesis][X86] Handle CMOVcc/SETcc OPERAND_COND_CODE OperandType Summary: D60041 / D60138 refactoring changed how CMOV/SETcc opcodes are handled. concode is now an immediate, with it's own operand type. This at least allows to not crash on the opcode. However, this still won't generate all the snippets with all the condcode enumerators. D60066 does that. Reviewers: courbet, gchatelet Reviewed By: gchatelet Subscribers: tschuett, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60057
  332. [X86] Split expandload and compressstore tests
  333. [X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order
  334. [CostModel][X86] Add more exhaustive masked load/store/gather/scatter/expand/compress cost tests
  335. [AMDGPU] Sort out and rename multiple CI/VI predicates Differential Revision: https://reviews.llvm.org/D60346
  336. [DWARF] Simplify DWARFDebugAranges::findAddress The current lower_bound approach has to check two iterators pos and pos-1. Changing it to upper_bound allows us to check one iterator (similar to DWARFUnitVector::getUnitFor*).
  337. [Symbolize] Uniquify sorted vector<pair<SymbolDesc, StringRef>>
  338. gn build: Pacify `gn format`
  339. [PDB Docs] Add documentation for the hash table format.
  340. [PDB Docs] The IPI Stream actually has index 4.
  341. [LLVM-C] Begin to Expose A More General Binary Interface Summary: Provides a new type, `LLVMBinaryRef`, and a binding to `llvm::object::createBinary` for more general interoperation with binary files than `LLVMObjectFileRef`. It also provides the proper non-consuming API for input buffers and populates an out parameter for error handling if necessary - two things the previous API did not do. In a follow-up, I'll define section and symbol iterators and begin to build upon the existing test infrastructure. This patch is a first step towards deprecating that API and replacing it with something more robust. Reviewers: deadalnix, whitequark Reviewed By: whitequark Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60322
  342. [gn] Support for building compiler-rt builtins This is support for building compiler-rt builtins, The library build should be complete for a subset of supported platforms, but not all CMake options have been replicated in GN. We always use the just built compiler to build all the runtimes, which is equivalent to the CMake runtimes build. This simplifies the build configuration because we don't need to support arbitrary host compiler and can always assume the latest Clang. With GN's toolchain support, this is significantly more efficient than the CMake runtimes build. Differential Revision: https://reviews.llvm.org/D60331
  343. [globalisel] Allow combiners to query legality
  344. [PDB Docs] Delete * LINKER * Stream information. This is actually just a module debug info stream, so it should technically be covered by a discussion of the module list.
  345. [InstCombine] add more tests for fmul+fdiv+sqrt; NFC
  346. [globalisel] Support 3-type legalForCartesianProduct()
  347. [LLVM-C] Add bindings to insert basic blocks Summary: Now that we can create standalone basic blocks, it's useful to be able to append them. Add bindings to - Insert a basic block after the current insertion block - Append a basic block to the end of a function's list of basic blocks Reviewers: whitequark, deadalnix, harlanhaskins Reviewed By: whitequark, harlanhaskins Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59658
  348. [X86] Enable tail calls for CallingConv::Swift It's currently only enabled on AArch64 (enabled in r281376).
  349. [X86] Preserve operand flag when expanding TCRETURNri The expansion of TCRETURNri(64) would not keep operand flags like undef/renamable/etc. which can result in machine verifier issues. Also add plumbing to be able to use `-run-pass=x86-pseudo`.
  350. [AMDGPU] Add MachineDCE pass after RenameIndependentSubregs Detect dead lanes can create some dead defs. Then RenameIndependentSubregs will break a REG_SEQUENCE which may use these dead defs. At this point a dead instruction can be removed but we do not run a DCE anymore. MachineDCE was only running before live variable analysis. The patch adds a mean to preserve LiveIntervals and SlotIndexes in case it works past this. Differential Revision: https://reviews.llvm.org/D59626
  351. [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228
  352. [X86] Merge the different SETcc instructions for each condition code into single instructions that store the condition code as an operand. Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between SETcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: andreadb, courbet, RKSimon, spatel, lebedev.ri Reviewed By: andreadb Subscribers: hiraditya, lebedev.ri, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60138
  353. [X86] Merge the different CMOV instructions for each condition code into single instructions that store the condition code as an immediate. Summary: Reorder the condition code enum to match their encodings. Move it to MC layer so it can be used by the scheduler models. This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between CMOV instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. This does complicate the scheduler models a little since we can't assign the A and BE instructions to a separate class now. I plan to make similar changes for SETcc and Jcc. Reviewers: RKSimon, spatel, lebedev.ri, andreadb, courbet Reviewed By: RKSimon Subscribers: gchatelet, hiraditya, kristina, lebedev.ri, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60041
  354. [gn] Rebase paths in symlink_or_copy against root_build_dir We should be always rebasing paths against root_build_dir which is the directory where scripts are run from, not root_out_dir which is the current toolchain directory. The latter can result in invalid paths when the action is being used from a non-default toolchain. Differential Revision: https://reviews.llvm.org/D60330
  355. [gn] Make -no-exceptions flag a config This allows it to be disabled for targets that need exceptions like libunwind, libc++abi and libc++. Differential Revision: https://reviews.llvm.org/D60328
  356. [LCG] Add aliased functions as LCG roots Current LCG doesn't check aliased functions. So if an internal function has a public alias it will not be added to CG SCC, but it is still reachable from outside through the alias. So this patch adds aliased functions to SCC. Differential Revision: https://reviews.llvm.org/D59898
  357. [AMDGPU] predicate and feature refactoring We have done some predicate and feature refactoring lately but did not upstream it. This is to sync. Differential revision: https://reviews.llvm.org/D60292
  358. Try to fix Sphinx bot.
  359. lit: make rm python 3 friendly (NFC) Add some alterations for python 3 compatibility.
  360. [PDB Docs] Finish documentation for PDB Info Stream. The information about the named stream map and feature codes was not present. This patch adds it.
  361. [PDB Docs] Add info about the hash adjustment buffer. This necessitates adding a document describing the serialized hash table format. This document is currently empty, although it will be filled out in followup patches.
  362. gn build: Merge 357768 and 357770
  363. [InstCombine] add tests for fdiv+fmul; NFC
  364. gn build: Merge r357719
  365. [InstCombine] add tests for sqrt+fdiv+fmul; NFC Examples based on recent llvm-dev thread. These are specific patterns of more general enhancements that would solve these.
  366. lit: support long paths on Windows Use ctypes to call into SHFileOperationW with the extended NT path to allow us to remove paths which exceed 261 characters on Windows. This functionality is exercised by swift's test suite.
  367. Add documentation for PDB TPI/IPI Stream.
  368. [InstCombine] add test to show reassociation that creates a denormal constant; NFC
  369. Revert "[llvm-readobj] Improve error message for --string-dump" This reverts commit 681b0798dbbc6b3500c9930977ec8a274b142acb. Reverted due to causing build failures: llvm-svn: 357772
  370. Change some dyn_cast to more apropriate isa. NFC
  371. [llvm-readobj] Improve error message for --string-dump Fixes bug 40630: https://bugs.llvm.org/show_bug.cgi?id=40630 This patch changes the error message when the section specified by --string-dump cannot be found by including the name of the section in the error message and changing the prefix text to not imply that the file itself was invalid. As part of this change some uses of std::error_code have been replaced with the llvm Error class to better encapsulate the error info (rather than passing File strings around), and the WithColor class replaces string literal error prefixes. Differential Revision: https://reviews.llvm.org/D59946
  372. [format] Add correct punctuation to comment Test commit that adds a grammatically correct full stop to a single comment.
  373. Add an option do not dump the generated object on disk Reviewers: courbet Subscribers: llvm-commits, bdb Tags: #llvm Differential Revision: https://reviews.llvm.org/D60317
  374. [ExpandMemCmp][NFC] Add tests for `memcmp(p, q, n) < 0` case.
  375. [SelectionDAG] Add fcmp UNDEF handling to SelectionDAG::FoldSetCC Second half of PR40800, this patch adds DAG undef handling to fcmp instructions to match the behavior in llvm::ConstantFoldCompareInstruction, this permits constant folding of vector comparisons where some elements had been reduced to UNDEF (by SimplifyDemandedVectorElts etc.). This involves a lot of tweaking to reduced tests as bugpoint loves to reduce fcmp arguments to undef........ Differential Revision: https://reviews.llvm.org/D60006
  376. GlobalISel: Add another overload of buildUnmerge It's annoying to have to create an array of the result type, particularly when you don't care about the size of the value.
  377. AMDGPU/GlobalISel: Fix non-power-of-2 select
  378. [llvm] Add isa_and_nonnull Summary: Add new ``isa_and_nonnull<>`` operator that works just like the ``isa<>`` operator, except that it allows for a null pointer as an argument (which it then returns false). Reviewers: lattner, aaron.ballman, greened Reviewed By: lattner Subscribers: hubert.reinterpretcast, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60291
  379. [DAGCombiner][x86] scalarize splatted vector FP ops There are a variety of vector patterns that may be profitably reduced to a scalar op when scalar ops are performed using a subset (typically, the first lane) of the vector register file. For x86, this is true for float/double ops and element 0 because insert/extract is just a sub-register rename. Other targets should likely enable the hook in a similar way. Differential Revision: https://reviews.llvm.org/D60150
  380. [TextAPI] Fix off-by-one error in the bit index extraction loop The loop in findNextSetBit() runs one pass more than it should. On 64-bit architectures this does not cause a problem, but 32-bit architectures mask the shift count to 5 bits which limits the number of shifts inside a range of 0 to 31. Shifting by 32 has the same effect as shifting by 0, so if the first bit in the set is 1, the function will return with Index different from EndIndexVal. Because of that, range-based for loops iterating thorough architectures will continue until hitting a 0 in the set, resulting in n additional iterations, where n is equal to the number of consecutive 1 bits at the start the set. Ultimately TBDv1.WriteFile and TBDv2.WriteFile will output additional architectures causing a failure in the unit tests. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D60198
  381. [Symbolize] Replace map<SymbolDesc, StringRef> with sorted vector
  382. [X86][AVX] Add PR34584 masked store test cases
  383. [X86] Add SSE/AVX1/AVX2 masked trunc+store tests
  384. Fix r357749 for big-endian architectures We need to read the strings from the minidump files as little-endian, regardless of the host byte order. I definitely remember thinking about this case while writing the patch (and in fact, I have implemented that for the "write" case), but somehow I have ended up not implementing the byte swapping when reading the data. This adds the necessary byte-swapping and should hopefully fix test failures on big-endian bots.
  385. [RISCV] Implement adding a displacement to a BlockAddress Recent change rL357393 uses MachineInstrBuilder::addDisp to add a based on a BlockAddress but this case was not implemented. This patch adds the missing case and a test for RISC-V that exercises the new case. Differential Revision: https://reviews.llvm.org/D60136
  386. Fix MSVC build for r357749 MSVC found the bare "make_unique" invocation ambiguous (between std:: and llvm:: versions). Explicitly qualifying the call with llvm:: should hopefully fix it.
  387. Minidump: Add support for reading/writing strings Summary: Strings in minidump files are stored as a 32-bit length field, giving the length of the string in *bytes*, which is followed by the appropriate number of UTF16 code units. The string is also supposed to be null-terminated, and the null-terminator is not a part of the length field. This patch: - adds support for reading these strings out of the minidump file (this implementation does not depend on proper null-termination) - adds support for writing them to a minidump file - using the previous two pieces implements proper (de)serialization of the CSDVersion field of the SystemInfo stream. Previously, this was only read/written as hex, and no attempt was made to access the referenced string -- now this string is read and written correctly. The changes are tested via yaml2obj|obj2yaml round-trip as well as a unit test which checks the corner cases of the string deserialization logic. Reviewers: jhenderson, zturner, clayborg Subscribers: llvm-commits, aprantl, markmentovai, amccarth, lldb-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59775
  388. [SelectionDAG] Compute known bits of CopyFromReg Summary: Teach SelectionDAG how to compute known bits of ISD::CopyFromReg if the virtual reg used has one def only. This can be particularly useful when calling isBaseWithConstantOffset() with the ISD::CopyFromReg argument, as more optimizations may get enabled in the result. Also add a missing truncation on X86, found by testing of this patch. Change-Id: Id1c9fceec862d118c54a5b53adf72ada5d6daefa Reviewers: bogner, craig.topper, RKSimon Reviewed By: RKSimon Subscribers: lebedev.ri, nemanjai, jvesely, nhaehnle, javed.absar, jsji, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59535
  389. [X86] Promote i16 SRA instructions to i32 We already promote SRL and SHL to i32. This will introduce sign extends sometimes which might be harder to deal with than the zero we use for promoting SRL. I ran this through some of our internal benchmark lists and didn't see any major regressions. I think there might be some DAG combine improvement opportunities in the test changes here. Differential Revision: https://reviews.llvm.org/D60278
  390. [FastISel] Fix crash for gc.relocate lowring Lowering safepoint checks that all gc.relocaes observed in safepoint must be lowered. However Fast-Isel is able to skip dead gc.relocate. To resolve this issue we just ignore dead gc.relocate in the check. Reviewers: reames Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D60184
  391. NFC: Move API uses of MD5::MD5Result to Optional rather than a pointer. Differential Revision: https://reviews.llvm.org/D60290
  392. Include invoke'd functions for recursive extract Summary: When recursively extracting a function from a bit code file, include functions mentioned in InvokeInst as well as CallInst Reviewers: loladiro, espindola, volkan Reviewed By: loladiro Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60231
  393. An unreachable block may have a route to a reachable block, don't fast-path return that it can't. A block reachable from the entry block can't have any route to a block that's not reachable from the entry block (if it did, that route would make it reachable from the entry block). That is the intended performance optimization for isPotentiallyReachable. For the case where we ask whether an unreachable from entry block has a route to a reachable from entry block, we can't conclude one way or the other. Fix a bug where we claimed there could be no such route. The fix in rL357425 ironically reintroduced the very bug it was fixing but only when a DominatorTree is provided. This fixes the remaining bug.
  394. [TextAPI] Prefix all architecture enums to fix the build on i386. Summary: This changes the Architecture enum to use a prefix (AK_) to prevent the preprocessor from replacing i386 with 1 when building llvm/clang for i386. Reviewers: steven_wu, lhames, mstorsjo Reviewed By: mstorsjo Subscribers: hiraditya, jkorous, dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60241
  395. [IR] Refactor attribute methods in Function class (NFC) Rename the functions that query the optimization kind attributes. Differential revision: https://reviews.llvm.org/D60287
  396. Make SourceManager::createFileID(UnownedTag, ...) take a const llvm::MemoryBuffer* Requires making the llvm::MemoryBuffer* stored by SourceManager const, which in turn requires making the accessors for that return const llvm::MemoryBuffer*s and updating all call sites. The original motivation for this was to use it and fix the TODO in CodeGenAction.cpp's ConvertBackendLocation() by using the UnownedTag version of createFileID, and since llvm::SourceMgr* hands out a const llvm::MemoryBuffer* this is required. I'm not sure if fixing the TODO this way actually works, but this seems like a good change on its own anyways. No intended behavior change. Differential Revision: https://reviews.llvm.org/D60247
  397. Fix some MCTargetOptions Doxygen comments (NFC)
  398. Revert [X86] When using Win64 ABI, exit with error if SSE is disabled for varargs It unnecessarily breaks previously-working code which used varargs, but didn't pass any float/double arguments (such as EDK2). Also revert the fixup on top of that: Revert [X86] Fix a test from r357317 This reverts r357317 (git commit d413f41de6baf500e5d20c638375447e18777db2) This reverts r357380 (git commit 7af32444b9b17719ebabb6bee6eb52465acc8507)
  399. Appease STLs where std::atomic<void*> lacks a constexpr default ctor MSVC 2019 casts the pointer to a pointer-sized integer, which is a reinterpret_cast, which is invalid in a constexpr context, so I have to remove the LLVM_REQUIRES_CONSTANT_INITIALIZATION annotation for now.
  400. [WebAssembly] Apply data relocations at runtime in shared objects See: https://github.com/WebAssembly/tool-conventions/blob/master/DynamicLinking.md Data section relocations in wasm shared libraries are applied by the library itself at static constructor time. This change adds a new synthetic function that applies relocations to relevant memory locations on startup. Differential Revision: https://reviews.llvm.org/D59278
  401. Ensure that ManagedStatic is constant initialized in MSVC 2017 & 2019 Fixes PR41367. This effectively relands r357655 with a workaround for MSVC 2017. I tried various approaches with unions, but I ended up going with this ifdef approach because it lets us write the proper C++11 code that we want to write, with a separate workaround that we can delete when we drop MSVC 2017 support. This also adds LLVM_REQUIRE_CONSTANT_INITIALIZATION, which wraps [[clang::require_constant_initialization]]. This actually detected a minor issue when using clang-cl where clang wasn't able to use the constexpr constructor in MSVC's STL, so I switched back to using the default ctor of std::atomic<void*>.
  402. [WebAssembly] Add new explicit relocation types for PIC relocations See https://github.com/WebAssembly/tool-conventions/pull/106 Differential Revision: https://reviews.llvm.org/D59907
  403. [llvm-objcopy] [llvm-symbolizer] Fix failing tests Summary: Fix failing tests that matched substrings in path. Reviewers: evgeny777, mattd, espindola, alexshap, rupprecht, jhenderson Reviewed By: jhenderson Subscribers: Bulletmagnet, emaste, arichardson, jakehehrlich, MaskRay, rupprecht, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60170
  404. llvm-dwarfdump: Support alternative architecture names in the -arch filter <rdar://problem/47918606>
  405. [x86] eliminate unnecessary broadcast of horizontal op This is another pattern that comes up if we more aggressively scalarize FP ops.
  406. [llvm] [cmake] Add additional headers only if they exist Modify the add_header_files_for_glob() function to only add files that do exist, rather than all matches of the glob. This fixes CMake error when one of the include directories (which happen to include /usr/include) contain broken symlinks. Differential Revision: https://reviews.llvm.org/D59632
  407. [RISCV] Support assembling TLS add and associated modifiers This patch adds support in the MC layer for parsing and assembling the 4-operand add instruction needed for TLS addressing. This also involves parsing the %tprel_hi, %tprel_lo and %tprel_add operand modifiers. Differential Revision: https://reviews.llvm.org/D55341
  408. [COFF] Fix delay import directory iterator Summary: Take the Index into account in `getDelayImportTable`, otherwise we always return the entry for the first delay DLL reference. Reviewers: ruiu Reviewed By: ruiu Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60081
  409. [SystemZ] Bugfix in isFusableLoadOpStorePattern() This function is responsible for checking the legality of fusing an instance of load -> op -> store into a single operation. In the SystemZ backend the check was incomplete and a test case emerged with a cycle in the instruction selection DAG as a result. Instead of using the NodeIds to determine node relationships, hasPredecessorHelper() now is used just like in the X86 backend. This handled the failing tests and as well gave a few additional transformations on benchmarks. The SystemZ isFusableLoadOpStorePattern() is now a very near copy of the X86 function, and it seems this could be made a utility function in common code instead. Review: Ulrich Weigand https://reviews.llvm.org/D60255
  410. [yaml2obj] - Check we correctly set the sh_info field of .symtab section. initSymtabSectionHeader has the following line: SHeader.sh_info = findLocalsNum(Symbols) + 1; As was mentioned in a review comments for D60122, it is never tested. The patch adds a test. Differential revision: https://reviews.llvm.org/D60192
  411. Revert rL357655 and rL357656 from llvm/trunk: Fix minor innaccuracy in previous comment on ManagedStaticBase ........ Make ManagedStatic constexpr constructible Apparently it needs member initializers so that it can be constructed in a constexpr context. I explained my investigation of this in PR41367. ........ Causes vs2017 debug llvm-tblgen to fail with "Unknown command line argument" errors - similar to the vs2019 error discussed on PR41367 without the patch....
  412. [Symbolize] Keep SymbolDescs with the same address and improve getNameFromSymbolTable heuristic I'll follow up with better heuristics or tests.
  413. [ARM GlobalISel] Support DBG_VALUE Make sure we can map and select DBG_VALUE.
  414. [SLP][X86] Regenerate operandorder tests with arguments on same line. NFCI. Stops update_test_checks.py from splitting the later arguments after the CHECKs.
  415. [AArch64][AsmParser] Fix .arch_extension directive parsing This patch fixes .arch_extension directive parsing to handle a wider range of architecture extension options. The existing parser was parsing extensions as an identifier which breaks for extensions containing a "-", such as the "tlb-rmi" extension. The extension is now parsed as a string. This is consistent with the extension parsing in the .arch and .cpu directive parsing. Patch by Cullen Rhodes (c-rhodes) Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D60118
  416. [llvm-symbolizer] Allow more flexible usage of -e. addr2line allows -e to be grouped with other options; it also allows it to prefix the value. Thus, all the following usages are possible: * addr2line -f -e <bin> <addr> * addr2line -fe <bin> <addr> * addr2line -f e<bin> <addr> * addr2line -fe<bin> <addr> This patch adds the same for llvm-symbolizer. Differential Revision: https://reviews.llvm.org/D60196
  417. [llvm-symbolizer] Add `--output-style` switch. In general, llvm-symbolizer follows the output style of GNU's addr2line. However, there are still some differences; in particular, for a requested address, llvm-symbolizer prints line and column, while addr2line prints only the line number. This patch adds a new switch to select the preferred style. Differential Revision: https://reviews.llvm.org/D60190
  418. [InstCombine] Combine no-wrap sub and icmp w/ constant. Teach InstCombine the transformation `(icmp P (sub nuw|nsw C2, Y), C) -> (icmp swap(P) Y, C2-C)` Reviewers: majnemer, apilipenko, sanjoy, spatel, lebedev.ri Reviewed By: lebedev.ri Subscribers: dmgreen, lebedev.ri, nikic, hiraditya, JDevlieghere, jfb, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59916
  419. [X86] Use INSERT_SUBREG rather than SUBREG_TO_REG when creating LEA64_32 during isel. SUBREG_TO_REG is supposed to be used to assert that we know the upper bits are zero. But that isn't the case here. We've done no analysis of the inputs.
  420. [FastISel] Fix the crash in gc.result lowering The Fast ISel has a fallback to SelectionDAGISel in case it cannot handle the instruction. This works as follows: Using reverse order, try to select instruction using Fast ISel, if it cannot handle instruction it fallbacks to SelectionDAGISel for these instructions if it is a call and continue fast instruction selections. However if unhandled instruction is not a call or statepoint related instruction it fallbacks to SelectionDAGISel for all remaining instructions in basic block. However gc.result instruction is missed and as a result it is possible that gc.result is processed earlier than statepoint causing breakage invariant the gc.results should be handled after statepoint. Test is updated because in the current form fast-isel cannot handle ret instruction (due to i1 ret type without explicit ext) and as a result test does not check fast-isel at all. Reviewers: reames Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D60182
  421. Revert r357452 - 'SimplifyCFG SinkCommonCodeFromPredecessors: Also sink function calls without used results (PR41259)' This revision causes tests to fail under ASAN. Since the cause of the failures is not clear (could be ASAN, could be a Clang bug, could be a bug in this revision), the safest course of action seems to be to revert while investigating.
  422. gn build: Merge r357663
  423. [WebAssembly] EmscriptenEHSjLj: Don't abort if __THREW__ is defined This allows __THREW__ to be defined in the current module, although it is still required to be a GlobalVariable. In emscripten we want to be able to compile the source code that defines this symbols. Previously we were avoid this by not running this pass when building that compiler-rt library, but I have change out to build it using the normal compiler path: https://github.com/emscripten-core/emscripten/pull/8391 Differential Revision: https://reviews.llvm.org/D60232
  424. [XCOFF] Add functionality for parsing AIX XCOFF object file headers Summary: 1. Add functionality for parsing AIX XCOFF object files headers. 2. Only support 32-bit AIX XCOFF object files in this patch. 3. Print out the AIX XCOFF object file header in YAML format. Reviewers: sfertile, hubert.reinterpretcast, jasonliu, mstorsjo, zturner, rnk Reviewed By: sfertile, hubert.reinterpretcast Subscribers: jsji, mgorny, hiraditya, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59419 Patch by Digger Lin
  425. [Support] On AIX, Check ENOTSUP on posix_fallocate instead of EOPNOTSUPP Summary: `posix_fallocate` can fail if the underlying filesystem does not support it; and, on AIX, such a failure is reported by a return value of `ENOTSUP`. The existing code checks only for `EOPNOTSUPP`, which may share the same value as `ENOTSUP`, but is not required to. Reviewers: xingxue, sfertile, jasonliu Reviewed By: xingxue Subscribers: kristina, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60175
  426. [AIX] SelectionDAGNodes.h: Pack bit-fields that are meant to be packed Summary: Certain classes in the subject file are expected to provide different views of a two-byte field as a collection of various bit-fields. On AIX, the canonical layout of bit-fields would cause these classes to span four bytes. Applying the `pack` pragma for compilers that employ the AIX canonical layout allows these classes to fit within the expected two bytes. In the future, the pragma would also likely need to be applied when building with Clang on AIX. Reviewers: xingxue, sfertile, jasonliu Reviewed By: xingxue Subscribers: jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60164
  427. [gn] Use "$link /lib" for archives instead of lib.exe Summary: This avoids the need to talk about lib.exe or llvm-lib.exe and it does the right thing with LLD. Reviewers: thakis Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60155
  428. [X86] Remove CustomInserters for RDPKRU/WRPKRU. Use some custom lowering and new ISD opcodes instead. These inserters inserted some instructions to zero some registers and copied from virtual registers to physical registers. This change instead inserts the zeros directly into the DAG at lowering time using new ISD opcodes that take the extra zeroes as inputs. The zeros will then go through isel on their own to select the MOV32r0 pseudo. Then we just need to mention the physical registers directly in the isel patterns and the isel table and InstrEmitter will take care of inserting the necessary copies to/from physical registers.
  429. [codeview] Remove Type member from CVRecord Summary: Now CVType and CVSymbol are effectively type-safe wrappers around ArrayRef<uint8_t>. Make the kind() accessor load it from the RecordPrefix, which is the same for types and symbols. Reviewers: zturner, aganea Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60018
  430. Fix minor innaccuracy in previous comment on ManagedStaticBase
  431. Make ManagedStatic constexpr constructible Apparently it needs member initializers so that it can be constructed in a constexpr context. I explained my investigation of this in PR41367.
  432. llvm-undname: Name a pair. No behavior change. Differential Revision: https://reviews.llvm.org/D60210
  433. [X86] Remove CustomInserter pseudos for MONITOR/MONITORX/CLZERO. Use custom instruction selection instead. This custom inserter existed so we could do a weird thing where we pretended that the instructions support a full address mode instead of taking a pointer in EAX/RAX. I think was largely so we could be pointer size agnostic in the isel pattern. To make this work we would then put the address into an LEA into EAX/RAX in front of the instruction after isel. But the LEA is overkill when we just have a base pointer. So we end up using the LEA as a slower MOV instruction. With this change we now just do custom selection during isel instead and just assign the incoming address of the intrinsic into EAX/RAX based on its size. After the intrinsic is selected, we can let isel take care of selecting an LEA or other operation to do any address computation needed in this basic block. I've also split the instruction into a 32-bit mode version and a 64-bit mode version so the implicit use is properly sized based on the pointer. Without this we get comments in the assembly output about killing eax and defing rax or vice versa depending on whether we define the instruction to use EAX/RAX.
  434. [X86] Remove dead CHECK lines for a test. NFC
  435. [X86] Autogenerate checks. NFC
  436. llvm-undname: Fix a crash-on-invalid Found by oss-fuzz, fixes issue 13260 on oss-fuzz. Differential Revision: https://reviews.llvm.org/D60207
  437. llvm-undame: Fix an assert-on-invalid Found by oss-fuzz, fixes issue 12432 on os-fuzz. Differential Revision: https://reviews.llvm.org/D60206
  438. llvm-undname: Fix an assert-on-invalid Found by oss-fuzz, fixes issues 12428 and 12429 on oss-fuzz. Differential Revision: https://reviews.llvm.org/D60204
  439. llvm-undname: Fix a crash-on-invalid Found by oss-fuzz, fixes issues 12435 and 12438 on oss-fuzz. Differential Revision: https://reviews.llvm.org/D60202
  440. llvm-cxxfilt: Demangle gcc "old-style unified" ctors and dtors These are variant 4, cf https://github.com/gcc-mirror/gcc/blob/master/gcc/cp/mangle.c#L1851 https://github.com/gcc-mirror/gcc/blob/master/gcc/cp/mangle.c#L1880 and gcc seems to sometimes emit them still. Differential Revision: https://reviews.llvm.org/D60229
  441. [x86] fold shuffles of h-ops that have an undef operand If an operand is undef, we can assume it's the same as the other operand.
  442. [x86] eliminate movddup of horizontal op This pattern would show up as a regression if we more aggressively convert vector FP ops to scalar ops. There's still a missed optimization for the v4f64 legal case (AVX) because we create that h-op with an undef operand. We should probably just duplicate the operands for that pattern to avoid trouble.
  443. [IR] Create new method in `Function` class (NFC) Create method `optForNone()` testing for the function level equivalent of `-O0` and refactor appropriately. Differential revision: https://reviews.llvm.org/D59852
  444. [x86] add another test for disguised h-op; NFC
  445. AMDGPU: Split block for si_end_cf Relying on no spill or other code being inserted before this was precarious. It relied on code diligently checking isBasicBlockPrologue which is likely to be forgotten. Ideally this could be done earlier, but this doesn't work because of phis. Any other instruction can't be placed before them, so we have to accept the position being incorrect during SSA. This avoids regressions in the fast register allocator rewrite from inverting the direction.
  446. [x86] add test for disguised horizontal op; NFC
  447. [dwarfdump] Remove bogus verifier error The standard doesn't require a DW_TAG_variable, DW_TAG_formal_parameter or DW_TAG_constant to A DW_AT_type attribute describing the type of the variable. It only specifies that it *can* have one.
  448. [ProfileSummary] Count callsite samples when computing total samples. Summary: Currently ProfileSummaryBuilder doesn't count into callsite samples when computing total samples. Considering that ProfileSummaryInfo is used to checked the hotness of not only body samples but also callsite samples (from SampleProfileLoader), I think the callsite sample counts should be considered when computing total samples. Reviewers: eraman, danielcdh, wmi Subscribers: hiraditya, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59835
  449. gn build: Add build file for dexp None of check-clang-tools's tests run this, but the CMake check-clang-tools depends on the binary, so add it for consistency. Differential Revision: https://reviews.llvm.org/D60222
  450. AMDGPU/NFC: Add offset field to arg metadata (required for code object v3)
  451. [X86] Extend boolean arguments to inline-asm according to getBooleanType Differential Revision: https://reviews.llvm.org/D60208
  452. [X86][AVX] combineHorizontalPredicateResult - split any/allof v16i16/v32i8 reduction on AVX1 Perform the 2 x 128-bit lo/hi OR/AND on the vectors before calling PMOVMSKB on the 128-bit result.
  453. [X86][AVX] combineHorizontalPredicateResult - support v16i16/v32i8 reduction on AVX1 Use getPMOVMSKB helper which splits v32i8 MOVMSK calls on pre-AVX2 targets.
  454. [DWARF] check whether the DIE is valid before querying for information Differential Revision: https://reviews.llvm.org/D60147
  455. [AArch64][GlobalISel] Legalize G_FEXP2 Same as G_EXP. Add a test, and update legalizer-info-validation.mir and f16-instructions.ll. Differential Revision: https://reviews.llvm.org/D60165
  456. [x86] make stack folding tests immune to unrelated transforms; NFC
  457. [DAGCombiner] Rename variables Demanded -> DemandedBits/DemandedElts. NFCI. Use consistent variable names down the SimplifyDemanded* call stack so debugging isn't such a annoyance.
  458. Test commit: Remove double variable assignment
  459. [llvm-readobj] - Fix 2 test cases. https://reviews.llvm.org/D60122 (r357595) changed the symbols description format. This change fix two more new test cases to fix BB: http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/16205/steps/test-stage1-compiler/logs/stdio
  460. [SystemZ] Improve codegen for certain SADDO-immediate cases When performing an add-with-overflow with an immediate in the range -2G ... -4G, code currently loads the immediate into a register, which generally takes two instructions. In this particular case, it is preferable to load the negated immediate into a register instead, which always only requires one instruction, and then perform a subtract.
  461. [yaml2obj][obj2yaml] - Change how symbol's binding is descibed when parsing/dumping. Currently, YAML has the following syntax for describing the symbols: Symbols: Local: LocalSymbol1: ... LocalSymbol2: ... ... Global: GlobalSymbol1: ... Weak: ... GNUUnique: I.e. symbols are grouped by their bindings. That is not very convenient, because: It does not allow to set a custom binding, what can be useful for producing broken/special outputs for test cases. Adding a new binding would require to change a syntax (what we observed when added GNUUnique recently). It does not allow to change the order of the symbols in .symtab/.dynsym, i.e. currently all Local symbols are placed first, then Global, Weak and GNUUnique are following, but we are not able to change the order. It is not consistent. Binding is just one of the properties of the symbol, we do not group them by other properties. It makes the code more complex that it can be. This patch shows it can be simplified with the change performed. The patch changes the syntax to just: Symbols: Symbol1: ... Symbol2: ... ... With that, we are able to work with the binding field just like with any other symbol property. Differential revision: https://reviews.llvm.org/D60122
  462. [NFC] Address missed review comment for test Reviewed by: grimar Differential Revision: https://reviews.llvm.org/D60200
  463. [x86] remove duplicate tests Accidentally double-committed these.
  464. [x86] add negative tests for FP scalarization; NFC These go with the proposal in D60150.
  465. [x86] add tests with constants for FP scalarization; NFC
  466. [llvm-objcopy] Make section rename/set flags case-insensitive This fixes https://bugs.llvm.org/show_bug.cgi?id=41305. GNU objcopy --set-section-flags/--rename-section flags are case-insensitive, so this patch updates llvm-objcopy to match. Reviewed by: grimar Differential Revision: https://reviews.llvm.org/D60200
  467. [x86] add tests with constants for FP scalarization; NFC
  468. [MIPS GlobalISel] Select floating point arithmetic operations Select 32 and 64 bit floating point add, sub, mul and div for MIPS32. Differential Revision: https://reviews.llvm.org/D60191
  469. [AArch64] Update v8.5a MTE LDG/STG instructions The latest MTE specification adds register Xt to the STG instruction family: STG [Xn, #offset] -> STG Xt, [Xn, #offset] The tag written to memory is taken from Xt rather than Xn. Also, the LDG instruction also was changed to read return address from Xt: LDG Xt, [Xn, #offset]. This patch includes those changes and tests. Specification is at: https://developer.arm.com/docs/ddi0596/c Differential Revision: https://reviews.llvm.org/D60188
  470. AMDGPU: Fix copy/paste error in intrnsic comment
  471. [DAGCombiner] loosen restrictions for moving shuffles after vector binop There are 3 changes to make this correspond to the same transform in instcombine: 1. Remove the legality check - we can't create anything less legal than we started with. 2. Ease the use restriction, so we only bail out if both operands have >1 use. 3. Ease the use restriction for binops with a repeated operand (eg, mul x, x). As discussed in D60150, there's a scalarization opportunity that will be made easier by allowing this transform more generally.
  472. [llvm-readobj] Add GNU style dumper for .gnu.version section Summary: Currently, `llvm-readobj` do not support GNU style dumper for symbol versioning sections. In this patch, I would like to implement dumper for `.gnu.version` section Reviewers: jhenderson, rupprecht, grimar Reviewed By: jhenderson, rupprecht Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59877
  473. [llvm-nm]Add support for --no-demangle GNU nm has --no-demangle, so llvm-nm should too. It disables the --demangle switch. The patch also allows --demangle to be specified multiple times (the last of all --no-demangle/--demangle switches takes precedence). Reviewed by: grimar, rupprecht, mattd Differential Revision: https://reviews.llvm.org/D60134
  474. gn build: Add build files for clangd xpc framework code This is a bit of a larger change since this is the first (and as far as I can tell only) place where the LLVM build produces macOS framework bundles. GN has some built-in support for this, so use that. `gn help create_bundle` has a terse description (but it's a bit outdated: `deps` must be `public_deps` and the conditionals in the example in the help aren't quite right on non-iOS). We need a new 'copy_bundle_data' tool, and since we copy the clangd.xpc bundle as bundle_data into ClangdXPC.framework it needs to be able to handle directories in addition to files. GN also insists we have a compile_xcassets tool even though it's not used. I just made that run `false`. Despite GN's support for bundles, we still need to manually create the expected symlink structure in the .framework bundle. Since this code never runs on Windows, it's safe to create the symlinks before the symlink targets exist, so we can just make the bundle depend on the steps that create the symlinks. For this to work, change the symlink script to create the symlink's containing directory if it doesn't yet exist. I locally verified that CMake and GN build create the same bundle structure. (I noticed that both builds set LC_ID_DYLIB to the pre-copy libClangdXPCLib.dylib name, but that seems to not cause any issues and it happens in the CMake build too.) (Also add an error message to clangd-xpc-test-client for when loading the dylib fails – this was useful while locally debugging this.) Differential Revision: https://reviews.llvm.org/D60130
  475. [X86] Regenerate LEA codegen tests
  476. [DAGCombine] Don't use getZExtValue() until we know the constant is in range. Noticed during prep for a patch for PR40758.
  477. [mips] Remove unused FGRH32 register class. NFC If we need this class in the future we will easily restore it. Differential Revision: http://reviews.llvm.org/D60132
  478. [X86] Make the post machine scheduler macrofusion-aware. Summary: Given that X86 does not use this currently, this is an NFC. I'll experiment with enabling and will report numbers. Reviewers: andreadb, lebedev.ri Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60185
  479. [X86][NFC] Add tests for misched macro-fusion.
  480. [InstCombine] Simplify ctpop with bitreverse/bswap Summary: Fixes PR41337 Reviewers: spatel Reviewed By: spatel Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60148
  481. Revert r357256 "[DAGCombine] Improve Lifetime node chains." As it caused a pathological compile-time regressionin V8, see PR41352. > Improve both start and end lifetime nodes chain dependencies. > > Reviewers: courbet > > Reviewed By: courbet > > Subscribers: hiraditya, llvm-commits > > Tags: #llvm > > Differential Revision: https://reviews.llvm.org/D59795 This also reverts the follow-up r357309: > [DAGCombiner] Rewrite ImproveLifetimeNodeChain to avoid DAG loop. > > Avoid EXPENSIVE_CHECK failure. NFCI.
  482. [PowerPC]add testcase for ppcctrloops pass shortloop check
  483. Fix TargetLibraryInfoTest.ValidProto after rL357552
  484. AMDGPU: Assume ECC is enabled by default if supported The test should really be checking for the property directly in the code object headers, but there are problems with this. I don't see this directly represented in the text form, and for the binary emission this is depending on a function level subtarget feature to emit a global flag.
  485. [WebAssembly] Add Emscripten OS definition + small_printf The Emscripten OS provides a definition of __EMSCRIPTEN__, and also that it supports iprintf optimizations. Also define small_printf optimizations, which is a printf with float support but not long double (which in wasm can be useful since long doubles are 128 bit and force linking of float128 emulation code). This part is based on sunfish's https://reviews.llvm.org/D57620 (which can't land yet since the WASI integration isn't ready yet). Differential Revision: https://reviews.llvm.org/D60167
  486. InstSimplify: Fold round intrinsics from sitofp/uitofp https://godbolt.org/z/gEMRZb
  487. [WebAssembly] Remove unneeded target operand flags This change is in preparation for the addition of new target operand flags for new relocation types. Have a symbol type as part of the flag set makes it harder to use and AFAICT these are serving no purpose. Differential Revision: https://reviews.llvm.org/D60014
  488. [X86] Update the test case for v4i1 bitselect in combine-bitselect.ll to not have an infinite loop in IR. In fact we don't even need a loop at all. I backed out the bug fix this was testing for and verified that this new case hit the same issue. This should stop D59626 from deleting some of this code by realizing it was dead due to the loop.
  489. [X86] Autogenerate complete checks. NFC
  490. AMDGPU: Remove unnecessary subtarget get
  491. AMDGPU: Fix names for generation features We should overall stop using these, but the uppercase name didn't work. Any feature string is converted to lowercase, so these could never be found in the table.
  492. AMDGPU: Don't use the default cpu in a few tests Avoids unnecessary test changes in a future commit.
  493. [GlobalISel] Add IRTranslator support for llvm.stacksave and llvm.stackrestore Also update arm64-irtranslator.ll. Differential Revision: https://reviews.llvm.org/D60140
  494. X86: regenerate speculative-load-hardening-indirect.ll tests. NFC.
  495. [COFF] Reduce the size of Chunk and SectionChunk, NFC Summary: Reorder the fields in both to use padding more efficiently, and add more comments on the purpose of the fields. Replace `std::vector<SectionChunk*> AssociativeChildren` with a singly-linked list. This avoids the separate vector allocation to list associative children, and shrinks the 3 pointers used for the typically empty vector down to 1. In the end, this reduces the sum of heap allocations used to link browser_tests.exe with NO PDB by 13.10%, going from 2,248,728 KB to 1,954,071 KB of heap. These numbers exclude memory mapped files, which are of course a significant factor in LLD's memory usage. Reviewers: ruiu, mstorsjo, aganea Subscribers: jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59797
  496. [X86] Mark the default case of the X86InstrInfo::convertToThreeAddress switch as unreachable. This function should only be called with instructions that are really convertible. And all convertible instructions need to be handled by the switch. So nothing should use the default.
  497. [X86] Check MI.isConvertibleTo3Addr() before calling convertToThreeAddress in X86FixupLEAs. X86FixupLEAs just assumes convertToThreeAddress will return nullptr for any instruction that isn't convertible. But the code in convertToThreeAddress for X86 assumes that any instruction coming in has at least 2 operands and that the second one is a register. But those properties aren't guaranteed of all instructions. We should check the instruction property first.
  498. [TableGen] Properly calculate the minimum size needed or ConvertFn in GenAsmmatcher.inc files We were using the number of Matchables rather than the number of rows in the converter table. This only matters for a few of the targets where the number of matchables is more than 255, but the number of converters is less than 255. Many of the targets have more than 256 converters. So already required a uint16_t.
  499. [x86] add more tests for FP scalarization; NFC
  500. [InstCombine] Added tests for PR41337
  501. [InstCombine] Simplify ctlz/cttz with bitreverse Summary: Fixes PR41273 Reviewers: spatel Reviewed By: spatel Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60096
  502. [AArch64][GlobalISel] Select llvm.aarch64.stlxr(i64, i64*) This adds partial instruction selection support for llvm.aarch64.stlxr. It also factors out selection for G_INTRINSIC_W_SIDE_EFFECTS into its own function. The new function removes the restriction that the intrinsic ID on the G_INTRINSIC_W_SIDE_EFFECTS be on operand 0. Also add a test, and add a GISel line to arm64-ldxr-stxr.ll. Differential Revision: https://reviews.llvm.org/D60100
  503. [FileCheck] Fix FileCheck.cpp compilation on Solaris Both LLVM 8.0.0 and current trunk fail to compile on Solaris with GCC 8.1.0: /vol/llvm/src/llvm/dist/utils/FileCheck/FileCheck.cpp: In function ‘void DumpAnnotatedInput(llvm::raw_ostream&, const llvm::FileCheckRequest&, llvm::StringRef, std::vector<InputAnnotation>&, unsigned int)’: /vol/llvm/src/llvm/dist/utils/FileCheck/FileCheck.cpp:408:41: error: call of overloaded ‘log10(unsigned int&)’ is ambiguous unsigned LineNoWidth = log10(LineCount) + 1; ^ In file included from /vol/gcc-8/lib/gcc/i386-pc-solaris2.11/8.1.0/include-fixed/math.h:24, from /vol/gcc-8/include/c++/8.1.0/cmath:45, from /vol/llvm/src/llvm/dist/include/llvm-c/DataTypes.h:28, from /vol/llvm/src/llvm/dist/include/llvm/Support/DataTypes.h:16, from /vol/llvm/src/llvm/dist/include/llvm/ADT/Hashing.h:47, from /vol/llvm/src/llvm/dist/include/llvm/ADT/ArrayRef.h:12, from /vol/llvm/src/llvm/dist/include/llvm/Support/CommandLine.h:22, from /vol/llvm/src/llvm/dist/utils/FileCheck/FileCheck.cpp:18: /vol/gcc-8/lib/gcc/i386-pc-solaris2.11/8.1.0/include-fixed/iso/math_iso.h:209:21: note: candidate: ‘long double std::log10(long double)’ inline long double log10(long double __X) { return __log10l(__X); } ^~~~~ /vol/gcc-8/lib/gcc/i386-pc-solaris2.11/8.1.0/include-fixed/iso/math_iso.h:170:15: note: candidate: ‘float std::log10(float)’ inline float log10(float __X) { return __log10f(__X); } ^~~~~ /vol/gcc-8/lib/gcc/i386-pc-solaris2.11/8.1.0/include-fixed/iso/math_iso.h:70:15: note: candidate: ‘double std::log10(double)’ extern double log10 __P((double)); ^~~~~ Fixed by using std::log10 instead, which allowed the compilation on i386-pc-solaris2.11 and sparc-sun-solaris2.11 to continue. Differential Revision: https://reviews.llvm.org/D60043
  504. [InstCombine] Added tests for PR41273
  505. [Remarks][NFCI] Remove useless include Remarks.h only uses LLVMBool, which comes from llvm-c/Types.h. Nothing from llvm-c/Core.h is used.
  506. [ArgPromotion] Set debug location at updated callsites Set the correct debug location on instructions which load arguments in preparation for a call to an arg-promoted function. This prevents location cascade from misattributing the line/scope of one of these loads to the location of the instruction preceding the call. Differential Revision: https://reviews.llvm.org/D60113
  507. [DebugInfo] Fix pr41180 : Loop Vectorization Debugify Failure Bug: https://bugs.llvm.org/show_bug.cgi?id=41180 In the bug test case the debug location was missing for the cmp instruction in the "middle block" BB. This patch fixes the bug by copying the debug location from the cmp of the scalar loop's terminator branch, if it exists. The patch also fixes the debug location on the subsequent branch instruction. It was previously using the location of the of the original loop's pre-header block terminator. Both of these instructions will now map to the source line of the conditional branch in the original loop. A regression test has been added that covers these issues. Patch by Orlando Cazalet-Hyams! Differential Revision: https://reviews.llvm.org/D59944
  508. [DAGCombiner] reduce code duplication; NFC
  509. [X86] Allow FixupLEAs to form INC/DEC under OptSize not just MinSize This matches our usual INC/DEC heuristic used during isel.
  510. [PowerPC] Fix reversed bit issue in DCMX mask for "xvtstdcdp" and "xvtstdcsp" P9 implementation Did experiments on power 9 machine, checked the outputs for NaN & Infinity+ cases with corresponding DCMX bit set. Confirmed the DCMX mask bit for NaN and infinity+ are reversed. This patch fixes the issue. Patch by Victor Huang. Differential Revision: https://reviews.llvm.org/D59384
  511. [WideableCond] Fix a nasty bug in detection of "explicit guards" The code was failing to actually check for the presence of the call to widenable_condition. The whole point of specifying the widenable_condition intrinsic was allowing widening transforms. A normal branch is not widenable. A normal branch leading to a deopt is not widenable (in general). I added a test case via LoopPredication, but GuardWidening has an analogous bug. Those are the only two passes actually using this utility just yet. Noticed while working on LoopPredication for non-widenable branches; POC in D60111.
  512. [llvm-objcopy] Change SHT_NOBITS to SHT_PROBITS for some --set-section-flags Summary: Some flags accepted by --set-section-flags and --rename-section can change a SHT_NOBITS section to a SHT_PROGBITS section. Note that none of them can change a SHT_PROGBITS to SHT_NOBITS. The full list (found via experimentation of individually setting each flag) that does this is: contents, load, noload, code, data, rom, and debug. This was found by testing llvm-objcopy with the gnu binutils test suite, specifically this test case: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob;f=binutils/testsuite/binutils-all/copy-1.d;h=f2b0d9e90df738c2891b4d5c7b62f62894b556ca;hb=HEAD Reviewers: jhenderson, grimar, jakehehrlich, alexshap, espindola Reviewed By: jhenderson Subscribers: emaste, arichardson, MaskRay, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59958
  513. [SLP] reorderInputsAccordingToOpcode is const method. NFCI.
  514. [BPF] Replace fstream and sstream with line_iterator Summary: This makes libLLVMBPFCodeGen.so 1128 bytes smaller for my build. Reviewers: yonghong-song Reviewed By: yonghong-song Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60117
  515. [llvm-shlib] Fix cross-compilation for LLVM-C When we're cross-compiling, build and use a native llvm-nm instead of attempting to use the one from the target's build tree. A nice follow-up would be to add a cache variable to allow specifying a path to an external native llvm-nm instead of building one ourselves, similar to LLVM_TABLEGEN and LLVM_CONFIG_PATH. Differential Revision: https://reviews.llvm.org/D60025
  516. [cmake] Add function for building native tool Instead of duplicating functionality for building native versions of tblgen and llvm-config, add a function to set up a native tool build. This will also be used for llvm-nm in a follow-up. This should be NFC for tblgen, besides the slightly different COMMENT for the custom command (it'll display the tablegen target name instead of always saying TableGen). For the native llvm-config, it's a behavior change in that we'll use llvm_ExternalProject_BuildCmd instead of constructing the build command manually, always build in Release, and reference the correct binary path for multi-config generators. I believe all of these changes to be bug fixes. Differential Revision: https://reviews.llvm.org/D60024
  517. [SimplifyCFG] Don't split musttail call from ret Summary: When inserting an `unreachable` after a noreturn call, we must ensure that it's not a musttail call to avoid breaking the IR invariants for musttail calls. Reviewers: fedor.sergeev, majnemer Reviewed By: majnemer Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60080
  518. [SampleProfile] Repeat indirect call promotion only when the target is actually hot. Summary: It is possible that multiple indirect call targets have been promoted for a single callsite from the profiled binary. Current implementation repeats promotion for all these targets as far as the callsite itself is hot (the callsite is assumed to be hot if any one of these targets was "hot" during the profiling). However, even when one of the ICPed target is hot other targets may not, and we should not repeat promotion for "cold" targets. Reviewers: danielcdh, wmi Subscribers: hiraditya, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59940
  519. [PruneEH] Don't split musttail call from ret Summary: When inserting an `unreachable` after a noreturn call, we must ensure that it's not a musttail call to avoid breaking the IR invariants for musttail calls. Reviewers: fedor.sergeev, majnemer Reviewed By: majnemer Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60079
  520. [SystemZ] Improve instruction selection of 64 bit shifts and rotates. For shift and rotate instructions that only use the last 6 bits of the shift amount, a shift amount of (x*64-s) can be substituted with (-s). This saves one instruction and a register: lhi %r1, 64 sr %r1, %r3 sllg %r2, %r2, 0(%r1) => lcr %r1, %r3 sllg %r2, %r2, 0(%r1) Review: Ulrich Weigand
  521. [Transforms] Redundant getValueOperand (NFC) `StoreInst::getValueOperand` is identical to `getOperand(0)`, so the call to `getOperand(0)` can be replaced. Further, `SI->getValueOperand` is redundantly called just a few lines down, despite its return value being stored in variable `DV`. No functional change.
  522. gn build: Merge r357469
  523. gn build: Add build files for non-framework xpc clangd bits Differential Revision: https://reviews.llvm.org/D60124
  524. [llvm-objcopy]Allow llvm-objcopy to be used on an ELF file with no section headers This patch fixes https://bugs.llvm.org/show_bug.cgi?id=41293 and https://bugs.llvm.org/show_bug.cgi?id=41045. llvm-objcopy assumed that it could always read a section header string table. This isn't the case when the sections were previously all stripped, and the e_shstrndx field was set to 0. This patch fixes this. It also fixes a double space in an error message relating to this issue, and prevents llvm-objcopy from adding extra space for non-existent section headers, meaning that --strip-sections on the output of a previous --strip-sections run produces identical output, simplifying the test. Reviewed by: rupprecht, grimar Differential Revision: https://reviews.llvm.org/D59989
  525. [mips] Remove the override of the `isMachineVerifierClean()` All issues found by machine verifier in MIPS target have been fixed.
  526. [mips] Use AltOrders to prevent using odd FP-registers To disable using of odd floating-point registers (O32 ABI and -mno-odd-spreg command line option) such registers and their super-registers added to the set of reserved registers. In general, it works. But there is at least one problem - in case of enabled machine verifier pass some floating-point tests failed because live ranges of register units that are reserved is not empty and verification pass failed with "Live segment doesn't end at a valid instruction" error message. There is D35985 patch which tries to solve the problem by explicit removing of register units. This solution did not get approval. I would like to use another approach for prevent using odd floating point registers - define `AltOrders` and `AltOrderSelect` for MIPS floating point register classes. Such `AltOrders` contains reduced set of registers. At first glance, such solution does not break any test cases and allows enabling machine instruction verification for all MIPS test cases. Differential Revision: http://reviews.llvm.org/D59799
  527. [ObjectYAML] Fix build issue - ObjectYAML depends on Object as minidump support adds additional dependency.
  528. [RISCV] Support assembling @plt symbol operands This patch allows symbols appended with @plt to parse and assemble with the R_RISCV_CALL_PLT relocation. Differential Revision: https://reviews.llvm.org/D55335 Patch by Lewis Revill.
  529. Add minidump support to obj2yaml Summary: This patch adds the code needed to parse a minidump file into the MinidumpYAML model, and the necessary glue code so that obj2yaml can recognise the minidump files and process them. Reviewers: jhenderson, zturner, clayborg Subscribers: mgorny, lldb-commits, amccarth, markmentovai, aprantl, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59634
  530. [X86][AVX] Add test case showing failure to fold broadcast load if its also used as a scalar
  531. Enforce StackID definition in PEI There are various places in LLVM where the definition of StackID is not properly honoured, for example in PEI where objects with a StackID > 0 are allocated on the default stack (StackID0). This patch enforces that PEI only considers allocating objects to StackID 0. Reviewers: arsenm, thegameg, MatzeB Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D60062
  532. [Internalize] Replace uses of std::set with DenseSet This makes it faster and saves 104 bytes for my build.
  533. [Internalize] Replace fstream with line_iterator for -internalize-public-api-file This makes my libLLVMipo.so.9svn smaller by 360 bytes.
  534. SimplifyCFG SinkCommonCodeFromPredecessors: Also sink function calls without used results (PR41259) The code was previously checking that candidates for sinking had exactly one use or were a store instruction (which can't have uses). This meant we could sink call instructions only if they had a use. That limitation seemed a bit arbitrary, so this patch changes it to "instruction has zero or one use" which seems more natural and removes the need to special-case stores. Differential revision: https://reviews.llvm.org/D59936
  535. [LoopPredication] Simplify widenable condition handling [NFC] The code doesn't actually need any of the information about the widenable condition at this level. The only thing we need is to ensure the WC call is the last thing anded in, and even that is a quirk we should really look to remove.
  536. Add an optional list of blocks to avoid when looking for a path in isPotentiallyReachable. The leads to some ambiguous overloads, so update three callers. Differential Revision: https://reviews.llvm.org/D60085
  537. [X86] Add test cases to fixup-lea.ll for optsize and no size optimization. Add +/-slow-incdec command lines We only form inc/dec in FixupLEAs under minsize today, but all other locations in the compiler for inc/dec with optsize.
  538. [X86] Autogenerate complete checks. NFC
  539. [X86] Use unsigned type for opcodes throughout X86FixupLEAs. All of the interfaces related to opcode in MachineInstr and MCInstrInfo refer to opcodes as unsigned.
  540. InstSimplify: Add missing case from r357386
  541. [AMDGPU] Add more test cases of D59608. Summary: - Add more test cases. Reviewers: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60071
  542. AMDGPU: Fix test filename
  543. [ARM] Optimize expressions like "return x != 0;" for Thumb1. There's an existing optimization for x != C, but somehow it was missing a special case for 0. While I'm here, also cleaned up the code/comments a bit: the second value produced by the MERGE_VALUES was actually dead, since a CMOV only produces one result. Differential Revision: https://reviews.llvm.org/D59616
  544. [ARM] Don't try to create "push {r12, lr}" in Thumb1 at -Oz. It's a little tricky to make this issue show up because prologue/epilogue emission normally likes to push at least two registers... but it doesn't when lr is force-spilled due to function length. Not sure if that really makes sense, but I decided not to touch it for now. Differential Revision: https://reviews.llvm.org/D59385
  545. [LoopPred] Rename a variable to simply a future patch [NFC]
  546. [AArch64][GlobalISe] Select STRQui for stores into v264s instead of scalarizing This improves selection for vector stores into v2s64s. Before we just scalarized them, but we can just use a STRQui instead. Differential Revision: https://reviews.llvm.org/D60083
  547. [NFC] Remove dead parameter "FreeInLoop", fix some typos and trailing whitespace. Differential Revision: https://reviews.llvm.org/D60084
  548. Not all blocks are reachable from entry. Don't assume they are. Fixes a bug in isPotentiallyReachable, noticed by inspection.
  549. [X86] Classify the AVX512 rounding control operand as X86::OPERAND_ROUNDING_CONTROL instead of MCOI::OPERAND_IMMEDIATE. Add an assert on legal values of rounding control in the encoder and remove an explicit mask. This should allow llvm-exegesis to intelligently constrain the rounding mode. The mask in the encoder shouldn't be necessary any more. We used to allow codegen to use 8-11 for rounding mode and the assembler would use 0-3 to mean the same thing so we masked here and in the printer. Codegen now matches the assembler and the printer was updated, but I forgot to update the encoder.
  550. [llvm-objcopy] Add --keep-symbols option Differential Revision: https://reviews.llvm.org/D60054
  551. [SLP] getVectorElementSize and isTreeTinyAndNotFullyVectorizable are const methods. NFCI.
  552. [SLP] getGatherCost and isFullyVectorizableTinyTree are const methods. NFCI.
  553. Commit accidentally omitted test case. This test case was approved as part of https://reviews.llvm.org/D49434, but was accidentally omitted from the final commit.
  554. [LoopPred] Be uniform about proving generated conditions We'd been optimizing the case where the predicate was obviously true, do the same for the false case. Mostly just for completeness sake, but also may improve compile time in loops which will exit through the guard. Such loops are presumed rare in fastpath code, but may be present down untaken paths, so optimizing for them is still useful.
  555. [NVPTX] Fix the codegen for llvm.round. Summary: Previously, we translate llvm.round to PTX cvt.rni, which rounds to the even interger when the source is equidistant between two integers. This is not correct as llvm.round should round away from zero. This change replaces llvm.round with a round away from zero implementation through target specific custom lowering. Modify a few affected tests to not check for cvt.rni. Instead, we check for the use of a few constants used in implementing round. We are also adding CUDA runnable tests to check for the values produced by llvm.round to test-suites/External/CUDA. Reviewers: tra Subscribers: jholewinski, sanjoy, jlebar, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59947
  556. [LoopPred] Delete the old condition expressions if unused LoopPredication was replacing the original condition, but leaving the instructions to compute the old conditions around. This would get cleaned up by other passes of course, but we might as well do it eagerly. That also makes the test output less confusing.
  557. [Tests] Autogen all the LoopPredication tests I'm about to make some changes to the pass which cause widespread - but uninteresting - test diffs. Prepare the tests for easy updating.
  558. [Tests] Add tests for a possible loop predication transform variant As highlighted by tests, if one of the operands is loop variant, but guaranteed to have the same value on all iterations, we have a missed oppurtunity.
  559. [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure. This change incorporates an effort by Connor Abbot to change how we deal with WWM operations potentially trashing valid values in inactive lanes. Previously, the SIFixWWMLiveness pass would work out which registers were being trashed within WWM regions, and ensure that the register allocator did not have any values it was depending on resident in those registers if the WWM section would trash them. This worked perfectly well, but would cause sometimes severe register pressure when the WWM section resided before divergent control flow (or at least that is where I mostly observed it). This fix instead runs through the WWM sections and pre allocates some registers for WWM. It then reserves these registers so that the register allocator cannot use them. This results in a significant register saving on some WWM shaders I'm working with (130 -> 104 VGPRs, with just this change!). Differential Revision: https://reviews.llvm.org/D59295
  560. gn build: Merge r357383
  561. [AArch64] Add v8.5-a Memory Tagging STZGM instruction This instruction writes a block of allocation tags and stores zero to the associated data locations. It differs from STGM by 1 bit and has the same arguments. The specification can be found here: https://developer.arm.com/docs/ddi0596/c Differential Revision: https://reviews.llvm.org/D60065
  562. [RISCV] Attach VK_RISCV_CALL to symbols upon creation This patch replaces the addition of VK_RISCV_CALL in RISCVMCCodeEmitter by creating the RISCVMCExpr when tail/call are parsed, or in the codegen case when the callee symbols are created. This required adding a new CallSymbol operand to allow only adding VK_RISCV_CALL to tail/call instructions. This patch will allow further expansion of parsing and codegen to easily include PLT symbols which must generate the R_RISCV_CALL_PLT relocation. Differential Revision: https://reviews.llvm.org/D55560 Patch by Lewis Revill.
  563. [AArch64] Add v8.5-a Memory Tagging STGM/LDGM instructions The STGV/LDGV instructions were replaced with STGM/LDGM. The encodings remain the same but there is no longer writeback so there are no unpredictable encodings to check for. The specfication can be found here: https://developer.arm.com/docs/ddi0596/c Differential Revision: https://reviews.llvm.org/D60064
  564. [RISCV] Generate address sequences suitable for mcmodel=medium This patch adds an implementation of a PC-relative addressing sequence to be used when -mcmodel=medium is specified. With absolute addressing, a 'medium' codemodel may cause addresses to be out of range. This is because while 'medium' implies a 2 GiB addressing range, this 2 GiB can be at any offset as opposed to 'small', which implies the first 2 GiB only. Note that LLVM/Clang currently specifies code models differently to GCC, where small and medium imply the same functionality as GCC's medlow and medany respectively. Differential Revision: https://reviews.llvm.org/D54143 Patch by Lewis Revill.
  565. [AArch64] Add v8.5-a Memory Tagging GMID_EL1 register The latest version of the MTE spec added a system register 'GMID_EL1'. It contains the block size used by the LDGM and STGM instructions and is read only. The specification can be found here: https://developer.arm.com/docs/ddi0596/c
  566. [InstCombine] Handle vector gep with scalar argument in evaluateInDifferentElementOrder Summary: This fixes PR41270. The recursive function evaluateInDifferentElementOrder expects to be called on a vector Value, so when we call it on a vector GEP's arguments, we must first check that the argument is indeed a vector. Reviewers: reames, spatel Reviewed By: spatel Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60058
  567. X86: Fix override warning
  568. Revert "[InstCombine] Handle vector gep with scalar argument in evaluateInDifferentElementOrder" This reverts commit 75216a6dbcfe5fb55039ef06a07e419fa875f4a5. I'll recommit with a better commit message with reference to the phabricator review.
  569. InstSimplify: Add baseline test for upcoming change
  570. [InstCombine] Handle vector gep with scalar argument in evaluateInDifferentElementOrder This fixes PR41270. The recursive function evaluateInDifferentElementOrder expects to be called on a vector Value, so when we call it on a vector GEP's arguments, we must first check that the argument is indeed a vector.
  571. [X86] Make post-ra scheduling macrofusion-aware. Subscribers: MatzeB, arsenm, jvesely, nhaehnle, hiraditya, javed.absar, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59688
  572. [InstCombine] eliminate commuted select-shuffles + binop (PR41304) If we have a commutable vector binop with inverted select-shuffles, we don't care about the order of the operands in each vector lane: LHS = shuffle V1, V2, <0, 5, 6, 3> RHS = shuffle V2, V1, <0, 5, 6, 3> LHS + RHS --> <V1[0]+V2[0], V2[1]+V1[1], V2[2]+V1[2], V1[3]+V2[3]> --> V1 + V2 PR41304: https://bugs.llvm.org/show_bug.cgi?id=41304 ...is currently titled as an SLP enhancement, but at least for the given example, we can reduce that in instcombine because we are just eliminating shuffles. As noted in the TODO, this could be generalized, but I haven't thought through those patterns completely, so this is limited to what appears to be always safe. Differential Revision: https://reviews.llvm.org/D60048
  573. [X86MacroFusion][NFC] Add more tests. In preparation for D59688.
  574. [X86] Fix a test from r357317 Summary: The missing `<` causes the lld command to override the test file, which fails in environments marking the test files as readonly. Reviewers: bkramer Reviewed By: bkramer Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60060
  575. [X86][SSE] Add fcmp constant folding tests Initial test coverage for D60006
  576. [RISCV] Add seto pattern expansion Adds a `seto` pattern expansion. Without it the lowerings of `fcmp one` and `fcmp ord` would be inefficient due to an unoptimized double negation. Differential Revision: https://reviews.llvm.org/D59699
  577. [X86] Use ISD::INTRINSIC_VOID in getTgtMemIntrinsic for truncating stores and scatter intrinsics. This is the appropriate opcode for only having a chain output. Though I'm not sure it matters much.
  578. [RISCV] Don't evaluatePCRelLo if a relocation will be forced (e.g. due to linker relaxation) A pcrel_lo will point to the associated pcrel_hi fixup which in turn points to the real target. RISCVMCExpr::evaluatePCRelLo will work around this indirection in order to allow the fixup to be evaluate properly. However, if relocations are forced (e.g. due to linker relaxation is enabled) then its evaluation is undesired and will result in a relocation with the wrong target. This patch modifies evaluatePCRelLo so it will not try to evaluate if the fixup will be forced as a relocation. A new helper method is added to RISCVAsmBackend to query this. Differential Revision: https://reviews.llvm.org/D59686
  579. gn build: Add build files for most clang-tools-extra unit tests Differential Revision: https://reviews.llvm.org/D60038
  580. [InstCombine] add tests for inverted select-shuffles + binop (PR41304); NFC
  581. [x86] allow movmsk with 2-element reductions One motivation for making this change is that the lack of using movmsk is likely a main source of perf difference between clang and gcc on the C-Ray benchmark as shown here: https://www.phoronix.com/scan.php?page=article&item=gcc-clang-2019&num=5 ...but this change alone isn't enough to solve that problem. The 'all-of' examples show what is likely the worst case trade-off: we end up with an extra instruction (or 2 if we count the 'xor' register clearing). The 'any-of' examples look clearly better using movmsk because we've traded 2 vector instructions for 2 scalar instructions, and movmsk may have better timing than the generic 'movq'. If we examine the llvm-mca output for these cases, it appears that even though the 'all-of' movmsk variant looks worse on paper, it would perform better on both Haswell and Jaguar. $ llvm-mca -mcpu=haswell no_movmsk.s -timeline Iterations: 100 Instructions: 400 Total Cycles: 504 Total uOps: 400 Dispatch Width: 4 uOps Per Cycle: 0.79 IPC: 0.79 Block RThroughput: 1.0 $ llvm-mca -mcpu=haswell movmsk.s -timeline Iterations: 100 Instructions: 600 Total Cycles: 358 Total uOps: 600 Dispatch Width: 4 uOps Per Cycle: 1.68 IPC: 1.68 Block RThroughput: 1.5 $ llvm-mca -mcpu=btver2 no_movmsk.s -timeline Iterations: 100 Instructions: 400 Total Cycles: 407 Total uOps: 400 Dispatch Width: 2 uOps Per Cycle: 0.98 IPC: 0.98 Block RThroughput: 2.0 $ llvm-mca -mcpu=btver2 movmsk.s -timeline Iterations: 100 Instructions: 600 Total Cycles: 311 Total uOps: 600 Dispatch Width: 2 uOps Per Cycle: 1.93 IPC: 1.93 Block RThroughput: 3.0 Finally, there may be CPUs where movmsk is horribly slow (old AMD small cores?), but if that's true, then we're also almost certainly making the wrong transform already for reductions with >2 elements, so that should be fixed independently. Differential Revision: https://reviews.llvm.org/D59997
  582. [InstCombine] canonicalize select shuffles by commuting In PR41304: https://bugs.llvm.org/show_bug.cgi?id=41304 ...we have a case where we want to fold a binop of select-shuffle (blended) values. Rather than try to match commuted variants of the pattern, we can canonicalize the shuffles and check for mask equality with commuted operands. We don't produce arbitrary shuffle masks in instcombine, but select-shuffles are a special case that the backend is required to handle because we already canonicalize vector select to this shuffle form. So there should be no codegen difference from this change. It's possible that this improves CSE in IR though. Differential Revision: https://reviews.llvm.org/D60016
  583. fix typo: "\t" => " " Reviewers: llvm.org, Jim Reviewed By: Jim Subscribers: arsenm, jvesely, nhaehnle, rupprecht, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59983
  584. SafepointIRVerifier port to new Pass Manager Straightforward port of StatepointIRVerifier pass to new Pass Manager framework. Fix By: skatkov Reviewed By: fedor.sergeev Differential Revision: https://reviews.llvm.org/D59825 This is a re-land of r357147/r357148 with LLVM_ENABLE_MODULES build fixed. Adding IR/SafepointIRVerifier.h into its own module.
  585. [NFC][InstCombine] Add tests for combining icmp of no-wrap sub w/ constant.
  586. gn build: Merge r357340
  587. gn build: Merge r357326
  588. [SystemZ] Remove fcmp undef from reduced test Pre-commit for D60006 (Add fcmp UNDEF handling to SelectionDAG::FoldSetCC) Approved by @uweigand (Ulrich Weigand)
  589. [MIPS] Remove fcmp undef from reduced test Pre-commit for D60006 (Add fcmp UNDEF handling to SelectionDAG::FoldSetCC) Approved by @atanasyan (Simon Atanasyan)
  590. [X86] Teach isel for RMW binops to handle negate Negate updates flags like a subtract. We should be able to use the flags from the RMW form of negate when we have (store (X86ISD::SUB 0, load A), A) Differential Revision: https://reviews.llvm.org/D60007
  591. [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs This patch adds support for the RISC-V hard float ABIs, building on top of rL355771, which added basic target-abi parsing and MC layer support. It also builds on some re-organisations and expansion of the upstream ABI and calling convention tests which were recently committed directly upstream. A number of aspects of the RISC-V float hard float ABIs require frontend support (e.g. flattening of structs and passing int+fp for fp+fp structs in a pair of registers), and will be addressed in a Clang patch. As can be seen from the tests, it would be worthwhile extending RISCVMergeBaseOffsets to handle constant pool as well as global accesses. Differential Revision: https://reviews.llvm.org/D59357
  592. [X86][SSE] detectAVGPattern - Match zext(or(x,y)) 'add like' patterns (PR41316) Fixes PR41316 where the expanded PAVG intrinsic had had one of its ADDs turned into an OR due to its operands having no conflicting bits.
  593. [RISCV] Add RV64 CHECK lines to test/CodeGen/RISCV/vararg.ll and prepare for hard float tests vararg.ll previously missed RV64 tests. This patch also prepares for using vararg.ll to test handling of varargs for the ilp32f/ilp32d/lp64f/lp64d hard float ABIs. In these ABIs, varargs are passed as in either the ilp32 or lp64 ABI. Due to some slight codegen differences, different check lines are needed for when RV32D is enabled.
  594. [X86][SSE] detectAVGPattern - begin generalizing ADD matches Move the ADD matching into a helper - first NFC stage towards supporting 'ADD like' cases such as in PR41316
  595. [cmake] Change deprecated $<CONFIG> to $<CONFIGURATION>. NFC See rL357338 for a similar change. The informational expression $<CONFIGURATION> has been deprecated since CMake 3.0
  596. [llvm-objcopy] Replace the size() helper with SectionTableRef::size Summary: BTW, STLExtras.h provides llvm::size() which is similar to std::size() for random access iterators. However, if we prefer qualified llvm::size(), the member function .size() will be more convenient. Reviewers: jhenderson, jakehehrlich, rupprecht, grimar, alexshap, espindola Reviewed By: grimar Subscribers: emaste, arichardson, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60028
  597. [X86][SSE] Add PAVG test case from PR41316
  598. [WebAssembly] Fix unwind destination mismatches in CFG stackify Summary: Linearing the control flow by placing `try`/`end_try` markers can create mismatches in unwind destinations. This patch resolves these mismatches by wrapping those instructions with an incorrect unwind destination with a nested `try`/`catch`/`end_try` and branching to the right destination within the new catch block. Reviewers: dschuff Subscribers: sunfish, sbc100, jgravelle-google, chrib, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D48345
  599. [WebAssembly] Run ExplicitLocals pass after CFGStackify Summary: While this does not change any final output, this will greatly simplify ixing unwind destination mismatches in CFGStackify (D48345), because we have to create some new registers there. Reviewers: dschuff Subscribers: sunfish, sbc100, jgravelle-google, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59652
  600. [RISCV] Add DAGCombine for (SplitF64 (ConstantFP x)) The SplitF64 node is used on RV32D to convert an f64 directly to a pair of i32 (necessary as bitcasting to i64 isn't legal). When performed on a ConstantFP, this will result in a FP load from the constant pool followed by a store to the stack and two integer loads from the stack (necessary as there is no way to directly move between f64 FPRs and i32 GPRs on RV32D). It's always cheaper to just materialise integers for the lo and hi parts of the FP constant, so do that instead.
  601. Adds `-ftime-trace` option to clang that produces Chrome `chrome://tracing` compatible JSON profiling output dumps. This change adds hierarchical "time trace" profiling blocks that can be visualized in Chrome, in a "flame chart" style. Each profiling block can have a "detail" string that for example indicates the file being processed, template name being instantiated, function being optimized etc. This is taken from GitHub PR: https://github.com/aras-p/llvm-project-20170507/pull/2 Patch by Aras Pranckevičius. Differential Revision: https://reviews.llvm.org/D58675
  602. [RISCV][NFC] Remove floating point operations from test/CodeGen/RISCV/vararg.ll This minimises differences in output when compiling with hardware floating point support, which will be done in a future patch (to demonstrate the same vararg calling convention is used).
  603. [cmake] Remove use of deprecated generator expression. NFC Use $<CONFIG> instead of $<CONFIGURATION>, since the latter has been deprecated since CMake 3.0, and the former is entirely equivalent.
  604. [WebAssembly] Optimize the number of routing blocks in FixIrreducibleCFG Summary: Currently we create a routing block to the dispatch block for every predecessor of every entry. So the total number of routing blocks created will be (# of preds) * (# of entries). But we don't need to do this: we need at most 2 routing blocks per loop entry, one for when the predecessor is inside the loop and one for it is outside the loop. (We can't merge these into one because this will creates another loop cycle between blocks inside and blocks outside) This patch fixes this and creates at most 2 routing blocks per entry. This also renames variable `Split` to `Routing`, which I think is a bit clearer. Reviewers: kripken Subscribers: sunfish, dschuff, sbc100, jgravelle-google, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59462
  605. [Support] Implement is_local_impl with AIX mntctl Summary: On AIX, we can determine whether a filesystem is remote using `mntctl`. If the information is not found, then claim that the file is remote (since that is the more restrictive case). Testing for the associated interface is restored with a modified version of the unit test from rL295768. Reviewers: jasonliu, xingxue Reviewed By: xingxue Subscribers: jsji, apaprocki, Hahnfeld, zturner, krytarowski, kristina, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58801
  606. [LoopPredication] Remove stale TODO
  607. [LoopPredication] Use the builder's insertion point everywhere [NFC]
  608. [MemorySSA] Temporary fix assert when reaching 0 limit.
  609. Try to fix buildbot error Error is: llvm/lib/Analysis/ScalarEvolution.cpp:3534:10: error: chosen constructor is explicit in copy-initialization return {UniqueSCEVs.FindNodeOrInsertPos(ID, IP), std::move(ID), IP}; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ /usr/bin/../lib/gcc/aarch64-linux-gnu/5.4.0/../../../../include/c++/5.4.0/tuple:479:19: note: explicit constructor declared here constexpr tuple(_UElements&&... __elements) ^ 1 error generated.
  610. [WebAssembly] Add mutable globals feature Summary: This feature is not actually used for anything in the WebAssembly backend, but adding it allows users to get it into the target features sections of their objects, which makes these objects future-compatible. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jdoerfert, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D60013
  611. [SCEV] Check the cache in get{S|U}MaxExpr before doing any work Summary: This lets us avoid e.g. checking if A >=s B in getSMaxExpr(A, B) if we've already established that (A smax B) is the best we can do. Fixes PR41225. Reviewers: asbirlea Subscribers: mcrosier, jlebar, bixia, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60010
  612. [MemorySSA] Limit clobber walks. Summary: This patch limits all getClobberingMemoryAccess() walks to MaxCheckLimit. Reviewers: george.burgess.iv Subscribers: sanjoy, jlebar, Prazek, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59569
  613. [GlobalISel][AArch64] Add isel support for G_INSERT_VECTOR_ELT on v2s32s This adds support for v2s32 vector inserts, and updates the selection + regbankselect tests for G_INSERT_VECTOR_ELT. Differential Revision: https://reviews.llvm.org/D59910
  614. [X86] When using Win64 ABI, exit with error if SSE is disabled for varargs We need XMM registers to handle varargs with the Win64 ABI. Before we would silently generate bad code resulting in an assertion failure elsewhere in the backend.
  615. [MemorySSA] Don't optimize incomplete phis. Summary: MemoryPhis cannot be optimized out until they are complete. Resolves PR41254. Reviewers: george.burgess.iv Subscribers: sanjoy, jlebar, Prazek, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59966
  616. [DAGCombiner] Rewrite ImproveLifetimeNodeChain to avoid DAG loop. Avoid EXPENSIVE_CHECK failure. NFCI.
  617. [WebAssembly] Handle END_LOOP in unreachable BB in CFGStackify Summary: This fixes crashes when a BB in which an END_LOOP is to be placed is unreachable and does not have any predecessors. Fixes PR41307. Reviewers: dschuff Subscribers: yurydelendik, sbc100, jgravelle-google, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60004
  618. AMDGPU: Remove dx10-clamp from subtarget features Since this can be set with s_setreg*, it should not be a subtarget property. Set a default based on the calling convention, and Introduce a new amdgpu-dx10-clamp attribute to override this if desired. Also introduce a new amdgpu-ieee attribute to match. The values need to match to allow inlining. I think it is OK for the caller's dx10-clamp attribute to override the callee, but there doesn't appear to be the infrastructure to do this currently without definining the attribute in the generic Attributes.td. Eventually the calling convention lowering will need to insert a mode switch somewhere for these.
  619. [Hexagon] Remove fcmp undef from reduced tests Pre-commit for D60006 (Add fcmp UNDEF handling to SelectionDAG::FoldSetCC) Approved by @kparzysz (Krzysztof Parzyszek)
  620. [X86] Add test cases showing failure to use RMW form of negate when only flags are used. NFC
  621. [DAG] Avoid redundancy in StoreMerge TokenFactor generation. Avoid generating redundant TokenFactor when all merged stores have the same chain.
  622. [X86] Use cached OptForSize in X86ISelDAGToDAG.cpp instead of pulling it from the function attribute. NFCI
  623. [SystemZ] Regenerate double constant comparison test Prep work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC)
  624. [MIPS] Regenerate double constant comparison test Prep work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC)
  625. [ARM] Regenerate execute-only float comparison tests Prep work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC)
  626. [InstCombine] autogenerate complete checks; NFC
  627. [AMDGPU] Add an additional Code Object V3 assembler example Document the intended use of the `.amdgcn.next_free_{s,v}gpr` in the context of multiple kernels and functions. Differential Revision: https://reviews.llvm.org/D59949
  628. [InstCombine] regenerate test checks; NFC
  629. [AArch64] Regenerate half precision tests Prep work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC)
  630. [llvm][NFC] Factor out logic for getting incoming & back Loop edges Reviewers: davidxl Reviewed By: davidxl Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59967
  631. [DAGCombine] Prune unnused nodes. Summary: Nodes that have no uses are eventually pruned when they are selected from the worklist. Record nodes newly added to the worklist or DAG and perform pruning after every combine attempt. Reviewers: efriedma, RKSimon, craig.topper, spatel, jyknight Reviewed By: jyknight Subscribers: jdoerfert, jyknight, nemanjai, jvesely, nhaehnle, javed.absar, hiraditya, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58070
  632. [ARM] Regenerate vector comparison tests Prep work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC)
  633. [CodeGen] Refactor the option for the maximum jump table size Refactor the option `max-jump-table-size` to default to the maximum representable number. Essentially, NFC.
  634. [DAG] Set up infrastructure to avoid smart constructor-based dangling nodes Summary: Various SelectionDAG non-combine operations (e.g. the getNode smart constructor and legalization) may leave dangling nodes by applying optimizations without fully pruning unused result values. This results in nodes that are never added to the worklist and therefore can not be pruned. Add a node inserter for the combiner to make sure such nodes have the chance of being pruned. This allows a number of additional peephole optimizations. Reviewers: efriedma, RKSimon, craig.topper, jyknight Reviewed By: jyknight Subscribers: msearles, jyknight, sdardis, nemanjai, javed.absar, hiraditya, jrtc27, atanasyan, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58068
  635. [X86] Fix some tests using fcmp with undef arguments Prep work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC)
  636. [InstCombine] move shuffle canonicalizations before other transforms This may not be NFC, but I'm not sure how to expose any diffs in tests. In theory, it should be slightly more efficient and possibly more profitable to do the canonicalizations (which can increase the undef elements in the mask) ahead of SimplifyDemandedVectorElts().
  637. [llvm-readobj] Add some generic notes (e.g. NT_VERSION) Summary: Support reading notes that don't have a standard note name. Reviewers: MaskRay Reviewed By: MaskRay Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59969
  638. [llvm-readelf] Allow prefix flags for -p and -x Summary: This allows syntax like `llvm-readelf -p.data1 -x.data2`. Reviewers: jhenderson Reviewed By: jhenderson Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59965
  639. [SLP] Add support for commutative icmp/fcmp predicates For the cases where the icmp/fcmp predicate is commutative, use reorderInputsAccordingToOpcode to collect and commute the operands. This requires a helper to recognise commutativity in both general Instruction and CmpInstr types - the CmpInst::isCommutative doesn't overload the Instruction::isCommutative method for reasons I'm not clear on (maybe because its based on predicate not opcode?!?). Differential Revision: https://reviews.llvm.org/D59992
  640. [llvm-objcopy] Fix case style of LayoutSegments. NFC
  641. [mips] Fix lowering a signed immediate for *.d MSA instructions The `lowerMSASplatImm` function zero-extends `i32` immediates while building constant. If target type is `i64`, negative immediate loses the sign. As a result, for example `__builtin_msa_ldi_d(-1)` lowered to series of instruction loads incorrect value 0xffffffff to the `$w0` register instead of single `ldi.d $w0, -1` instruction. The fix zero-extends unsigned immediates and signed-extend signed immediates. Differential Revision: http://reviews.llvm.org/D59884
  642. [NFC][llvm-exegesis] Also promote getSchedClassPoint() into ResolvedSchedClass. Summary: It doesn't need anything from Analysis::SchedClassCluster class, and takes ResolvedSchedClass as param, so this seems rather fitting. Reviewers: courbet, gchatelet Reviewed By: courbet Subscribers: tschuett, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59994
  643. [AMDGPU][MC] Corrected conversion rules for inlinable constants to match rules for literals See bug 40806: https://bugs.llvm.org/show_bug.cgi?id=40806 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D59786
  644. gn build: Merge r357248
  645. gn build: Merge r357259
  646. [NFC][llvm-exegesis] Refactor ResolvedSchedClass & friends Summary: `ResolvedSchedClass` will need to be used outside of `Analysis` (before `InstructionBenchmarkClustering` even), therefore promote it into a non-private top-level class, and while there also move all of the functions that are only called by `ResolvedSchedClass` into that same new file. Reviewers: courbet, gchatelet Reviewed By: courbet Subscribers: mgorny, tschuett, mgrang, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59993
  647. [DAGCombiner] simplify shuffle of shuffle After investigating the examples from D59777 targeting an SSE4.1 machine, it looks like a very different problem due to how we map illegal types (256-bit in these cases). We're missing a shuffle simplification that maps elements of a vector back to a shuffled operand. We have a more general version of this transform in DAGCombiner::visitVECTOR_SHUFFLE(), but that generality means it is limited to patterns with a one-use constraint, and the examples here have 2 uses. We don't need any uses or legality limitations for a simplification (no new value is created). It looks like we miss this pattern in IR too. In one of the zext examples here, we have shuffle masks like this: Shuf0 = vector_shuffle<0,u,3,7,0,u,3,7> Shuf = vector_shuffle<4,u,6,7,u,u,u,u> ...so that's moving the high half of the 1st vector into the low half. But the high half of the 1st vector is already identical to the low half. Differential Revision: https://reviews.llvm.org/D59961
  648. Recommit "[DSE] Preserve basic block ordering using OrderedBasicBlock." Updated to use DenseMap::insert instead of [] operator for insertion, to avoid a crash caused by epoch checks. This reverts commit 2b85de438326f9d27bc96dc934ec98b98abdb337.
  649. [DAGCombine] Improve Lifetime node chains. Improve both start and end lifetime nodes chain dependencies. Reviewers: courbet Reviewed By: courbet Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59795
  650. [DAGCombiner] fold sext into decrement This is a sibling to rL357178 that I noticed we'd hit if we chose an alternate transform in D59818. %z = zext i8 %x to i32 %dec = add i32 %z, -1 %r = sext i32 %dec to i64 => %z2 = zext i8 %x to i64 %r = add i64 %z2, -1 https://rise4fun.com/Alive/kPP The x86 vector diffs show a slight regression, so there's a chance that we should limit this and the previous transform to scalars. But given that we allowed vectors before, I'm matching that behavior here. We should change both transforms together if that's the right thing to do.
  651. Switch lowering: exploit unreachable fall-through when lowering case range cluster In the example below, we would previously emit two range checks, one for cases 1--3 and one for 4--6. This patch makes us exploit the fact that the fall-through is unreachable and only one range check is necessary. switch i32 %i, label %default [ i32 1, label %bb1 i32 2, label %bb1 i32 3, label %bb1 i32 4, label %bb2 i32 5, label %bb2 i32 6, label %bb2 ] default: unreachable
  652. [x86] add tests for decrement+sext; NFC
  653. [AMDGPU][MC] Corrected handling of tied src for atomic return MUBUF opcodes See bug 40917: https://bugs.llvm.org/show_bug.cgi?id=40917 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D59878
  654. [MCA] Add an experimental MicroOpQueue stage. This patch adds an experimental stage named MicroOpQueueStage. MicroOpQueueStage can be used to simulate a hardware micro-op queue (basically, a decoupling queue between 'decode' and 'dispatch'). Users can specify a queue size, as well as a optional MaxIPC (which - in the absence of a "Decoders" stage - can be used to simulate a different throughput from the decoders). This stage is added to the default pipeline between the EntryStage and the DispatchStage only if PipelineOption::MicroOpQueue is different than zero. By default, llvm-mca sets PipelineOption::MicroOpQueue to the value of hidden flag -micro-op-queue-size. Throughput from the decoder can be simulated via another hidden flag named -decoder-throughput. That flag allows us to quickly experiment with different frontend throughputs. For targets that declare a loop buffer, flag -decoder-throughput allows users to do multiple runs, each time simulating a different throughput from the decoders. This stage can/will be extended in future. For example, we could add a "buffer full" event to notify bottlenecks caused by backpressure. flag -decoder-throughput would probably go away if in future we delegate to another stage (DecoderStage?) the simulation of a (potentially variable) throughput from the decoders. For now, flag -decoder-throughput is "good enough" to run some simple experiments. Differential Revision: https://reviews.llvm.org/D59928
  655. AMDGPU: Make sram-ecc off by default for Vega20 Differential Revision: https://reviews.llvm.org/D59718
  656. [llvm-readelf]Merge dynamic and static relocation printing to avoid code duplication The majority of the printRelocation and printDynamicRelocation functions were identical. This patch factors this all out into a new function. There are a couple of minor differences to do with printing of symbols without names, but I think these are harmless, and in some cases a small improvement. Reviewed by: grimar, rupprecht, Higuoxing Differential Revision: https://reviews.llvm.org/D59823
  657. [NFC][llvm-exegesis] Refactor Analysis::SchedClassCluster::measurementsMatch() Summary: The diff looks scary but it really isn't: 1. I moved the check for the number of measurements into `SchedClassClusterCentroid::validate()` 2. While there, added a check that we can only have a single inverse throughput measurement. I missed that when adding it initially. 3. In `Analysis::SchedClassCluster::measurementsMatch()` is called with the current LLVM values from schedule class and the values from Centroid. 3.1. The values from centroid we can already get from `SchedClassClusterCentroid::getAsPoint()`. This isn't 100% a NFC, because previously for inverse throughput we used `min()`. I have asked whether i have done that correctly in https://reviews.llvm.org/D57647?id=184939#inline-510384 but did not hear back. I think `avg()` should be used too, thus it is a fix. 3.2. Finally, refactor the computation of the LLVM-specified values into `Analysis::SchedClassCluster::getSchedClassPoint()` I will need that function for [[ https://bugs.llvm.org/show_bug.cgi?id=41275 | PR41275 ]] Reviewers: courbet, gchatelet Reviewed By: courbet Subscribers: tschuett, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59951
  658. [X86] Add X86TargetLowering::isCommutativeBinOp override. We currently just have test coverage for PMULUDQ - will add more in the future.
  659. [SLP] Add support for swapping icmp/fcmp predicates to permit vectorization We should be able to match elements with the swapped predicate as well - as long as we commute the source operands. Differential Revision: https://reviews.llvm.org/D59956
  660. [PowerPC] Add the support for __builtin_setrnd() Summary: PowerPC64/PowerPC64le supports the builtin function __builtin_setrnd to set the floating point rounding mode. This function will use the least significant two bits of integer argument to set the floating point rounding mode. double __builtin_setrnd(int mode); The effective values for mode are: 0 - round to nearest 1 - round to zero 2 - round to +infinity 3 - round to -infinity Note that the mode argument will modulo 4, so if the int argument is greater than 3, it will only use the least significant two bits of the mode. Namely, builtin_setrnd(102)) is equal to builtin_setrnd(2). Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D59405
  661. [ScheduleDAG] Move `Topo` and `addEdge` to base class. Some DAG mutations can only be applied to `ScheduleDAGMI`, and have to internally cast a `ScheduleDAGInstrs` to `ScheduleDAGMI`. There is nothing actually specific to `ScheduleDAGMI` in `Topo`.
  662. [llvm-objcopy] Delete two redundant reinterpret_cast. NFC
  663. Test commit. Fix typo.
  664. AMDGPU/GlobalISel: Insert waterfall loop for vector indexing The register index can only really be an SGPR. Lie that a VGPR index is legal, and then rewrite the instruction in a waterfall loop to handle the index.
  665. [PowerPC] Strength reduction of multiply by a constant by shift and add/sub in place A shift and add/sub sequence combination is faster in place of a multiply by constant. Because the cycle or latency of multiply is not huge, we only consider such following worthy patterns. ``` (mul x, 2^N + 1) => (add (shl x, N), x) (mul x, -(2^N + 1)) => -(add (shl x, N), x) (mul x, 2^N - 1) => (sub (shl x, N), x) (mul x, -(2^N - 1)) => (sub x, (shl x, N)) ``` And the cycles or latency is subtarget-dependent so that we need consider the subtarget to determine to do or not do such transformation. Also data type is considered for different cycles or latency to do multiply. Differential Revision: https://reviews.llvm.org/D58950
  666. gn build: Add check-clang-tools to run clang-tools-extra lit tests Only runs the clang-tools-extra lit tests; not yet the unit tests. Add a build file for clangd-indexer too, since it's needed for the tests. Differential Revision: https://reviews.llvm.org/D59955
  667. [llvm-readobj] Change variable names to match LLVM-style. NFC. Summary: This patch helps change variable names to match LLVM-style Reviewers: jhenderson, Higuoxing Reviewed By: Higuoxing Subscribers: rupprecht, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59931
  668. Revert Recommit "[DSE] Preserve basic block ordering using OrderedBasicBlock." Another buildbot failure http://lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/20402 clang-9: /home/ssglocal/clang-cmake-x86_64-sde-avx512-linux/clang-cmake-x86_64-sde-avx512-linux/llvm/include/llvm/ADT/DenseMap.h:1228: llvm::DenseMapIterator<KeyT, ValueT, KeyInfoT, Bucket, IsConst>::value_type* llvm::DenseMapIterator<KeyT, ValueT, KeyInfoT, Bucket, IsConst>::operator->() const [with KeyT = const llvm::Instruction*; ValueT = unsigned int; KeyInfoT = llvm::DenseMapInfo<const llvm::Instruction*>; Bucket = llvm::detail::DenseMapPair<const llvm::Instruction*, unsigned int>; bool IsConst = false; llvm::DenseMapIterator<KeyT, ValueT, KeyInfoT, Bucket, IsConst>::pointer = llvm::detail::DenseMapPair<const llvm::Instruction*, unsigned int>*; llvm::DenseMapIterator<KeyT, ValueT, KeyInfoT, Bucket, IsConst>::value_type = llvm::detail::DenseMapPair<const llvm::Instruction*, unsigned int>]: Assertion `isHandleInSync() && "invalid iterator access!"' failed. 0. Program arguments: /home/ssglocal/clang-cmake-x86_64-sde-avx512-linux/clang-cmake-x86_64-sde-avx512-linux/stage1.install/bin/clang-9 -cc1 -triple x86_64-unknown-linux-gnu -emit-obj -disable-free -main-file-name ArchiveCommandLine.cpp -mrelocation-model static -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu skylake-avx512 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -coverage-notes-file /home/ssglocal/clang-cmake-x86_64-sde-avx512-linux/clang-cmake-x86_64-sde-avx512-linux/test/sandbox/build/MultiSource/Benchmarks/7zip/Output/ArchiveCommandLine.llvm.gcno -resource-dir /home/ssglocal/clang-cmake-x86_64-sde-avx512-linux/clang-cmake-x86_64-sde-avx512-linux/stage1.install/lib/clang/9.0.0 -I /home/ssglocal/clang-cmake-x86_64-sde-avx512-linux/clang-cmake-x86_64-sde-avx512-linux/test/sandbox/build/MultiSource/Benchmarks/7zip -I /home/ssglocal/clang-cmake-x86_64-sde-avx512-linux/clang-cmake-x86_64-sde-avx512-linux/test/test-suite/MultiSource/Benchmarks/7zip -I /home/ssglocal/clang-cmake-x86_64-sde-avx512-linux/clang-cmake-x86_64-sde-avx512-linux/test/test-suite/include -I ../../../include -D _GNU_SOURCE -D __STDC_LIMIT_MACROS -D NDEBUG -D BREAK_HANDLER -D UNICODE -D _UNICODE -I /home/ssglocal/clang-cmake-x86_64-sde-avx512-linux/clang-cmake-x86_64-sde-avx512-linux/test/test-suite/MultiSource/Benchmarks/7zip/C -I /home/ssglocal/clang-cmake-x86_64-sde-avx512-linux/clang-cmake-x86_64-sde-avx512-linux/test/test-suite/MultiSource/Benchmarks/7zip/CPP/myWindows -I /home/ssglocal/clang-cmake-x86_64-sde-avx512-linux/clang-cmake-x86_64-sde-avx512-linux/test/test-suite/MultiSource/Benchmarks/7zip/CPP/include_windows -I /home/ssglocal/clang-cmake-x86_64-sde-avx512-linux/clang-cmake-x86_64-sde-avx512-linux/test/test-suite/MultiSource/Benchmarks/7zip/CPP -I . -D _FILE_OFFSET_BITS=64 -D _LARGEFILE_SOURCE -D NDEBUG -D _REENTRANT -D ENV_UNIX -D _7ZIP_LARGE_PAGES -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/5.4.0/../../../../include/c++/5.4.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/5.4.0/../../../../include/x86_64-linux-gnu/c++/5.4.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/5.4.0/../../../../include/x86_64-linux-gnu/c++/5.4.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/5.4.0/../../../../include/c++/5.4.0/backward -internal-isystem /usr/local/include -internal-isystem /home/ssglocal/clang-cmake-x86_64-sde-avx512-linux/clang-cmake-x86_64-sde-avx512-linux/stage1.install/lib/clang/9.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O3 -std=gnu++98 -fdeprecated-macro -fdebug-compilation-dir /home/ssglocal/clang-cmake-x86_64-sde-avx512-linux/clang-cmake-x86_64-sde-avx512-linux/test/sandbox/build/MultiSource/Benchmarks/7zip -ferror-limit 19 -fmessage-length 0 -pthread -fobjc-runtime=gcc -fcxx-exceptions -fexceptions -fdiagnostics-show-option -vectorize-loops -vectorize-slp -o Output/ArchiveCommandLine.llvm.o -x c++ /home/ssglocal/clang-cmake-x86_64-sde-avx512-linux/clang-cmake-x86_64-sde-avx512-linux/test/test-suite/MultiSource/Benchmarks/7zip/CPP/7zip/UI/Common/ArchiveCommandLine.cpp -faddrsig This reverts r357222 (git commit 64cccfcc72c44ea62f441b782d2177a90912769a)
  669. [WebAssembly] Merge used feature sets, update atomics linkage policy Summary: It does not currently make sense to use WebAssembly features in some functions but not others, so this CL adds an IR pass that takes the union of all used feature sets and applies it to each function in the module. This allows us to prevent atomics from being lowered away if some function has opted in to using them. When atomics is not enabled anywhere, we detect whether there exists any atomic operations or thread local storage that would be stripped and disallow linking with objects that contain atomics if and only if atomics or tls are stripped. When atomics is enabled, mark it as used but do not require it of other objects in the link. These changes allow libraries that do not use atomics to be built once and linked into both single-threaded and multithreaded binaries. Reviewers: aheejin, sbc100, dschuff Subscribers: jgravelle-google, hiraditya, sunfish, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59625
  670. Recommit "[DSE] Preserve basic block ordering using OrderedBasicBlock." Recommitting after addressing a buildbot failure. This reverts commit c87869ebea000dd6483de7c7451cb36c1d36f866.
  671. [llvm-readobj] Fix formatting of unknown note types
  672. [yaml2obj] Fixing opening empty yaml files. Essentially echo "" | yaml2obj crashes. This patch attempts to trim whitespace and determine if the yaml string in the file is empty or not. If the input is empty then it will not properly print out an error message and return an error code. Differential Revision: https://reviews.llvm.org/D59964 A test/tools/yaml2obj/empty.yaml M tools/yaml2obj/yaml2obj.cpp
  673. Update lit config for ld.lld command to match "ld\.lld" instead of trying to match respective regex. (It was able to work with ld-lld and ld1lld as well) Differential Revision: https://reviews.llvm.org/D59962
  674. [LSR] Fix signed overflow in GenerateCrossUseConstantOffsets. For the attached test case, unchecked addition of immediate starts and ends overflows, as they can be arbitrary i64 constants. Proof: https://rise4fun.com/Alive/Plqc Reviewers: qcolombet, gilr, efriedma Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D59218
  675. [BPF] add proper multi-dimensional array support For multi-dimensional array like below int a[2][3]; the previous implementation generates BTF_KIND_ARRAY type like below: . element_type: int . index_type: unsigned int . number of elements: 6 This is not the best way to represent arrays, esp., when converting BTF back to headers and users will see int a[6]; instead. This patch generates proper support for multi-dimensional arrays. For "int a[2][3]", the two BTF_KIND_ARRAY types will be generated: Type #n: . element_type: int . index_type: unsigned int . number of elements: 3 Type #(n+1): . element_type: #n . index_type: unsigned int . number of elements: 2 The linux kernel already supports such a multi-dimensional array representation properly. Signed-off-by: Yonghong Song <yhs@fb.com> Differential Revision: https://reviews.llvm.org/D59943
  676. [MC] Fix floating-point literal lexing. This patch has three related fixes to improve float literal lexing: 1. Make AsmLexer::LexDigit handle floats without a decimal point more consistently. 2. Make AsmLexer::LexFloatLiteral print an error for floats which are apparently missing an "e". 3. Make APFloat::convertFromString use binutils-compatible exponent parsing. Together, this fixes some cases where a float would be incorrectly rejected, fixes some cases where the compiler would crash, and improves diagnostics in some cases. Patch by Brandon Jones. Differential Revision: https://reviews.llvm.org/D57321
  677. [SelectionDAGBuilder] Fix 80 column violation. NFC
  678. [InterleavedAccessPass] Don't increase the number of bytes loaded. Even if the interleaving transform would otherwise be legal, we shouldn't introduce an interleaved load that is wider than the original load: it might have undefined behavior. It might be possible to perform some sort of mask-narrowing transform in some cases (using a narrower interleaved load, then extending the results using shufflevectors). But I haven't tried to implement that, at least for now. Fixes https://bugs.llvm.org/show_bug.cgi?id=41245 . Differential Revision: https://reviews.llvm.org/D59954
  679. Revert [DSE] Preserve basic block ordering using OrderedBasicBlock. This reverts r357208 (git commit c0bfd37d385c93711ef3a349599dba20e6b101ef) This causes a buildbot failure: http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/16124 FAILED: lib/IR/CMakeFiles/LLVMCore.dir/IRBuilder.cpp.o /home/buildslave/ps4-buildslave1/clang-with-thin-lto-ubuntu/install/stage2/bin/clang++ -DGTEST_HAS_RTTI=0 -D_DEBUG -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -Ilib/IR -I/home/buildslave/ps4-buildslave1/clang-with-thin-lto-ubuntu/llvm.src/lib/IR -Iinclude -I/home/buildslave/ps4-buildslave1/clang-with-thin-lto-ubuntu/llvm.src/include -fPIC -fvisibility-inlines-hidden -Werror -Werror=date-time -Werror=unguarded-availability-new -std=c++11 -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wstring-conversion -fdiagnostics-color -ffunction-sections -fdata-sections -flto=thin -O3 -UNDEBUG -fno-exceptions -fno-rtti -MD -MT lib/IR/CMakeFiles/LLVMCore.dir/IRBuilder.cpp.o -MF lib/IR/CMakeFiles/LLVMCore.dir/IRBuilder.cpp.o.d -o lib/IR/CMakeFiles/LLVMCore.dir/IRBuilder.cpp.o -c /home/buildslave/ps4-buildslave1/clang-with-thin-lto-ubuntu/llvm.src/lib/IR/IRBuilder.cpp clang-9: /home/buildslave/ps4-buildslave1/clang-with-thin-lto-ubuntu/llvm.src/lib/Analysis/OrderedBasicBlock.cpp:38: bool llvm::OrderedBasicBlock::comesBefore(const llvm::Instruction *, const llvm::Instruction *): Assertion `!(LastInstFound == BB->end() && NextInstPos != 0) && "Instruction supposed to be in NumberedInsts"' failed.
  680. [DSE] Preserve basic block ordering using OrderedBasicBlock. By extending OrderedBB to allow removing and replacing cached instructions, we can preserve OrderedBBs in DSE easily. This eliminates one source of quadratic compile time in DSE. Fixes PR38829. Reviewers: rnk, efriedma, hfinkel Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D59789
  681. [MemDepAnalysis] Allow caller to pass in an OrderedBasicBlock. If the caller can preserve the OBB, we can avoid recomputing the order for each getDependency call. Reviewers: efriedma, rnk, hfinkel Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D59788
  682. [SLP][X86] Add tests showing failure to commute icmp/fcmp by swapping predicate By swapping icmp/fcmp predicates we can commute their operands to improve vectorization
  683. [SLP][X86] Add tests showing failure to commute icmp/fcmp operands Some predicates are fully commutative - we should be able to easily commute their operands to improve vectorization
  684. Temporarily revert "SafepointIRVerifier port to new Pass Manager" to unbreak the modular bots and its follow-up commit. This reverts commit https://reviews.llvm.org/D59825 because it introduced a fatal error: cyclic dependency in module 'LLVM_intrinsic_gen': LLVM_intrinsic_gen -> LLVM_IR -> LLVM_intrinsic_gen
  685. [llvm-objcopy][NFC] Move ELF-specific logic into /ELF/ directory
  686. [X86] Teach the isel optimization for (x << C1) op C2 to (x op (C2>>C1)) << C1 to consider cases where C2>>C1 can fit an unsigned 32-bit immediate For 64-bit operations we should consider if the immediate can be made to fit in an unsigned 32-bits immedate. For OR/XOR this allows us to load the immediate with MOV32ri instead of movabsq. For AND this allows us to fold the immediate. Differential Revision: https://reviews.llvm.org/D59867
  687. Delay initialization of three static global maps, NFC This avoids allocating a few KB of heap memory on startup, and instead allocates these maps lazily. I noticed this while profiling LLD.
  688. Make helper functions static. NFC.
  689. [MIPS GlobalISel] Select float constants Select 32 and 64 bit float constants for MIPS32. Differential Revision: https://reviews.llvm.org/D59933
  690. gn build: Add some build files for clangd Enough to build the clangd binaries, but this is still missing build files for: - fuzzer - indexer - index/dex/dexp - benchmarks - xpc Differential Revision: https://reviews.llvm.org/D59899
  691. Add "git llvm revert" and "git llvm svn-lookup" subcommands Summary: The current git-svnrevert script only works with git-svn repos (e.g. using "git svn find-rev" to find the commit to revert). This adds a similar implementation that works with the llvm git command handler. Usage: ``` // Revert by svn id $ git llvm revert r123456 // See what commands would be run instead of actually reverting $ git llvm revert -n r123456 <full git revert + git commit commands> // Git commit hash also fine $ git llvm revert abc123456 // For convenience, the git->svn method can be used directly: $ git llvm svn-lookup abc123456 r123456 // Push revert upstream (drop the -n when ready) $ git llvm push -n ``` Regardless of how the command is invoked (with a svn revision or git hash), the message is: ``` Revert [LibFoo] Change Foo implementation This reverts r123456 (git commit abc123) ``` Reviewers: jyknight, mehdi_amini, jlebar Reviewed By: jlebar Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59837
  692. [DAG] Fix Lifetime Node ID hashing.
  693. [DAGCombiner] fold sext into negation As noted in D59818: %z = zext i8 %x to i32 %neg = sub i32 0, %z %r = sext i32 %neg to i64 => %z2 = zext i8 %x to i64 %r = sub i64 0, %z2 https://rise4fun.com/Alive/KzSR
  694. [x86] add vector test for sext of negate; NFC
  695. [AMDGPU] Clarify Code Object V2/V3 differences in AMDGPUUsage Ensure Code Object V2 documentation is complete, but always contains a warning and a link to the equivalent Code Object V3 documentation. Explicitly indicate that any note records present in a code object that are not documented must be considered deprecated and ignored. Differential Revision: https://reviews.llvm.org/D59782
  696. [Documentation] Proposal to change variable names Differential Revision: https://reviews.llvm.org/D59251
  697. [x86] avoid cmov in movmsk reduction This is probably the least important of our movmsk problems, but I'm starting at the bottom to reduce distractions. We were creating a select_cc which bypasses the select and bitmask codegen optimizations that we have now. If we produce a compare+negate instead, we allow things like neg/sbb carry bit hacks, and in all cases we avoid a cmov. There's no partial register update danger in these sequences because we always produce the zero-register xor ahead of the 'set' if needed. There seems to be a missing fold for sext of a bool bit here: negl %ecx movslq %ecx, %rax ...but that's an independent transform. Differential Revision: https://reviews.llvm.org/D59818
  698. [X86MacroFusion] Handle branch fusion (AMD CPUs). Summary: This adds a BranchFusion feature to replace the usage of the MacroFusion for AMD CPUs. See D59688 for context. Reviewers: andreadb, lebedev.ri Subscribers: hiraditya, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59872
  699. AMDGPU: Make exec mask optimzations more resistant to block splits Also improve the check for SALU instructions to also ignore implicit_def and other fake instructions.
  700. [X86] AMD Piledriver (BdVer2): fine-tune some latencies Based on llvm-exegesis measurements. Now that llvm-exegesis is ~2 magnitudes faster, and is a bit smarter, it is now possible to continue cleanup of the scheduler model. With this, there are no more latency inconsistencies for the opcodes that produce stable measurements, and only a few inconsistencies for unstable measurements (MMX_* opcodes, opcodes that llvm-exegesis measures by chaining - CMP, TEST, BT, SETcc, CVT, MOV, etc.)
  701. [NFC] Format InlineFeatureIgnoreList. To avoid more spurious clang-format changes when adding features (D59872).
  702. - Addressed comments
  703. - Addressed @jhenderson 's comments - Format patch
  704. [llvm-readobj] Add new helper function `getSymbolVersionByIndex()` Summary: When implementing `GNU style` dumper for `.gnu.version` section, we should find symbol version name by `vs_index`. Reviewers: jhenderson, rupprecht Reviewed By: rupprecht Subscribers: arphaman, rupprecht, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59545
  705. [DAGCombiner] Fold truncate(build_vector(x,y)) -> build_vector(truncate(x),truncate(y)) If scalar truncates are free, attempt to pre-truncate build_vectors source operands. Only attempt to do this before legalization as we often end up with truncations/extensions during build_vector lowering. Differential Revision: https://reviews.llvm.org/D59654
  706. [ARM GlobalISel] Run regbankselect test for Thumb. NFCI This should just work, since ARM mode and Thumb2 mode are at the same level of support now and should map the same to GPR and FPR.
  707. [yaml2obj][obj2yaml] - Teach yaml2obj/obj2yaml tools about STB_GNU_UNIQUE symbols. yaml2obj/obj2yaml does not support the symbols with STB_GNU_UNIQUE yet. Currently, obj2yaml fails with llvm_unreachable when met such a symbol. I faced it when investigated the https://bugs.llvm.org/show_bug.cgi?id=41196. Differential revision: https://reviews.llvm.org/D59875
  708. [asan] Add options -asan-detect-invalid-pointer-cmp and -asan-detect-invalid-pointer-sub options. This is in preparation to a driver patch to add gcc 8's -fsanitize=pointer-compare and -fsanitize=pointer-subtract. Disabled by default as this is still an experimental feature. Reviewed By: morehouse, vitalybuka Differential Revision: https://reviews.llvm.org/D59220
  709. [VPlan] Determine Vector Width programmatically. With this change, the VPlan native path is triggered with the directive: #pragma clang loop vectorize(enable) There is no need to specify the vectorize_width(N) clause. Patch by Francesco Petrogalli <francesco.petrogalli@arm.com> Differential Revision: https://reviews.llvm.org/D57598
  710. [X85][AVX] Add missing vXi16 broadcast fold patterns Now that D59484 has landed its easier to add these. Added missing AVX512BW v32i16 equivalents while I was at it.
  711. [ARM GlobalISel] Fix G_STORE with s1 G_STORE for 1-bit values uses a STRBi12, which stores the whole byte. Zero out the undefined bits before writing.
  712. [ARM GlobalISel] Fix selection of G_SELECT G_SELECT uses a 1-bit scalar for the condition, and is currently implemented with a plain CMPri against 0. This means that values such as 0x1110 are interpreted as true, when instead the higher bits should be treated as undefined and therefore ignored. Replace the CMPri with a TSTri against 0x1, which performs an implicit AND, yielding the expected result.
  713. [llvm-exegesis] Introduce a 'naive' clustering algorithm (PR40880) Summary: This is an alternative to D59539. Let's suppose we have measured 4 different opcodes, and got: `0.5`, `1.0`, `1.5`, `2.0`. Let's suppose we are using `-analysis-clustering-epsilon=0.5`. By default now we will start processing the `0.5` point, find that `1.0` is it's neighbor, add them to a new cluster. Then we will notice that `1.5` is a neighbor of `1.0` and add it to that same cluster. Then we will notice that `2.0` is a neighbor of `1.5` and add it to that same cluster. So all these points ended up in the same cluster. This may or may not be a correct implementation of dbscan clustering algorithm. But this is rather horribly broken for the reasons of comparing the clusters with the LLVM sched data. Let's suppose all those opcodes are currently in the same sched cluster. If i specify `-analysis-inconsistency-epsilon=0.5`, then no matter the LLVM values this cluster will **never** match the LLVM values, and thus this cluster will **always** be displayed as inconsistent. The solution is obviously to split off some of these opcodes into different sched cluster. But how do i do that? Out of 4 opcodes displayed in the inconsistency report, which ones are the "bad ones"? Which ones are the most different from the checked-in data? I'd need to go in to the `.yaml` and look it up manually. The trivial solution is to, when creating clusters, don't use the full dbscan algorithm, but instead "pick some unclustered point, pick all unclustered points that are it's neighbor, put them all into a new cluster, repeat". And just so as it happens, we can arrive at that algorithm by not performing the "add neighbors of a neighbor to the cluster" step. But that won't work well once we teach analyze mode to operate in on-1D mode (i.e. on more than a single measurement type at a time), because the clustering would depend on the order of the measurements. Instead, let's just create a single cluster per opcode, and put all the points of that opcode into said cluster. And simultaneously check that every point in that cluster is a neighbor of every other point in the cluster, and if they are not, the cluster (==opcode) is unstable. This is //yet another// step to bring me closer to being able to continue cleanup of bdver2 sched model.. Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=40880 | PR40880 ]]. Reviewers: courbet, gchatelet Reviewed By: courbet Subscribers: tschuett, jdoerfert, RKSimon, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59820
  714. [SelectionDAG] Add 2 tests for selection across basic blocks Summary: Add tests for selection across basic block boundary: * one test containing a buffer load, where part of the offset computation is placed in the predecessor of the load * similar test, but containing two buffer loads and shared computations Please note that the behaviour being tested will be updated in a subsequent commit. This commit was extracted from https://reviews.llvm.org/D59535. Reviewers: RKSimon Reviewed By: RKSimon Subscribers: jvesely, nhaehnle, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59690
  715. SafepointIRVerifier port to new Pass Manager Add missed include.
  716. SafepointIRVerifier port to new Pass Manager Straightforward port of StatepointIRVerifier pass to new Pass Manager framework. Reviewers: fedor.sergeev, reames Reviewed By: fedor.sergeev Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D59825
  717. [WebAssembly] Rename wasm fixup kinds These fixup kinds are not explicitly related to the code section. They are there to signal how to apply the fixup. Also, a couple of other minor wasm cleanups. Differential Revision: https://reviews.llvm.org/D59908
  718. Add reproduction instructions to llvm-objdump's embedded source test.
  719. Fix typoed variable name. NFCI.
  720. [NewPM] Fix a nasty bug with analysis invalidation in the new PM. The issue here is that we actually allow CGSCC passes to mutate IR (and therefore invalidate analyses) outside of the current SCC. At a minimum, we need to support mutating parent and ancestor SCCs to support the ArgumentPromotion pass which rewrites all calls to a function. However, the analysis invalidation infrastructure is heavily based around not needing to invalidate the same IR-unit at multiple levels. With Loop passes for example, they don't invalidate other Loops. So we need to customize how we handle CGSCC invalidation. Doing this without gratuitously re-running analyses is even harder. I've avoided most of these by using an out-of-band preserved set to accumulate the cross-SCC invalidation, but it still isn't perfect in the case of re-visiting the same SCC repeatedly *but* it coming off the worklist. Unclear how important this use case really is, but I wanted to call it out. Another wrinkle is that in order for this to successfully propagate to function analyses, we have to make sure we have a proxy from the SCC to the Function level. That requires pre-creating the necessary proxy. The motivating test case now works cleanly and is added for ArgumentPromotion. Thanks for the review from Philip and Wei! Differential Revision: https://reviews.llvm.org/D59869
  721. [X86] Add test cases from PR27202.
  722. [ARM] Remove dead function ARMMCCodeEmitter::getSOImmOpValue The last reference to this function was removed from the ARM td files in 2015 in rL225266. Differential Revision: https://reviews.llvm.org/D59868
  723. [x86] improve AVX lowering of vector zext If we know the 2 halves of an oversized zext-in-reg are the same, don't create those halves independently. I tried several different approaches to fold this, but it's difficult to get right during legalization. In the default path, we are creating a generic shuffle that looks like an unpack high, but it can get transformed into a different mask (a blend), so it's not straightforward to match that. If we try to fold after it actually becomes an X86ISD::UNPCKH node, we can't be sure what the operand node is - it might be a generic shuffle, or it could be some x86-specific op. From the test output, we should be doing something like this for SSE4.1 as well, but I'd rather leave that as a follow-up since it involves changing lowering actions. Differential Revision: https://reviews.llvm.org/D59777
  724. [x86] look through bitcast operand of MOVMSK This is not exactly NFC because it should make further combines of MOVMSK easier to match, but there should be no outward differences because we have isel patterns in place specifically to allow this. See: // Also support integer VTs to avoid a int->fp bitcast in the DAG.
  725. [X86ISelDAGToDAG] Move initialization of OptForSize and OptForMinSize from PreprocessISelDAG to runOnMachineFunction. NFCI This makes more sense as a place to initialize these. I don't think runOnMachineFunction was overriden when these cached values were originally created.
  726. test/CodeGen/X86/codegen-prepare-replacephi.mir requires a default triple
  727. [DAGCombiner] Teach TokenFactor pruning to peek through lifetime nodes Summary: Lifetime nodes were inhibiting TokenFactor simplification inhibiting chain-based optimizations. Reviewers: courbet, jyknight Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59897
  728. [LegalizeVectorTypes] Allow single loads and stores for more short vectors When lowering a load or store for TypeWidenVector, the type legalizer would use a single load or store if the associated integer type was legal or promoted. E.g. it loads a v4i8 as an i32 if i32 is legal/promotable. (See https://reviews.llvm.org/rL236528 for reference.) This applies that behaviour to vector types. If the vector type is TypePromoteInteger, the element type is going to be TypePromoteInteger as well, which will lead to have a single promoting load rather than N individual promoting loads. For instance, if we have a v3i1, we would now have a load of v4i1 instead of 3 loads of i1. Patch by Guillaume Marques. Thanks! Differential Revision: https://reviews.llvm.org/D56201
  729. [ConstantRangeTest] Add exhaustive intersectWith() test Add a test that checks the intersectWith() implementation against all 4-bit range pairs. The test uses a more explicit way of calculating the possible intersections, and checks that the right one is picked out according to the smallest set heuristic. This is in preparation for introducing intersectWith() variants that use different heuristics to pick an intersection range, if there are multiple possibilities.
  730. Fix llvm-rc tests. Summary: Follow-up for D56743. * Add more "--" in llvm-rc invocations. * Add llvm-rc to the tools list. This uses full path to llvm-rc in test RUN lines (llvm-lit -v), making them copy-pasteable. Reviewers: mstorsjo, zturner Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59858
  731. [WebAssembly] Add some whitespace to WebAssemblyFixIrreducibleControlFlow Differential Revision: https://reviews.llvm.org/D59855 modified: llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp
  732. Revert r356996 "[DAG] Avoid smart constructor-based dangling nodes." This patch appears to trigger very large compile time increases in halide builds.
  733. [ConstantRange] Add isWrappedSet() and isUpperSignWrapped() Split off from D59749. This adds isWrappedSet() and isUpperSignWrapped() set with the same behavior as isSignWrappedSet() and isUpperWrapped() for the respectively other domain. The methods isWrappedSet() and isSignWrappedSet() will not consider ranges of the form [X, Max] == [X, 0) and [X, SignedMax] == [X, SignedMin) to be wrapping, while isUpperWrapped() and isUpperSignWrapped() will. Also replace the checks in getUnsignedMin() and friends with method calls that implement the same logic.
  734. [CGP] Reset DT when optimizing select instructions Summary: A recent fix (r355751) caused a compile time regression because setting the ModifiedDT flag in optimizeSelectInst means that each time a select instruction is optimized the function walk in runOnFunction stops and restarts again (which was needed to build a new DT before we started building it lazily in r356937). Now that the DT is built lazily, a simple fix is to just reset the DT at this point, rather than restarting the whole function walk. In the future other places that set ModifiedDT may want to switch to just resetting the DT directly. But that will require an evaluation to ensure that they don't otherwise need to restart the function walk. Reviewers: spatel Subscribers: jdoerfert, llvm-commits, xur Tags: #llvm Differential Revision: https://reviews.llvm.org/D59889
  735. [opt-viewer] Teach optrecord.py about !Failure tags WarnMissedTransforms.cpp produces remarks that use !Failure tags. These weren't supported in optrecord.py, so if you encountered one in any of the tools, the tool would crash. Add them as a type of missed optimization. Differential Revision: https://reviews.llvm.org/D59895
  736. [ARM] Don't confuse the scheduler for very large VLDMDIA etc. ARMBaseInstrInfo::getNumLDMAddresses is making bad assumptions about the memory operands of load and store-multiple operations. This doesn't really fix the problem properly, but it's enough to prevent crashing, at least. Fixes https://bugs.llvm.org/show_bug.cgi?id=41231 . Differential Revision: https://reviews.llvm.org/D59834
  737. [AArch64][GlobalISel] Make G_PHI of v2s64, v4s32, v2s32 legal.
  738. [ConstantRange] Rename isWrappedSet() to isUpperWrapped() Split out from D59749. The current implementation of isWrappedSet() doesn't do what it says on the tin, and treats ranges like [X, Max] as wrapping, because they are represented as [X, 0) when using half-inclusive ranges. This also makes it inconsistent with the semantics of isSignWrappedSet(). This patch renames isWrappedSet() to isUpperWrapped(), in preparation for the introduction of a new isWrappedSet() method with corrected behavior.
  739. [opt-viewer] Make filter_=None by default in get_remarks and gather_results Right now, if you try to use optdiff.py on any opt records, it will fail because its calls to gather_results weren't updated to support filtering. Since filters are supposed to be optional, this makes them None by default in get_remarks and in gather_results. This allows other tools that don't support filtering to still use the functions as is. Differential Revision: https://reviews.llvm.org/D59894
  740. RegPressure: Fix crash on blocks with only dbg_value If there were only dbg_values in the block, recede would hit the beginning of the block and try to use thet dbg_value as a real instruction.
  741. [InstCombine] Use uadd.sat and usub.sat for canonicalization Start using the uadd.sat and usub.sat intrinsics for the existing canonicalizations. These intrinsics should optimize better than expanded IR, have better handling in the X86 backend and should be no worse than expanded IR in other backends, as far as we know. rL357012 already introduced use of uadd.sat for the add+umin pattern. Differential Revision: https://reviews.llvm.org/D58872
  742. [GlobalISel] Fix legalizer artifact combiner from crashing with invalid dead instructions. The artifact combiners push instructions which have been marked for deletion onto an list for the legalizer to deal with on return. However, for trunc(ext) combines the combiner routine recursively calls itself. When it does this the dead instructions list may not be empty, and the other combiners don't expect to be dealing with essentially invalid MIR (multiple vreg defs etc). This change fixes it by ensuring that the dead instructions are processed on entry into tryCombineInstruction. As a result, this fix exposed a few places in tests where G_TRUNC instructions were not being deleted even though they were dead. Differential Revision: https://reviews.llvm.org/D59892
  743. [X86MacroFusion][NFC] Add a bulldozer test.
  744. Reapply "AMDGPU: Scavenge register instead of findUnusedReg" This reapplies r356149, using the correct overload of findUnusedReg which passes the current iterator. This worked most of the time, because the scavenger iterator was moved at the end of the frame index loop in PEI. This would fail if the spill was the first instruction. This was further hidden by the fact that the scavenger wasn't passed in for normal frame index elimination.
  745. AMDGPU: Add testcase I meant to merge into r357093
  746. [X86] Add post-isel pseudos for rotate by immediate using SHLD/SHRD Haswell CPUs have special support for SHLD/SHRD with the same register for both sources. Such an instruction will go to the rotate/shift unit on port 0 or 6. This gives it 1 cycle latency and 0.5 cycle reciprocal throughput. When the register is not the same, it becomes a 3 cycle operation on port 1. Sandybridge and Ivybridge always have 1 cyc latency and 0.5 cycle reciprocal throughput for any SHLD. When FastSHLDRotate feature flag is set, we try to use SHLD for rotate by immediate unless BMI2 is enabled. But MachineCopyPropagation can look through a copy and change one of the sources to be different. This will break the hardware optimization. This patch adds psuedo instruction to hide the second source input until after register allocation and MachineCopyPropagation. I'm not sure if this is the best way to do this or if there's some other way we can make this work. Fixes PR41055 Differential Revision: https://reviews.llvm.org/D59391
  747. [PeepholeOpt] Don't stop simplifying copies on sequence of subregs This patch removes an overly conservative check that would prevent simplifying copies when the value we were tracking would go through several subregister indices. Indeed, the intend of this check was to not track values whenever we have to compose subregister, but actually what the check was doing was bailing anytime we see a second subreg, even if that second subreg would actually be the new source of truth (as opposed to a part of that subreg). Differential Revision: https://reviews.llvm.org/D59891
  748. [AArch64][SVE] Asm: error on unexpected SVE vector register type suffix This patch fixes an assembler bug that allowed SVE vector registers to contain a type suffix when not expected. The SVE unpredicated movprfx instruction is the only instruction affected. The following are examples of what was previously valid: movprfx z0.b, z0.b movprfx z0.b, z0.s movprfx z0, z0.s These instructions are now erroneous. Patch by Cullen Rhodes (c-rhodes) Reviewed By: sdesmalen Differential Revision: https://reviews.llvm.org/D59636
  749. AMDGPU: Enable the scavenger for large frames Another test is needed for the case where the scavenge fail, but there's another issue with that which needs an additional fix.
  750. AMDGPU: Add additional MIR tests for exec mask optimizations Also includes one example of how this transform is unsound. This isn't verifying the copies are used in the control flow intrinisic patterns. Also add option to disable exec mask opt pass. Since this pass is unsound, it may be useful to turn it off until it is fixed.
  751. AMDGPU: Skip debug_instr when collapsing end_cf Based on how these are inserted, I doubt this was causing a problem in practice.
  752. AMDGPU: Fix missing scc implicit def on s_andn2_b64_term Introduce new helper class to copy properties directly from the base instruction.
  753. New methods to check for under-/overflow in the SMT API Summary: Added methods to check for under-/overflow in additions, subtractions, signed divisions/modulus, negations, and multiplications. Reviewers: ddcc, gou4shi1 Reviewed By: ddcc, gou4shi1 Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59796
  754. PEI: Delay checking requiresFrameIndexReplacementScavenging Currently this is called before the frame size is set on the function. For AMDGPU, the scavenger is used for large frames where part of the offset needs to be materialized in a register, so estimating the frame size is useful for knowing whether the scavenger is useful.
  755. [MCA] Fix -Wparentheses warning breaking the -Werror build. Waring was introduced at r357074.
  756. AMDGPU: Don't hardcode num defs for MUBUF instructions This shouldn't change anything since the no-ret atomics are selected later.
  757. MIR: Freeze reserved regs after parsing everything The AMDGPU implementation of getReservedRegs depends on MachineFunctionInfo fields that are parsed from the YAML section. This was reserving the wrong register since it was setting the reserved regs before parsing the correct one. Some tests were relying on the default reserved set for the assumed default calling convention.
  758. AMDGPU: wave_barrier is not isBarrier This is not a control flow instruction, so should not be marked as isBarrier. This fixes a verifier error if followed by unreachable.
  759. [BPF] use std::map to ensure consistent output The .BTF.ext FuncInfoTable and LineInfoTable contain information organized per ELF section. Current definition of FuncInfoTable/LineInfoTable is: std::unordered_map<uint32_t, std::vector<BTFFuncInfo>> FuncInfoTable std::unordered_map<uint32_t, std::vector<BTFLineInfo>> LineInfoTable where the key is the section name off in the string table. The unordered_map may cause the order of section output different for different platforms. The same for unordered map definition of std::unordered_map<std::string, std::unique_ptr<BTFKindDataSec>> DataSecEntries where BTF_KIND_DATASEC entries may have different ordering for different platforms. This patch fixed the issue by using std::map. Test static-var-derived-type.ll is modified to generate two DataSec's which will ensure the ordering is the same for all supported platforms. Signed-off-by: Yonghong Song <yhs@fb.com>
  760. [X86MacroFusion][NFC] Improve macrofusion testing. Add negative tests. Add arithmetic/inc/cmp/and macrofusion tests.
  761. [MCA][Pipeline] Don't visit stages in reverse order when calling method cycleEnd(). NFCI There is no reason why stages should be visited in reverse order. This patch allows the definition of stages that push instructions forward from their cycleEnd() routine.
  762. AMDGPU: Fix areLoadsFromSameBasePtr for DS atomics The offset operand index is different for atomics.
  763. gn build: Merge r357047
  764. [DAGCombiner] Unify Lifetime and memory Op aliasing. Rework BaseIndexOffset and isAlias to fully work with lifetime nodes and fold in lifetime alias analysis. This is mostly NFC. Reviewers: courbet Reviewed By: courbet Subscribers: hiraditya, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59794
  765. [DAGCombine] Refactor GatherAllAliases. NFCI.
  766. Re-commit r355490 "[CodeGen] Omit range checks from jump tables when lowering switches with unreachable default" Original commit by Ayonam Ray. This commit adds a regression test for the issue discovered in the previous commit: that the range check for the jump table can only be omitted if the fall-through destination of the jump table is unreachable, which isn't necessarily true just because the default of the switch is unreachable. This addresses the missing optimization in PR41242. > During the lowering of a switch that would result in the generation of a > jump table, a range check is performed before indexing into the jump > table, for the switch value being outside the jump table range and a > conditional branch is inserted to jump to the default block. In case the > default block is unreachable, this conditional jump can be omitted. This > patch implements omitting this conditional branch for unreachable > defaults. > > Differential Revision: https://reviews.llvm.org/D52002 > Reviewers: Hans Wennborg, Eli Freidman, Roman Lebedev
  767. Revert of 357063 [AMDGPU][MC] Corrected handling of tied src for atomic return MUBUF opcodes Reason: the change was mistakenly committed before review
  768. The IR verifier currently supports the constrained floating point intrinsics, but the implementation is hard to extend. It doesn't currently have an easy way to support intrinsics that, for example, lack a rounding mode. This will be needed for impending new constrained intrinsics. This code is split out of D55897 <https://reviews.llvm.org/D55897>, which itself was split out of D43515 <https://reviews.llvm.org/D43515>. Reviewed by: arsenm Differential Revision: http://reviews.llvm.org/D59830
  769. [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal Cleanup isAArch64FrameOffsetLegal by: - Merging the large switch statement to reuse AArch64InstrInfo::getMemOpInfo(). - Using AArch64InstrInfo::getUnscaledLdSt() to determine whether an instruction has an unscaled variant. - Simplifying the logic that calculates the offset to fit the immediate. Reviewers: paquette, evandro, eli.friedman, efriedma Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D59636
  770. [AMDGPU][MC] Corrected handling of tied src for atomic return MUBUF opcodes See bug 40917: https://bugs.llvm.org/show_bug.cgi?id=40917 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D59305
  771. [X86][SSE] Add shuffle test case for PR41249
  772. [AArch64] Adds cases for LDRSHWui and LDRSHXui to getMemOpInfo This patch also adds cases PRFUMi and PRFMui. This change was discussed in https://reviews.llvm.org/D59635.
  773. [Support] MemoryBlock size should reflect the requested size This patch mirrors the change made to the Unix equivalent in r351916. This in turn fixes bugs related to the use of FileOutputBuffer to output to "-", i.e. stdout, on Windows. Differential Revision: https://reviews.llvm.org/D59663
  774. Revert rL356864 : [X86][SSE41] Start shuffle combining from ZERO_EXTEND_VECTOR_INREG (PR40685) Enable SSE41 ZERO_EXTEND_VECTOR_INREG shuffle combines - for the PMOVZX(PSHUFD(V)) -> UNPCKH(V,0) pattern we reduce the shuffles (port5-bottleneck on Intel) at the expense of creating a zero (pxor v,v) and an extra register move - which is a good trade off as these are pretty cheap and in most cases it doesn't increase register pressure. This also exposed a missed opportunity to use combine to ZERO_EXTEND_VECTOR_INREG with folded loads - even if we're in the float domain. ........ Causes PR41249
  775. [DWARF] Add D to Seen early to avoid duplicate elements in Worklist
  776. [DWARF] Simplify DWARFVerifier::handleDebugAbbrev. NFC
  777. [DAGCombiner] Don't allow addcarry if the carry producer is illegal. getAsCarry() checks that the input argument is a carry-producing node before allowing a transformation to addcarry. This patch adds a check to make sure that the carry-producing node is legal. If it is not, it may not remain in a form that is manageable by the target backend. The test case caused a compilation failure during instruction selection for this reason on SystemZ. Patch by Ulrich Weigand. Review: Sanjay Patel https://reviews.llvm.org/D59822
  778. [llvm-dwarfdump] Simplify -o handling ToolOutputFile handles '-' so no need to specialize here. Also, we neither reassign the variable nor pass it around, thus no need to use std::unique_ptr<ToolOutputFile>. exit(1) -> return 1; to call the destructor of raw_fd_stream
  779. [X86] Add test cases for missed opportunities in (x << C1) op C2 to (x op (C2>>C1)) << C1 transform. We handle the case where the C2 does not fit in a signed 32-bit immediate, but (C2>>C1) does. But there's also some 64-bit opportunities when C2 is not an unsigned 32-bit immediate, but (C2>>C1) is. For OR/XOR this allows us to load the immediate with with MOV32ri instead of a movabsq. For AND it allows us to use a 32-bit AND and fold the immediate.
  780. [X86] When iselling (x << C1) and/or/xor C2 as (x and/or/xor (C2>>C1)) << C1, go through the isel table instead of manually selecting. Previously we manually selected the AND/OR/XOR with immediate and the SHL(or ADD if the shift is 1). But this was missing out on the opportunity to use a 64 bit AND with a 32-bit immediate and possibly other isel tricks we have built into the tables. Instead, insert the new nodes into the DAG using insertDAGNode and allow them each to be selected through the normal table.
  781. [NFC][PowerPC] Custom PowerPC specific machine-scheduler This patch lays the groundwork for extending the generic machine scheduler by providing a PPC-specific implementation. There are no functional changes as this is an incremental patch that simply provides the necessary overrides which just encapsulate the behavior of the generic scheduler. Subsequent patches will add specific behavior. Differential Revision: https://reviews.llvm.org/D59284
  782. [X86] Autogenerate complete checks. NFC
  783. [X86] Simplify some code in matchBitExtract by using ANY_EXTEND. We were manually outputting the code we would get from selecting ANY_EXTEND. We can save some code by just letting an ANY_EXTEND go through isel on its own.
  784. [Remarks] Emit a section containing remark diagnostics metadata A section containing metadata on remark diagnostics will be emitted if the flag (-mllvm) -remarks-section is present. For now, the metadata is: * a magic number for remarks: "REMARKS\0" * the version number: a little-endian uint64_t * the absolute file path to the serialized remark diagnostics: a null-terminated string. Differential Revision: https://reviews.llvm.org/D59571
  785. gn build: Add build files for clang-include-fixer and find-all-symbols Differential Revision: https://reviews.llvm.org/D59838
  786. [ConstantRange] Exclude full set from isSignWrappedSet() Split off from D59749. This uses a simpler and more efficient implementation of isSignWrappedSet(), and considers full sets as non-wrapped, to be consistent with isWrappedSet(). Otherwise the behavior is unchanged. There are currently only two users of this function and both already check for isFullSet() || isSignWrappedSet(), so this is not going to cause a change in overall behavior. Differential Revision: https://reviews.llvm.org/D59848
  787. [cmake] Reset variable before using it A bunch of macros use the same variable name, and since CMake macros don't get their own scope, the value persists across macro invocations, and we can end up exporting targets which shouldn't be exported. Clear the variable before each use to avoid this. Converting these macros to functions would also help, since it would avoid the variable leaking into its parent scope, and that's something I plan to follow up with. It won't fully address the problem, however, since functions still inherit variables from their parent scopes, so if someone in the parent scope just happened to use the same variable name we'd still have the same issue.
  788. [PPC] Refactor PPCBranchSelector.cpp This patch splits the huge function PPCBranchSelector.cpp:runOnMachineFunction into several smaller functions. No functional change. Differential Revision: https://reviews.llvm.org/D59623
  789. [LiveRange] Reset the VNIs when splitting subranges When splitting a subrange we end up with two different subranges covering two different, non overlapping, lanes. As part of this splitting the VNIs of the original live-range need to be dispatched to the subranges according to which lanes they are actually defining. Prior to this patch we were assuming that all values were defining all lanes. This was wrong as demonstrated by llvm.org/PR40835. Differential Revision: https://reviews.llvm.org/D59731
  790. [SDAG] add simplifications for FP at node creation time We have the folds for fadd/fsub/fmul already in DAGCombiner, so it may be possible to remove that code if we can guarantee that these ops are zapped before they can exist.
  791. [PowerPC] Remove UseVSXReg The UseVSXReg flag can be safely removed and the code cleaned up. Patch By: Yi-Hong Liu Differential Revision: https://reviews.llvm.org/D58685
  792. Revert "[llvm] Reapply "Prevent duplicate files in debug line header in dwarf 5."" This reverts commit rL357020. The commit broke the test llvm/test/tools/llvm-objdump/embedded-source.test on some builds including clang-ppc64be-linux-multistage, clang-s390x-linux, clang-with-lto-ubuntu, clang-x64-windows-msvc, llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast (and others).
  793. [WebAssembly] Initial implementation of PIC code generation This change implements lowering of references global symbols in PIC mode. This change implements lowering of global references in PIC mode using a new @GOT reference type. @GOT references can be used with function or data symbol names combined with the get_global instruction. In this case the linker will insert the wasm global that stores the address of the symbol (either in memory for data symbols or in the wasm table for function symbols). For now I'm continuing to use the R_WASM_GLOBAL_INDEX_LEB relocation type for this type of reference which means that this relocation type can refer to either a global or a function or data symbol. We could choose to introduce specific relocation types for GOT entries in the future. See the current dynamic linking proposal: https://github.com/WebAssembly/tool-conventions/blob/master/DynamicLinking.md Differential Revision: https://reviews.llvm.org/D54647
  794. gn build: Format all build files Re-ran `git ls-files '*.gn' '*.gni' | xargs llvm/utils/gn/gn.py format`.
  795. gn build: Merge r356929 (effectively relands r353518, reverted in r353621)
  796. [llvm] Reapply "Prevent duplicate files in debug line header in dwarf 5." Reapply rL356941 after regenerating the object file in the failing test llvm/test/tools/llvm-objdump/embedded-source.test from source. Original commit message: [llvm] Prevent duplicate files in debug line header in dwarf 5. Motivation: In previous dwarf versions, file name indexes started from 1, and the primary source file was not explicit. Dwarf 5 standard (6.2.4) prescribes the primary source file to be explicitly given an entry with an index number 0. The current implementation honors the specification by just duplicating the main source file, once with index number 0, and later maybe with another index number. While this is compliant with the letter of the standard, the duplication causes problems for consumers of this information such as lldb. (Some files are duplicated, where only some of them have a line table although all refer to the same file) With this change, dwarf 5 debug line section files always start from 0, and the zeroth entry is not duplicated whenever possible. This requires different handling of dwarf 4 and dwarf 5 during generation (e.g. when a function returns an index zero for a file name, it signals an error in dwarf 4, but not in dwarf 5) However, I think the minor complication is worth it, because it enables all consumers (lldb, gdb, dwarfdump, objdump, and so on) to treat all files in the file name list homogenously. Tags: #llvm, #debug-info Differential Revision: https://reviews.llvm.org/D59515
  797. [llvm-objcopy] - Strip sections before symbols. This is a fix for https://bugs.llvm.org/show_bug.cgi?id=40007. Idea is to swap the order of stripping. So that we strip sections before symbols what allows us to strip relocation sections without emitting the error about relative symbols. Differential revision: https://reviews.llvm.org/D59763
  798. [WebAssembly] Don't analyze branches after CFGStackify Summary: `WebAssembly::analyzeBranch` now does not analyze anything if the function is CFG stackified. We were previously doing similar things by checking if a branch's operand is whether an integer or an MBB, but this failed to bail out when a BB did not have any terminators. Consider this case: ``` bb0: try $label0 call @foo // unwinds to %ehpad bb1: ... br $label0 // jumps to %cont. can be deleted ehpad: catch ... cont: end_try ``` Here `br $label0` will be deleted in CFGStackify's `removeUnnecessaryInstrs` function, because we jump to the %cont block even without the branch. But in this case, MachineVerifier fails to verify this, because `ehpad` is not a successor of `bb1` even if `bb1` does not have any terminators. MachineVerifier incorrectly thinks `bb1` falls through to the next block. This pass now consistently rejects all analysis after CFGStackify whether a BB has terminators or not, also making the MachineVerifier work. (MachineVerifier does not try to verify relationships between BBs if `analyzeBranch` fails, the behavior we want after CFGStackify.) This also adds a new option `-wasm-disable-ehpad-sort` for testing. This option helps create the sorted order we want to test, and without the fix in this patch, the tests in cfg-stackify-eh.ll fail at MachineVerifier with `-wasm-disable-ehpad-sort`. Reviewers: dschuff Subscribers: sunfish, sbc100, jgravelle-google, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59740
  799. [ConstantRange] Fix outdated comment; NFC Full/empty is required now, so there is no default.
  800. [InstCombine] Add tests for ssubo X, C -> saddo X, -C; NFC Add baseline tests for canonicalization of ssubo X, C -> saddo X, -C. Patch by Dan Robertson. Differential Revision: https://reviews.llvm.org/D59653
  801. [InstCombine] form uaddsat from add+umin (PR14613) This is the last step towards solving the examples shown in: https://bugs.llvm.org/show_bug.cgi?id=14613 With this change, x86 should end up with psubus instructions when those are available. All known codegen issues with expanding the saturating intrinsics were resolved with: D59006 / rL356855 We also have some early evidence in D58872 that using the intrinsics will lead to better perf. If some target regresses from this, custom lowering of the intrinsics (as in the above for x86) may be needed.
  802. [WebAssembly] Add CFGStacikfied field to WebAssemblyFunctionInfo Summary: This adds `CFGStackified` field and its serialization to WebAssemblyFunctionInfo. Reviewers: dschuff Subscribers: sunfish, sbc100, jgravelle-google, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59747
  803. [WebAssembly] Support WebAssemblyFunctionInfo serialization Summary: The framework for supporting target-specific MachineFunctionInfo was added in r356215. This adds serialization support for WebAssemblyFunctionInfo on top of that. This patch only adds the framework and does not actually serialize anything at this point; we have to add YAML mapping later for the fields in WebAssemblyFunctionInfo we want to serialize if necessary. Reviewers: dschuff, arsenm Subscribers: sunfish, wdng, sbc100, jgravelle-google, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59737
  804. [WebAssembly] Fix a bug when mixing TRY/LOOP markers Summary: When TRY and LOOP markers are in the same BB and END_TRY and END_LOOP markers are in the same BB, END_TRY should be _before_ END_LOOP, because LOOP is always before TRY if they are in the same BB. (TRY is placed in the latest possible position, whereas LOOP is in the earliest possible position.) Reviewers: dschuff Subscribers: sunfish, sbc100, jgravelle-google, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59751
  805. [WebAssembly] Fix bugs in BLOCK/TRY placement Summary: Before we placed all TRY/END_TRY markers before placing BLOCK/END_BLOCK markers. This couldn't handle this case: ``` bb0: br bb2 bb1: // nearest common dominator of bb3 and bb4 br_if ... bb3 br bb4 bb2: ... bb3: call @foo // unwinds to ehpad bb4: call @bar // unwinds to ehpad ehpad: catch ... ``` When we placed TRY markers, we placed it in bb1 because it is the nearest common dominator of bb3 and bb4. But because bb0 jumps to bb2, when we placed block markers, we ended up with interleaved scopes like ``` block try end_block catch end_try ``` which was not correct. This patch fixes the bug by placing BLOCK and TRY markers in one pass while iterating BBs in a function. This also adds some more routines to `placeTryMarkers`, because we now have to assume that there can be previously placed BLOCK and END_BLOCK. Reviewers: dschuff Subscribers: sunfish, sbc100, jgravelle-google, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59739
  806. [InstCombine] add tests for uaddsat using min; NFC
  807. [InstCombine] update tests to use FileCheck; NFC
  808. [llvm-exegesis] Allow the target to disable the selection of some registers. Summary: This prevents "Cannot encode high byte register in REX-prefixed instruction" from happening on instructions that require REX encoding when AH & co get selected. On the down side, these 4 registers can no longer be selected automatically, but this avoids having to expose all the X86 encoding complexity. Reviewers: gchatelet Subscribers: tschuett, jdoerfert, llvm-commits, bdb Tags: #llvm Differential Revision: https://reviews.llvm.org/D59821
  809. [RISCV] Update setcc-logic.ll codegen test This should have been updated as part of D59753.
  810. [MCA] Correctly update the UsedResourceGroups mask in the InstrBuilder. Found by inspection when looking at the debug output of MCA. This problem was latent, and none of the upstream models were affected by it. No functional change intended.
  811. Test commit: fix typo
  812. [SystemZ] Remove LRMux pseudo instruction. This instruction is unused and not needed. Review: Ulrich Weigand.
  813. [DAG] Avoid smart constructor-based dangling nodes. Various SelectionDAG non-combine operations (e.g. the getNode smart constructor and legalization) may leave dangling nodes by applying optimizations or not fully pruning unused result values. This can result in nodes that are never added to the worklist and therefore can not be pruned. Add a node inserter as the current node deleter to make sure such nodes have the chance of being pruned. Many minor changes, mostly positive.
  814. Moved body of methods dump to .cpp file to fix compilation when modules are enabled
  815. [RISCV] Improve codegen for icmp {ne,eq} with a constant Adds two patterns to improve the codegen of GPR value comparisons with small constants. Instead of first loading the constant into another register and then doing an XOR of those registers, these patterns directly use the constant as an XORI immediate.
  816. [TargetLowering] Add SimplifyDemandedBits support for ISD::INSERT_VECTOR_ELT This helps us relax the extension of a lot of scalar elements before they are inserted into a vector. Its exposes an issue in DAGCombiner::convertBuildVecZextToZext as some/all the zero-extensions may be relaxed to ANY_EXTEND, so we need to handle that case to avoid a couple of AVX2 VPMOVZX test regressions. Once this is in it should be easier to fix a number of remaining failures to fold loads into VBROADCAST nodes. Differential Revision: https://reviews.llvm.org/D59484
  817. Fix nondeterminism introduced in r353954 DenseMap iteration order is not guaranteed, use MapVector instead. Fix provided by srhines. Differential Revision: https://reviews.llvm.org/D59807
  818. [TableGen] Let list elements have a trailing comma Let lists have an trailing comma to allow cleaner diffs e.g: def : Features<[FeatureA, FeatureB, ]>; Reviewed By: hfinkel Differential Revision: https://reviews.llvm.org/D59247
  819. [TableGen] Give meaningful msg for def use in multiclass When one mistakenly specifies 'def' instead of using 'defm', the error message is quite misleading: 'Couldn't find class..' Instead, it should recommend using defm if the multiclass of same name exists. Reviewed By: hfinkel Differential Revision: https://reviews.llvm.org/D59294
  820. [ARM][Asm] Accept upper case coprocessor number and registers Differential revision: https://reviews.llvm.org/D59760
  821. [llvm-dlltool] Set a proper machine type for weak symbol object files This makes GNU binutils not reject the libraries outright. GNU ld handles weak externals slightly differently though, so it can't use them for aliases in import libraries, but this makes GNU ld able to use the rest of the import libraries. LLD accepted object files with machine type 0 aka IMAGE_FILE_MACHINE_UNKNOWN. Differential Revision: https://reviews.llvm.org/D59742
  822. [ADT] Update SmallVectorTest.EmplaceBack tests after rL356312 rL356312 changed the return type of emplace_back from void to reference. Update the tests to check the behavior. Reviewers: dblaikie Reviewed By: dblaikie Subscribers: dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59809
  823. [X86] In matchBitExtract, place all of the new nodes before Node's position in the DAG for the topological sort. We were using OrigNBits, but that put all the nodes before the node we used to start the control computation. This caused some node earlier than the sequence we inserted to be selected before the sequence we created. We want our new sequence to be selected first since it depends on OrigNBits. I don't have a test case. Found by reviewing the code.
  824. [X86] In matchBitExtract, if we need to truncate the BEXTR make sure we put the BEXTR at Node's position in the DAG for the topological sort. We were using OrigNBits, but that doesn't guarantee that it will be selected before the nodes that make up X.
  825. [X86] Remove unneeded FIXME. NFC We do fold loads right below this.
  826. X86Parser: Fix potential reference to deleted object Within the MatchFPUWaitAlias function, Operands[0] is potentially overwritten leading to &Op referencing a deleted object. To fix this, assign the reference after the function. Differential Revision: https://reviews.llvm.org/D57376
  827. X86AsmParser: Do not process a non-existent token This error can only happen if an unfinished operation is at Eof. Patch by Brandon Jones Differential Revision: https://reviews.llvm.org/D57379
  828. [ARM] Add missing memory operands to a bunch of instructions. This should hopefully lead to minor improvements in code generation, and more accurate spill/reload comments in assembly. Also fix isLoadFromStackSlotPostFE/isStoreToStackSlotPostFE so they don't lead to misleading assembly comments for merged memory operands; this is technically orthogonal, but in practice the relevant memory operand lists don't show up without this change. Differential Revision: https://reviews.llvm.org/D59713
  829. [x86] add tests for vector cmps; NFC
  830. Revert "AMDGPU: Scavenge register instead of findUnusedReg" This reverts r356149. This is crashing on rocBLAS.
  831. AMDGPU: Remove unnecessary check for isFullCopy Subregister indexes are not used for physical register operands, so isFullCopy is implied by the physical register check.
  832. AMDGPU: Make collapse-endcf test more useful Without a VALU instruction in the return block, these were mostly testing the path to delete exec mask code before s_endpgm rather than the end cf handling.
  833. [AArch64] Prefer "mov" over "orr" to materialize constants. This is generally more readable due to the way the assembler aliases work. (This causes a lot of test changes, but it's not really as scary as it looks at first glance; it's just mechanically changing a bunch of checks for orr to check for mov instead.) Differential Revision: https://reviews.llvm.org/D59720
  834. AMDGPU: Set hasSideEffects 0 on _term instructions These were defaulting to true, but they are just wrappers around bit operations. This avoids regressions in the exec mask optimization passes in a future commit.
  835. Revert "[llvm] Prevent duplicate files in debug line header in dwarf 5." This reverts commit 312ab05887d0e2caa29aaf843cefe39379a98d36. My commit broke the build; I will revert and find out what happened.
  836. [LLVM-C] Add binding to look up intrinsic by name Summary: Add a binding to Function::lookupIntrinsicID so clients don't have to go searching the ID table themselves. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59697
  837. AMDGPU: Add support for cross address space synchronization scopes Differential Revision: https://reviews.llvm.org/D59517
  838. [llvm] Prevent duplicate files in debug line header in dwarf 5. Summary: Motivation: In previous dwarf versions, file name indexes started from 1, and the primary source file was not explicit. Dwarf 5 standard (6.2.4) prescribes the primary source file to be explicitly given an entry with an index number 0. The current implementation honors the specification by just duplicating the main source file, once with index number 0, and later maybe with another index number. While this is compliant with the letter of the standard, the duplication causes problems for consumers of this information such as lldb. (Some files are duplicated, where only some of them have a line table although all refer to the same file) With this change, dwarf 5 debug line section files always start from 0, and the zeroth entry is not duplicated whenever possible. This requires different handling of dwarf 4 and dwarf 5 during generation (e.g. when a function returns an index zero for a file name, it signals an error in dwarf 4, but not in dwarf 5) However, I think the minor complication is worth it, because it enables all consumers (lldb, gdb, dwarfdump, objdump, and so on) to treat all files in the file name list homogenously. Reviewers: dblaikie, probinson, aprantl, espindola Reviewed By: probinson Subscribers: emaste, jvesely, nhaehnle, aprantl, javed.absar, arichardson, hiraditya, MaskRay, rupprecht, jdoerfert, llvm-commits Tags: #llvm, #debug-info Differential Revision: https://reviews.llvm.org/D59515
  839. [SLPVectorizer] Merge reorderAltShuffleOperands into reorderInputsAccordingToOpcode As discussed on D59738, this generalizes reorderInputsAccordingToOpcode to handle multiple + non-commutative instructions so we can get rid of reorderAltShuffleOperands and make use of the extra canonicalizations that reorderInputsAccordingToOpcode brings. Differential Revision: https://reviews.llvm.org/D59784
  840. [SelectionDAG] Add icmp UNDEF handling to SelectionDAG::FoldSetCC First half of PR40800, this patch adds DAG undef handling to icmp instructions to match the behaviour in llvm::ConstantFoldCompareInstruction and SimplifyICmpInst, this permits constant folding of vector comparisons where some elements had been reduced to UNDEF (by SimplifyDemandedVectorElts etc.). This involved a lot of tweaking to reduced tests as bugpoint loves to reduce icmp arguments to undef........ Differential Revision: https://reviews.llvm.org/D59363
  841. [CGP] Build the DominatorTree lazily Summary: In r355512 CGP was changed to build the DominatorTree only once per function traversal, to avoid repeatedly building it each time it was accessed. This solved one compile time issue but introduced another. In the second case, we now were building the DT unnecessarily many times when we performed many function traversals (i.e. more than once per function when running CGP because of changes made each time). Change to saving the DT in the CodeGenPrepare object, and building it lazily when needed. It is reset whenever we need to rebuild it. The case that exposed the issue there are 617 functions, and we walk them (i.e. execute the "while (MadeChange)" loop in runOnFunction) a total of 12083 times (so previously we were building the DT 12083 times). With this patch we only build the DT 844 times (average of 1.37 times per function). We dropped the total time to compile this file from 538.11s without this patch to 339.63s with it. There is still an issue as CGP is taking much longer than all other passes even with this patch, and before a recent compiler release cut at r355392 the total time to this compile was only 97 sec with a huge reduction in CGP time. I suspect that one of the other recent changes to CGP led to iterating each function many more times on average, but I need to do some more investigation. Reviewers: spatel Subscribers: jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59696
  842. [x86] add another vector zext test; NFC Goes with the proposal in D59777
  843. Moved everything SMT-related to LLVM and updated the cmake scripts. Differential Revision: https://reviews.llvm.org/D54978
  844. MISched: Don't schedule regions with 0 instructions I think this is correct, but may not necessarily be the correct fix for the assertion I'm really trying to solve. If a scheduling region was found that only has dbg_value instructions, the RegPressure tracker would end up in an inconsistent state because it would skip over any debug instructions and point to an instruction outside of the scheduling region. It may still be possible for this to happen if there are some real schedulable instructions between dbg_values, but I haven't managed to break this. The testcase is extremely sensitive and I'm not sure how to make it more resistent to future scheduler changes that would avoid stressing this situation.
  845. merge-request.sh: Update 8.0 metabug for 8.0.1
  846. AMDGPU: Preserve LiveIntervals in WQM This seems to already be done, but wasn't marked.
  847. [llvm-objcopy]Preserve data in segments not covered by sections llvm-objcopy previously knew nothing about data in segments that wasn't covered by section headers, meaning that it wrote zeroes instead of what was there. As it is possible for this data to be useful to the loader, this patch causes llvm-objcopy to start preserving this data. Data in sections that are explicitly removed continues to be written as zeroes. This fixes https://bugs.llvm.org/show_bug.cgi?id=41005. Reviewed by: jakehehrlich, rupprecht Differential Revision: https://reviews.llvm.org/D59483
  848. [SLPVectorizer] Update file missed in rL356913 Differential Revision: https://reviews.llvm.org/D59738
  849. [x86] add tests for vector zext; NFC The AVX1 lowering is poor.
  850. [SLPVectorizer] reorderInputsAccordingToOpcode - remove non-Instruction canonicalization Remove attempts to commute non-Instructions to the LHS - the codegen changes appear to rely on chance more than anything else and also have a tendency to fight existing instcombine canonicalization which moves constants to the RHS of commutable binary ops. This is prep work towards: (a) reusing reorderInputsAccordingToOpcode for alt-shuffles and removing the similar reorderAltShuffleOperands (b) improving reordering to optimized cases with commutable and non-commutable instructions to still find splat/consecutive ops. Differential Revision: https://reviews.llvm.org/D59738
  851. Revert 356905 Commited from wrong directory...
  852. Python 2/3 compat: queue vs Queue Differential Revision: https://reviews.llvm.org/D59590
  853. MinidumpYAML.cpp: Fix some code standard violations missed during review functions should begin with lower case letters. NFC.
  854. [RegAlloc] Simplify MIR test Remove the IR part from test/CodeGen/X86/regalloc-copy-hints.mir (added by r355854). To make the test remain functional, the parts of the MBB names referring to BB names have been removed, as well as all machine memory operands.
  855. [DebugInfo] IntelJitEventListener follow up for "add SectionedAddress ..." Following r354972 the Intel JIT Listener would not report line table information because the section indices did not match. There was a similar issue with the PerfJitEventListener. This change performs the section index lookup when building the object address used to query the line table information. Differential Revision: https://reviews.llvm.org/D59490
  856. [clang-tidy] Separate the check-facing interface Summary: Move ClangTidyCheck to a separate header/.cpp Switch checks to #include "ClangTidyCheck.h" Mention ClangTidyCheck.h in the docs Reviewers: hokein, gribozavr, aaron.ballman Reviewed By: hokein Subscribers: mgorny, javed.absar, xazax.hun, arphaman, jdoerfert, llvm-commits, cfe-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D59714
  857. [llvm-objcopy] - Refactor the code. NFC. The idea of the patch is about to move out the code to a new helper static functions (to reduce the size of 'handleArgs' and to isolate the parts of it's logic). Differential revision: https://reviews.llvm.org/D59762
  858. [MIPS GlobalISel] Select copy for arguments from FPRBRegBank Move selectCopy into MipsInstructionSelector class. Select copy for arguments from FPRBRegBank for MIPS32. Differential Revision: https://reviews.llvm.org/D59644
  859. gn build: Clean up README.rst a bit - Make introduction a bit shorter - Add a `git clone` step to Quick start - Put command to run first in each of the Quick start steps - Use ``code`` instead of `label` throughout; this is .rst not .md Differential Revision: https://reviews.llvm.org/D59600
  860. gn build: Let get.py keep zip file in memory instead of using a temp file The zip is small, and it's a bit less code this way. No intended behavior change. Differential Revision: https://reviews.llvm.org/D59677
  861. [MIPS GlobalISel] Add floating point register bank Add floating point register bank for MIPS32. Implement getRegBankFromRegClass for float register classes. Differential Revision: https://reviews.llvm.org/D59643
  862. [MIPS GlobalISel] Lower float and double arguments in registers Lower float and double arguments in registers for MIPS32. When float/double argument is passed through gpr registers select appropriate move instruction. Differential Revision: https://reviews.llvm.org/D59642
  863. [llvm-readobj] Separate `Symbol Version` dumpers into `LLVM style` and `GNU style` Summary: Currently, llvm-readobj can dump symbol version sections only in LLVM style. In this patch, I would like to separate these dumpers into GNU style and LLVM style for future implementation. Reviewers: grimar, jhenderson, mattd, rupprecht Reviewed By: jhenderson, rupprecht Subscribers: ormris, dyung, RKSimon, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59186
  864. Fix the build with GCC 4.8 after r356783
  865. [TTI] Move getIntrinsicCost to allow functions to be overridden. NFC Moving this to base class TargetTransformInfoImplCRTPBase allows static_cast to a subtarget so that calls to e.g. getMemcpyCost actually go the overridden functions. Differential revision: https://reviews.llvm.org/D59706
  866. [ARM GlobalISel] 64-bit memops should be aligned We currently use only VLDR/VSTR for all 64-bit loads/stores, so the memory operands must be word-aligned. Mark aligned operations as legal and narrow non-aligned ones to 32 bits. While we're here, also mark non-power-of-2 loads/stores as unsupported.
  867. [X86] Update some of the getMachineNode calls from X86ISelDAGToDAG to also include a VT for a EFLAGS result. This makes the nodes consistent with how they would be emitted from the isel table.
  868. [X86] When selecting (x << C1) op C2 as (x op (C2>>C1)) << C1, use the operation VT for the target constant. Normally when the nodes we use here(AND32ri8 for example) are selected their immediates are just converted from ConstantSDNode to TargetConstantSDNode without changing VT from the original operation VT. So we should still be emitting them with the operation VT. Theoretically this could expose more accurate opportunities for CSE.
  869. [X86] Remove GetLo8XForm and use GetLo32XForm instead. NFCI We were using this to create an AND32ri8 node from a 64-bit and, but that node normally still uses a 32-bit immediate. So we should just truncate the existing immediate to i32. We already verified it has the same value in bits 31:7.
  870. [X86] Remove a couple unused SDNodeXForms. NFC
  871. Revert r356688 "[X86] Don't avoid folding multiple use sign extended 8-bit immediate into instructions under optsize." Looking back over how the one use optimization works, I don't think this is the right way to fix this.
  872. [X86][SSE41] Start shuffle combining from ZERO_EXTEND_VECTOR_INREG (PR40685) Enable SSE41 ZERO_EXTEND_VECTOR_INREG shuffle combines - for the PMOVZX(PSHUFD(V)) -> UNPCKH(V,0) pattern we reduce the shuffles (port5-bottleneck on Intel) at the expense of creating a zero (pxor v,v) and an extra register move - which is a good trade off as these are pretty cheap and in most cases it doesn't increase register pressure. This also exposed a missed opportunity to use combine to ZERO_EXTEND_VECTOR_INREG with folded loads - even if we're in the float domain.
  873. [WebAssembly] Rename a variable in CFGSort (NFC) Class `RegionInfo` was `SortUnitInfo` before, so the variables were named `SUI`. Now the class name is `RegionInfo`, so this renames `SUI` to `RI`, matching the class name.
  874. [LegalizeDAG] Expand i16 bswap directly to a rotate by 8 instead of relying on DAG combine. An i16 bswap can be implemented with an i16 rotate by 8. We previously emitted a shift and OR sequence that DAG combine should be able to turn back into rotate. But we might as well go there directly. If rotate isn't legal, LegalizeDAG should further legalize it to either the opposite rotate, or the shift and OR pattern. I don't know of any way to get the existing DAG combine reliance to fail. So I don't know any way to add new tests for this that wouldn't have worked previously.
  875. [X86] Remove icmp undef from reduced tests Pre-commit for D59363 (Add icmp UNDEF handling to SelectionDAG::FoldSetCC) Approved by @spatel (Sanjay Patel)
  876. [X86][AVX] Start shuffle combining from ZERO_EXTEND_VECTOR_INREG (PR40685) Just enable this for AVX for now as SSE41 introduces extra register moves for the PMOVZX(PSHUFD(V)) -> UNPCKH(V,0) pattern (but otherwise helps reduce port5 usage on Intel targets). Only AVX support is required for PR40685 as the issue is due to 8i8->8i32 zext shuffle leftovers.
  877. [CGP] Make several static functions member functions (NFC) This is extracted from D59696 as suggested in the review. It is preparation for making the DominatorTree a member variable.
  878. Recommit r356738 "[llvm-objcopy] - Implement replaceSectionReferences for GroupSection class." Fix: r356853 + set AddressAlign to 4 in Inputs/compress-debug-sections.yaml for the new group section introduced. Original commit message: Currently, llvm-objcopy incorrectly handles compression and decompression of the sections from COMDAT groups, because we do not implement the replaceSectionReferences for this type of the sections. The patch does that. Differential revision: https://reviews.llvm.org/D59638
  879. [x86] improve the default expansion of uaddsat/usubsat This is yet another step towards solving PR14613: https://bugs.llvm.org/show_bug.cgi?id=14613 uaddsat X, Y --> (X >u (X + Y)) ? -1 : X + Y usubsat X, Y --> (X >u Y) ? X - Y : 0 We can't count on a sane vector ISA, so override the default (umin/umax) expansion of unsigned add/sub saturate in cases where we do not have umin/umax. Differential Revision: https://reviews.llvm.org/D59006
  880. [SLPVectorizer] shouldReorderOperands - just check for reordering. NFCI. Remove the I.getOperand() calls from inside shouldReorderOperands - reorderInputsAccordingToOpcode should handle the creation of the operand lists and shouldReorderOperands should just check to see whether the i'th element should be commuted.
  881. [llvm-objcopy] - Report SHT_GROUP sections with invalid alignment. This patch fixes the reason of ubsan failure (UB detected) happened after landing the D59638 (I had to revert it). http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-ubsan/builds/11760/steps/check-llvm%20ubsan/logs/stdio) Problem is the following. Our implementation of GroupSection assumes that its address is 4 bytes aligned when writes it: template <class ELFT> void ELFSectionWriter<ELFT>::visit(const GroupSection &Sec) { ELF::Elf32_Word *Buf = reinterpret_cast<ELF::Elf32_Word *>(Out.getBufferStart() + Sec.Offset); ... But the test case for D59638 did not set AddressAlign in YAML. So address was not 4 bytes aligned since Sec.Offset was odd. That triggered the issue. This patch teaches llvm-objcopy to report an error for such sections (which should not met in reality), what is better than having UB. Differential revision: https://reviews.llvm.org/D59695
  882. [ConstantRange] Add getFull() + getEmpty() named constructors; NFC This adds ConstantRange::getFull(BitWidth) and ConstantRange::getEmpty(BitWidth) named constructors as more readable alternatives to the current ConstantRange(BitWidth, /* full */ false) and similar. Additionally private getFull() and getEmpty() member functions are added which return a full/empty range with the same bit width -- these are commonly needed inside ConstantRange.cpp. The IsFullSet argument in the ConstantRange(BitWidth, IsFullSet) constructor is now mandatory for the few usages that still make use of it. Differential Revision: https://reviews.llvm.org/D59716
  883. gn build: Merge r356820
  884. gn build: Add build files for modularize and pp-trace Differential Revision: https://reviews.llvm.org/D59701
  885. Fix unused variable warning on non-asserts builds. NFCI.
  886. Remove unused function argument. NFCI.
  887. [DWARF] Delete a stray break and a stray comment. NFC
  888. [X86][SLP] Show example of failure to uniformly commute splats for 'alt' shuffles. If either the main/alt opcodes isn't commutable we may end up with the splats not correctly commuted to the same side.
  889. [x86] reduce code duplication; NFC
  890. [SLPVectorizer] reorderInputsAccordingToOpcode - use InstructionState directly. NFCI.
  891. [LowerSwitch] Use ConstantRange::fromKnownBits(); NFC Using an unsigned range to stay NFC, but a signed range would really be more useful here.
  892. [SLPVectorizer] Don't repeat VL.size() call. NFCI.
  893. [DebugInfo] follow up for "add SectionedAddress to DebugInfo interfaces" [Symbolizer] Add getModuleSectionIndexForAddress() helper routine The https://reviews.llvm.org/D58194 patch changed symbolizer interface. Particularily it requires not only Address but SectionIndex also. Note object::SectionedAddress parameter: Expected<DILineInfo> symbolizeCode(const std::string &ModuleName, object::SectionedAddress ModuleOffset, StringRef DWPName = ""); There are callers of symbolizer which do not know particular section index. That patch creates getModuleSectionIndexForAddress() routine which will detect section index for the specified address. Thus if caller set ModuleOffset.SectionIndex into object::SectionedAddress::UndefSection state then symbolizer would detect section index using getModuleSectionIndexForAddress routine. Differential Revision: https://reviews.llvm.org/D58848
  894. [gn] Add clang-tools-extra/clang-tidy/tool/BUILD.gn
  895. [gn] Add clang-tools-extra/clang-tidy/tool/BUILD.gn
  896. Disable MachO TBD write tests for Windows. The tests are failing on the windows bots. I am disabling them for now. This is a followup to r356820.
  897. [Legacy][TimePasses] allow -time-passes reporting into a custom stream As a followup to newpm -time-passes fix (D59366), now adding a similar functionality to legacy time-passes. Enhancing llvm::reportAndResetTimings to accept an optional stream for reporting output. By default it still reports into the stream created by CreateInfoOutputFile (-info-output-file). Also fixing to actually reset after printing as declared. Reviewed By: philip.pfaffe Differential Revision: https://reviews.llvm.org/D59416
  898. Followup for r356820 to fix the bots. Try using a move constructor instead.
  899. [TextAPI] TBD Reader/Writer Add basic infrastructure for reading and writting TBD files (version 1 - 3). The TextAPI library is not used by anything yet (besides the unit tests). Tool support will be added in a separate commit. The TBD format is currently documented in the implementation file (TextStub.cpp). https://reviews.llvm.org/D53945 Update: This contains changes to fix issues discovered by the bots: - add parentheses to silence warnings. - rename variables - use PlatformType from BinaryFormat - Trying if switching from a vector to an array will appeas the bots. - Replace the tuple with a struct to work around an explicit constructor bug. - This fixes an issue where we were leaking the YAML document if there was a parsing error. Updated the license information in all files.
  900. [SLP] Remove redundancy of performing operand reordering twice: once in buildTree() and later in vectorizeTree(). This is a refactoring patch that removes the redundancy of performing operand reordering twice, once in buildTree() and later in vectorizeTree(). To achieve this we need to keep track of the operands within the TreeEntry struct while building the tree, and later in vectorizeTree() we are just accessing them from the TreeEntry in the right order. This patch is the first in a series of patches that will allow for better operand reordering across chains of instructions (e.g., a chain of ADDs), as presented here: https://www.youtube.com/watch?v=gIEn34LvyNo Patch by: @vporpo (Vasileios Porpodas) Differential Revision: https://reviews.llvm.org/D59059
  901. [pdb] Add -type-stats and sort stats by descending size Summary: It prints this on chromium browser_tests.exe.pdb: Types Total: 5647475 entries ( 371,897,512 bytes, 65.85 avg) -------------------------------------------------------------------------- LF_CLASS: 397894 entries ( 119,537,780 bytes, 300.43 avg) LF_STRUCTURE: 236351 entries ( 83,208,084 bytes, 352.05 avg) LF_FIELDLIST: 291003 entries ( 66,087,920 bytes, 227.10 avg) LF_MFUNCTION: 1884176 entries ( 52,756,928 bytes, 28.00 avg) LF_POINTER: 1149030 entries ( 13,877,344 bytes, 12.08 avg) LF_ARGLIST: 789980 entries ( 12,436,752 bytes, 15.74 avg) LF_METHODLIST: 361498 entries ( 8,351,008 bytes, 23.10 avg) LF_ENUM: 16069 entries ( 6,108,340 bytes, 380.13 avg) LF_PROCEDURE: 269374 entries ( 4,309,984 bytes, 16.00 avg) LF_MODIFIER: 235602 entries ( 2,827,224 bytes, 12.00 avg) LF_UNION: 9131 entries ( 2,072,168 bytes, 226.94 avg) LF_VFTABLE: 323 entries ( 207,784 bytes, 643.29 avg) LF_ARRAY: 6639 entries ( 106,380 bytes, 16.02 avg) LF_VTSHAPE: 126 entries ( 6,472 bytes, 51.37 avg) LF_BITFIELD: 278 entries ( 3,336 bytes, 12.00 avg) LF_LABEL: 1 entries ( 8 bytes, 8.00 avg) The PDB is overall 1.9GB, so the LF_CLASS and LF_STRUCTURE declarations account for about 10% of the overall file size. I was surprised to find that on average LF_FIELDLIST records are short. Maybe this is because there are many more types with short member lists than there are instantiations with lots of members, like std::vector. Reviewers: aganea, zturner Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59672
  902. Revert "[llvm-readobj] Separate `Symbol Version` dumpers into `LLVM style` and `GNU style`" This reverts commit 94a0cffe250c1cd6b8fea5607be502cadf617bdc (r356764). This change was originally committed in r356764, but then partially reverted in r356777 due to "bad changes". This caused test failures because the test changes committed along with the original change were not reverted, so this change reverts the rest of the changes.
  903. [TargetLowering] SimplifyDemandedBits trunc(srl(x, C1)) - early out for out of range C1. NFCI.
  904. [ARM] Don't form "ands" when it isn't scheduled correctly. In r322972/r323136, the iteration here was changed to catch cases at the beginning of a basic block... but we accidentally deleted an important safety check. Restore that check to the way it was. Fixes https://bugs.llvm.org/show_bug.cgi?id=41116 Differential Revision: https://reviews.llvm.org/D59680
  905. [X86] Use xmm registers to implement 64-bit popcnt on 32-bit targets if possible if popcnt instruction is not available On 32-bit targets without popcnt, we currently expand 64-bit popcnt to sequences of arithmetic and logic ops for each 32-bit half and then add the 32 bit halves together. If we have xmm registers we can use use those to implement the operation instead. This results in less instructions then doing two separate 32-bit popcnt sequences. This mitigates some of PR41151 for the i64 on i686 case when we have SSE2. Differential Revision: https://reviews.llvm.org/D59662
  906. [X86] Use movq for i64 atomic load on 32-bit targets when sse2 is enable We used a lock cmpxchg8b to do i64 atomic loads. But if we have SSE2 we can do better and use a plain movq to do the load instead. I tried to just use an f64 atomic load and add isel patterns to MOVSD(which the domain fixing pass can turn to MOVQ), but the atomic_load SDNode in TargetSelectionDAG.td requires the type to be integer. So I've emitted VZEXT_LOAD instead which should be selected by isel to a MOVQ. Hopefully we don't need a specific atomic flavor of this. I kept the memory operand from the original AtomicSDNode. I wasn't sure if I might need to set the MOVolatile flag? I've left some FIXMEs for improvements we can do without SSE2. Differential Revision: https://reviews.llvm.org/D59679
  907. Fix non-determinism in Reassociate caused by address coincidences Summary: Between building the pair map and querying it there are a few places that erase and create Values. It's rare but the address of these newly created Values is occasionally the same as a just-erased Value that we already have in the pair map. These coincidences should be accounted for to avoid non-determinism. Thanks to Roman Tereshin for the test case. Reviewers: rtereshin, bogner Reviewed By: rtereshin Subscribers: mgrang, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59401
  908. [KnownBits] Add const to some methods. NFC Add "const" to the trunc, zext, sext and zextOrTrunc methods to make it clear that they aren't updating the object itself.
  909. [AArch64, ARM] Add support for Exynos M5 Add Exynos M5 support and test cases.
  910. [ARM] [NFC] Use tGPR in patterns where appropriate. This doesn't have any practical effect at the moment, as far as I know, because high registers aren't allocatable in Thumb1 mode. But it might matter in the future. Differential Revision: https://reviews.llvm.org/D59675
  911. [SLP] fix variables names in test; NFC 'tmpXXX' conflicts with the auto-generated script regex names. That could cause mask a bug or fail if the output changes.
  912. IR: Support parsing numeric block ids, and emit them in textual output. Just as as llvm IR supports explicitly specifying numeric value ids for instructions, and emits them by default in textual output, now do the same for blocks. This is a slightly incompatible change in the textual IR format. Previously, llvm would parse numeric labels as string names. E.g. define void @f() { br label %"55" 55: ret void } defined a label *named* "55", even without needing to be quoted, while the reference required quoting. Now, if you intend a block label which looks like a value number to be a name, you must quote it in the definition too (e.g. `"55":`). Previously, llvm would print nameless blocks only as a comment, and would omit it if there was no predecessor. This could cause confusion for readers of the IR, just as unnamed instructions did prior to the addition of "%5 = " syntax, back in 2008 (PR2480). Now, it will always print a label for an unnamed block, with the exception of the entry block. (IMO it may be better to print it for the entry-block as well. However, that requires updating many more tests.) Thus, the following is supported, and is the canonical printing: define i32 @f(i32, i32) { %3 = add i32 %0, %1 br label %4 4: ret i32 %3 } New test cases covering this behavior are added, and other tests updated as required. Differential Revision: https://reviews.llvm.org/D58548
  913. [X86] Regenerate powi tests to include i686 x87/sse targets
  914. [X86] Add PR13897 test case (i128 mul on i686)
  915. [ValueTracking] Avoid redundant known bits calculation in computeOverflowForSignedAdd() We're already computing the known bits of the operands here. If the known bits of the operands can determine the sign bit of the result, we'll already catch this in signedAddMayOverflow(). The only other way (and as the comment already indicates) we'll get new information from computing known bits on the whole add, is if there's an assumption on it. As such, we change the code to only compute known bits from assumptions, instead of computing full known bits on the add (which would unnecessarily recompute the known bits of the operands as well). Differential Revision: https://reviews.llvm.org/D59473
  916. [X86] lowerShuffleAsBitMask - ensure float bit masks are the correct width (PR41203)
  917. [AliasAnalysis] Second prototype to cache BasicAA / anyAA state. Summary: Adding contained caching to AliasAnalysis. BasicAA is currently the only one using it. AA changes: - This patch is pulling the caches from BasicAAResults to AAResults, meaning the getModRefInfo call benefits from the IsCapturedCache as well when in "batch mode". - All AAResultBase implementations add the QueryInfo member to all APIs. AAResults APIs maintain wrapper APIs such that all alias()/getModRefInfo call sites are unchanged. - AA now provides a BatchAAResults type as a wrapper to AAResults. It keeps the AAResults instance and a QueryInfo instantiated to batch mode. It delegates all work to the AAResults instance with the batched QueryInfo. More API wrappers may be needed in BatchAAResults; only the minimum needed is currently added. MemorySSA changes: - All walkers are now templated on the AA used (AliasAnalysis=AAResults or BatchAAResults). - At build time, we optimize uses; now we create a local walker (lives only as long as OptimizeUses does) using BatchAAResults. - All Walkers have an internal AA and only use that now, never the AA in MemorySSA. The Walkers receive the AA they will use when built. - The walker we use for queries after the build is instantiated on AliasAnalysis and is built after building MemorySSA and setting AA. - All static methods doing walking are now templated on AliasAnalysisType if they are used both during build and after. If used only during build, the method now only takes a BatchAAResults. If used only after build, the method now takes an AliasAnalysis. Subscribers: sanjoy, arsenm, jvesely, nhaehnle, jlebar, george.burgess.iv, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59315
  918. [Tests] Add masked.gather tests for non-constant masks + speculation possibilities
  919. [ConstantFolding] Fix GetConstantFoldFPValue to avoid cast overflow. Summary: In C++, the behavior of casting a double value that is beyond the range of a single precision floating-point to a float value is undefined. This change replaces such a cast with APFloat::convert to convert the value, which is consistent with how we convert a double value to a half value. Reviewers: sanjoy Subscribers: lebedev.ri, sanjoy, jlebar, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59500
  920. Make clang-move use same file naming convention as other tools In all the other clang-foo tools, the main library file is called Foo.cpp and the file in the tool/ folder is called ClangFoo.cpp. Do this for clang-move too. No intended behavior change. Differential Revision: https://reviews.llvm.org/D59700
  921. [tests] Add a generic masked.gather test to show sometimes we can't transform
  922. [tests] Add tests for converting masked.load to load speculatively
  923. [llvm-readobj] Revert bad changes
  924. [Tests] Use valid alignment in masked.gather tests
  925. gn build: Merge r356750
  926. gn build: Merge r356570
  927. gn build: Merge r356662
  928. gn build: Merge r356692
  929. InstCombineSimplifyDemanded: Allow v3 results for AMDGCN buffer and image intrinsics This helps to avoid the situation where RA spots that only 3 of the v4f32 result of a load are used, and immediately reallocates the 4th register for something else, requiring a stall waiting for the load. Differential Revision: https://reviews.llvm.org/D58906 Change-Id: I947661edfd5715f62361a02b100f14aeeada29aa
  930. gn build: Merge r356753
  931. gn build: Merge r356652 (and follow-up r56655)
  932. gn build: Merge r356729
  933. [llvm-readobj] Separate `Symbol Version` dumpers into `LLVM style` and `GNU style` Summary: Currently, llvm-readobj can dump symbol version sections only in LLVM style. In this patch, I would like to separate these dumpers into GNU style and LLVM style for future implementation. Reviewers: grimar, jhenderson, mattd, rupprecht Reviewed By: rupprecht Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59186
  934. [x86] auto-generate complete test checks; NFC
  935. [x86] auto-generate complete test checks; NFC
  936. [x86] add 'nounwind' to tests to reduce noise; NFC
  937. [x86] auto-generate complete checks for test; NFC
  938. [AMDGPU] Use three- and five-dword result type in image ops Some image ops return three or five dwords. Previously, we modeled that with a 4 or 8 dword register class. The register allocator could cleverly spot that some subregs were dead and allocate something else there, but that caused the de-optimization that waitcnt insertion would think that the result was used immediately. This commit allows such an image op to have a result with a three or five dword result, avoiding the above de-optimization. Differential Revision: https://reviews.llvm.org/D58905 Change-Id: I3651211bbd7ed22721ee7b9fefd7bcc60a809d8b
  939. [AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics Now we have vec3 MVTs, this commit implements dwordx3 variants of the buffer intrinsics. On gfx6, a dwordx3 buffer load intrinsic is implemented as a dwordx4 instruction, and a dwordx3 buffer store intrinsic is not supported. We need to support the dwordx3 load intrinsic because it is generated by subtarget-unaware code in InstCombine. Differential Revision: https://reviews.llvm.org/D58904 Change-Id: I016729d8557b98a52f529638ae97c340a5922a4e
  940. [SLPVectorizer] Add test related to SLP Throttling support, NFCI.
  941. [ObjectYAML] Add basic minidump generation support Summary: This patch adds the ability to read a yaml form of a minidump file and write it out as binary. Apart from the minidump header and the stream directory, only three basic stream kinds are supported: - Text: This kind is used for streams which contain textual data. This is typically the contents of a /proc file on linux (e.g. /proc/PID/maps). In this case, we just put the raw stream contents into the yaml. - SystemInfo: This stream contains various bits of information about the host system in binary form. We expose the data in a structured form. - Raw: This kind is used as a fallback when we don't have any special knowledge about the stream. In this case, we just print the stream contents in hex. For this code to be really useful, more stream kinds will need to be added (particularly for things like lists of memory regions and loaded modules). However, these can be added incrementally. Reviewers: jhenderson, zturner, clayborg, aprantl Subscribers: mgorny, lemo, llvm-commits, lldb-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59482
  942. [llvm-exegesis] Fix compilation before c++17. ClusteringTest.cpp:25:23: error: constexpr variable cannot have non-literal type 'const llvm::exegesis::(anonymous namespace)::(lambda at /home/buildslave/ps4-buildslave4/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/llvm.src/unittests/tools/llvm-exegesis/ClusteringTest.cpp:25:35)' static constexpr auto HasPoints = [](const std::vector<int> &Indices) {
  943. [llvm-exegesis] Add clustering test. Summary: To show that dbscan is insensitive to the order of the points. Subscribers: tschuett, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59693
  944. [llvm-objcopy]Add coverage for --split-dwo and --output-format Also fix up a couple of minor issues in the test being updated, where FileCheck could match on incorrect output and fix the test case order to match the struct order. Reviewed by: grimar Differential Revision: https://reviews.llvm.org/D59691
  945. Revert r356738 "[llvm-objcopy] - Implement replaceSectionReferences for GroupSection class." Seems this broke ubsan bot: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-ubsan/builds/11760
  946. [RISCV] Add basic RV32E definitions and MC layer support The RISC-V ISA defines RV32E as an alternative "base" instruction set encoding, that differs from RV32I by having only 16 rather than 32 registers. This patch adds basic definitions for RV32E as well as MC layer support (assembling, disassembling) and tests. The only supported ABI on RV32E is ILP32E. Add a new RISCVFeatures::validate() helper to RISCVUtils which can be called from codegen or MC layer libraries to validate the combination of TargetTriple and FeatureBitSet. Other targets have similar checks (e.g. erroring if SPE is enabled on PPC64 or oddspreg + o32 ABI on Mips), but they either duplicate the checks (Mips), or fail to check for both codegen and MC codepaths (PPC). Codegen for the ILP32E ABI support and RV32E codegen are left for a future patch/patches. Differential Revision: https://reviews.llvm.org/D59470
  947. [RISCV] Optimize emission of SELECT sequences This patch optimizes the emission of a sequence of SELECTs with the same condition, avoiding the insertion of unnecessary control flow. Such a sequence often occurs when a SELECT of values wider than XLEN is legalized into two SELECTs with legal types. We have identified several use cases where the SELECTs could be interleaved with other instructions. Therefore, we extend the sequence to include non-SELECT instructions if we are able to detect that the non-SELECT instructions do not impact the optimization. This patch supersedes https://reviews.llvm.org/D59096, which attempted to address this issue by introducing a new SelectionDAG node. Hat tip to Eli Friedman for his feedback on how to best handle this issue. Differential Revision: https://reviews.llvm.org/D59355 Patch by Luís Marques.
  948. [RISCV] Allow conversion of CC logic to bitwise logic Indicates in the TargetLowering interface that conversions from CC logic to bitwise logic are allowed. Adds tests that show the benefit when optimization opportunities are detected. Also adds tests that show that when the optimization is not applied correct code is generated (but opportunities for other optimizations remain). Differential Revision: https://reviews.llvm.org/D59596 Patch by Luís Marques.
  949. [llvm-objcopy] - Fix a st_name of the first symbol table entry. Spec says about the first symbol table entry that index 0 both designates the first entry in the table and serves as the undefined symbol index. It should have zero value. Hence the first symbol table entry has no name. And so has to have a st_name == 0. (http://refspecs.linuxbase.org/elf/gabi4+/ch4.symtab.html) Currently, we do not emit zero value for the first symbol table entry. That happens because we add empty strings to the string builder, which for each such case adds a zero byte: (https://github.com/llvm-mirror/llvm/blob/master/lib/MC/StringTableBuilder.cpp#L185) After the string optimization performed it might return non zero indexes for the empty string requested. The patch fixes this issue for the case above and other sections with no names. Differential revision: https://reviews.llvm.org/D59496
  950. [llvm-objcopy] - Implement replaceSectionReferences for GroupSection class. Currently, llvm-objcopy incorrectly handles compression and decompression of the sections from COMDAT groups, because we do not implement the replaceSectionReferences for this type of the sections. The patch does that. Differential revision: https://reviews.llvm.org/D59638
  951. [llvm-objcopy]Add support for *-freebsd output formats GNU objcopy can support output formats like elf32-i386-freebsd and elf64-x86-64-freebsd. The only difference from their regular non-freebsd counterparts that I have observed is that the freebsd versions set the OS/ABI field to ELFOSABI_FREEBSD. This patch sets the OS/ABI field according based on the format whenever --output-format is specified. Reviewed by: rupprecht, grimar Differential Revision: https://reviews.llvm.org/D59645
  952. [RISCV][NFC] Add test case to MC/RISCV/linker-relaxation.s showing incorrect relocations being emitted A follow-up patch will fix this case.
  953. [AMDGPU] Added v5i32 and v5f32 register classes They are not used by anything yet, but a subsequent commit will start using them for image ops that return 5 dwords. Differential Revision: https://reviews.llvm.org/D58903 Change-Id: I63e1904081e39a6d66e4eb96d51df25ad399d271
  954. [RISCV][NFC] Expand test/MC/RISCV/linker-relaxation.s tests Add more complete CHECK lines for the relocations generated when relaxation is enabled, and add cases where a locally defined symbol is referenced. Two instances of pcrel_lo(defined_symbol) are commented out, as they will produce an error. A follow-up patch will fix this.
  955. [X86] Add 32-bit command lines with and without SSE2 to atomic-non-integer.ll. NFC
  956. [BPF] fix flaky btf unit test static-var-derived-type.ll The DataSecEentries is defined as an unordered_map since order does not really matter. std::unordered_map<std::string, std::unique_ptr<BTFKindDataSec>> DataSecEntries; This seems causing the test static-var-derived-type.ll flaky as two sections ".bss" and ".readonly" have undeterministic ordering when performing map iterating, which decides the output assembly code sequence of BTF_KIND_DATASEC entries. Fix the test to have only one data section to remove flakiness. Signed-off-by: Yonghong Song <yhs@fb.com>
  957. [DWARF] Refactor RelocVisitor and fix computation of SHT_RELA-typed relocation entries Summary: getRelocatedValue may compute incorrect value for SHT_RELA-typed relocation entries. // DWARFDataExtractor.cpp uint64_t DWARFDataExtractor::getRelocatedValue(uint32_t Size, uint32_t *Off, ... // This formula is correct for REL, but may be incorrect for RELA if the value // stored in the location (getUnsigned(Off, Size)) is not zero. return getUnsigned(Off, Size) + Rel->Value; In this patch, we * refactor these visit* functions to include a new parameter `uint64_t A`. Since these visit* functions are no longer used as visitors, rename them to resolve*. + REL: A is used as the addend. A is the value stored in the location where the relocation applies: getUnsigned(Off, Size) + RELA: The addend encoded in RelocationRef is used, e.g. getELFAddend(R) * and add another set of supports* functions to check if a given relocation type is handled. DWARFObjInMemory uses them to fail early. Reviewers: echristo, dblaikie Reviewed By: echristo Subscribers: mgorny, aprantl, aheejin, fedor.sergeev, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57939
  958. [BPF] handle derived type properly for computing type id Currently, the type id for a derived type is computed incorrectly. For example, type #1: int type #2: ptr to #1 For a global variable "int *a", type #1 will be attributed to variable "a". This is due to a bug which assigns the type id of the basetype of that derived type as the derived type's type id. This happens to "const", "volatile", "restrict", "typedef" and "pointer" types. This patch fixed this bug, fixed existing test cases and added a new one focusing on pointers plus other derived types. Signed-off-by: Yonghong Song <yhs@fb.com>
  959. [X86] Autogenerate complete checks. NFC
  960. [AArch64] Split the neon.addp intrinsic into integer and fp variants. This is the result of discussions on the list about how to deal with intrinsics which require codegen to disambiguate them via only the integer/fp overloads. It causes problems for GlobalISel as some of that information is lost during translation, while with other operations like IR instructions the information is encoded into the instruction opcode. This patch changes clang to emit the new faddp intrinsic if the vector operands to the builtin have FP element types. LLVM IR AutoUpgrade has been taught to upgrade existing calls to aarch64.neon.addp with fp vector arguments, and we remove the workarounds introduced for GlobalISel in r355865. This is a more permanent solution to PR40968. Differential Revision: https://reviews.llvm.org/D59655
  961. [X86] Use LoadInst->getType() instead of LoadInst->getPointerOperandType()->getElementType(). NFCI For the future day when the pointer's don't have element types, we shoudl just use the type of the load result instead.
  962. [InstSimplify] Add tests for signed icmp of and/or; NFC Even if a signed predicate is used, the ranges computed for and/or are unsigned, resulting in missed simplifications.
  963. [Object] Fix reading objects created with -fembed-bitcode-marker Currently, this fails with many tools, e.g. $ clang -fembed-bitcode-marker -c -o test.o test.c $ nm test.o nm: test.o The file was not recognized as a valid object file -fembed-bitcode-marker creates a LLVM,bitcode section consisting of a single byte. When reading the object file, IRObjectFile::findBitcodeInObject succeeds, causing SymbolicFile::createSymbolicFile to try to read the "bitcode" rather than using the outer Mach-O data - when then fails. Fix this by making findBitcodeInObject return an error if the section size <= 1. Patched by: Nicholas Allegra Differential Revision: https://reviews.llvm.org/D44373
  964. Mips: Fix typo in assert message
  965. Mips: Don't create copy of nothing This was creating a copy of the register the pseudo itself was def'ing, leaving a copy of an undefined register. I'm not sure how the verifier is not catching this, but this avoids asserting in a future change to RegAllocFast
  966. GlobalISel: Fix RegBankSelect for REG_SEQUENCE The AArch64 test was broken since the result register already had a set register class, so this test was a no-op. The mapping verify call would fail because the result size is not the same as the inputs like in a copy or phi. The AMDGPU testcases are half broken and introduce illegal VGPR->SGPR copies which need much more work to handle correctly (same for phis), but add them as a baseline.
  967. Don't add a tail keyword to calls to ObjC runtime functions if the calls are annotated with notail. r356705 annotated calls to objc_retainAutoreleasedReturnValue with notail on x86-64. This commit teaches ARC optimizer to check the notail marker on the call before turning it into a tail call. rdar://problem/38675807
  968. [AArch64] Update for Exynos Fix the feature set for Exynos M4 by removing support for `+fp16fml` and fix test case.
  969. [llvm-objdump] Support arg grouping for -j and -M (e.g. llvm-objdump -sj.foo -dMreg-names-raw) Summary: r354375 added support for most objdump groupings, but didn't add support for -j|--sections, because that wasn't possible. r354870 added --disassembler options, but grouping still wasn't available. r355185 supported values for grouped options. This just puts the three of them together. This supports -j in modes like `-s -j .foo`, `-sj .foo`, `-sj=.foo`, or `-sj.foo`, and similar for `-M`. Reviewers: ormris, jhenderson, ikudrin Reviewed By: jhenderson, ikudrin Subscribers: javed.absar, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59618
  970. [X86] canonicalizeBitSelect - don't attempt to canonicalize mask registers We don't use X86ISD::ANDNP for mask registers. Test case from @craig.topper (Craig Topper)
  971. [llvm-pdbutil] Add -type-ref-stats to help find unused type info Summary: This considers module symbol streams and the global symbol stream to be roots. Most types that this considers "unreferenced" are referenced by LF_UDT_MOD_SRC_LINE id records, which VC seems to always include. Essentially, they are types that the user can only find in the debugger if they call them by name, they cannot be found by traversing a symbol. In practice, around 80% of type information in a PDB is referenced by a symbol. That seems like a reasonable number. I don't really plan to do anything with this tool. It mostly just exists for informational purposes, and to confirm that we probably don't need to implement type reference tracking in LLD. We can continue to merge all types as we do today without wasting space. Reviewers: zturner, aganea Subscribers: mgorny, hiraditya, arphaman, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59620
  972. [x86] add tests with movmsk potential (PR39665); NFC
  973. [InstCombine] Don't transform ((C1 OP zext(X)) & C2) -> zext((C1 OP X) & C2) if either zext or OP has another use. If they have other users we'll just end up increasing the instruction count. We might be able to weaken this to only one of them having a single use if we can prove that the and will be removed. Fixes PR41164. Differential Revision: https://reviews.llvm.org/D59630
  974. [X86] Don't avoid folding multiple use sign extended 8-bit immediate into instructions under optsize. Under optsize we try to avoid folding immediates into instructions under optsize. But if the immediate is 16-bits or 32 bits, but can be encoded as an 8-bit immediate we don't save enough from disabling the folding unless the immediate has enough uses to make up for the size of the move which is either 3 bytes or 5 bytes since there are no sign extended 8-bit moves. We would also save something if the immediate was a live out of the basic block and thus a move was unavoidable, but that would require a more advanced heuristic than just counting uses. Note we only avoid folding multiple use immediates into the patterns that use X86ISD::ADD/SUB/XOR/OR/AND/CMP/ADC/SBB nodes and not the more common ISD::ADD/SUB/XOR/OR/AND nodes. Differential Revision: https://reviews.llvm.org/D59522
  975. [ScalarizeMaskedMemIntrin] Add support for scalarizing expandload and compressstore intrinsics. This adds support for scalarizing these intrinsics as well the X86TargetTransformInfo support to avoid scalarizing them in the cases X86 can handle. I've omitted handling special cases for constant masks for this first pass. Though CodeGenPrepare can constant fold the branch conditions and remove some of the control flow anyway. Fixes PR40994 and is covers most of PR3666. Might want to implement constant masks to close that. Differential Revision: https://reviews.llvm.org/D59180
  976. [ValueTracking] Use ConstantRange based overflow check for signed sub This is D59450, but for signed sub. This case is not NFC, because the overflow logic in ConstantRange is more powerful than the existing check. This resolves the TODO in the function. I've added two tests to show that this indeed catches more cases than the previous logic, but the main correctness test coverage here is in the existing ConstantRange unit tests. Differential Revision: https://reviews.llvm.org/D59617
  977. Add more rotate tests, including ORs of rotates This is a part of https://reviews.llvm.org/D47735.
  978. Fixup opt-remarks.ll gold plugin test. NFC Now that rL356594 has added a TailCallElim pass to LTO, the call gets marked as tail.
  979. [DAGCombiner] Use getTokenFactor in a few more cases. SDNodes can only have 64k operands and for some inputs (e.g. large number of stores), we can reach this limit when creating TokenFactor nodes. This patch is a follow up to D56740 and updates a few more places that potentially can create TokenFactors with too many operands. Reviewers: efriedma, craig.topper, aemerson, RKSimon Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D59156
  980. [DAGCombine] SimplifySelectCC - call FoldSetCC with the setcc result type We were calling FoldSetCC with the compare operand type instead of the result type. Found by OSS-Fuzz #13838 (https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=13838)
  981. [CodeGenPrepare] limit formation of overflow intrinsics (PR41129) This is probably a bigger limitation than necessary, but since we don't have any evidence yet that this transform led to real-world perf improvements rather than regressions, I'm making a quick, blunt fix. In the motivating x86 example from: https://bugs.llvm.org/show_bug.cgi?id=41129 ...and shown in the regression test, we want to avoid an extra instruction in the dominating block because that could be costly. The x86 LSR test diff is reversing the changes from D57789. There's no evidence that 1 version is any better than the other yet. Differential Revision: https://reviews.llvm.org/D59602
  982. [llvm-readobj] Format codes. NFC.
  983. [Thumb] Fix infinite loop in ABS expansion (PR41160) Don't expand ISD::ABS node if its legal.
  984. [AMDGPU] Support for v3i32/v3f32 Added support for dwordx3 for most load/store types, but not DS, and not intrinsics yet. SI (gfx6) does not have dwordx3 instructions, so they are not enabled there. Some of this patch is from Matt Arsenault, also of AMD. Differential Revision: https://reviews.llvm.org/D58902 Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9
  985. Fix -Wmisleading-indentation gcc7 warning. NFCI.
  986. [AArch64] Allow -mattr=tpidr-el[1|2|3] Added subtarget features for AArch64 to use TPIDR_EL[1|2|3] as the TLS base register, rather than the default TPIDR_EL0. Patch by Philip Derrin! Differential revision: https://reviews.llvm.org/D54685
  987. [SelectionDAG] Add scalarization of ABS node (PR41149) Patch by: @ikulagin (Ivan Kulagin) Differential Revision: https://reviews.llvm.org/D59577
  988. Fix two more issues with r356652 The first problem was a use-after-free in the tests (detected by asan bots). The temporary array created for the "create" call is guaranteed to live only until the end of the statement. The fix there is to store the test data in a local variable to ensure it has the right lifetime The second issue is broken BUILD_SHARED_LIBS build, which I fix by adding the appropriate BinaryFormat dependency to the Object unit tests.
  989. [RISCV][NFC] Remove old CHECK lines from linker-relaxation.s test The RELOC: check lines are no longer used.
  990. Attempt to fix modules build for r356652 The commit added a new .def file. This adds it to the list of textual headers.
  991. [Object] Add basic minidump support Summary: This patch adds basic support for reading minidump files. It contains the definitions of various important minidump data structures (header, stream directory), and of one minidump stream (SystemInfo). The ability to read other streams will be added in follow-up patches. However, all streams can be read even now as raw data, which means lldb's minidump support (where this code is taken from) can be immediately rebased on top of this patch as soon as it lands. As we don't have any support for generating minidump files (yet), this tests the code via unit tests with some small handcrafted binaries in the form of c char arrays. Reviewers: Bigcheese, jhenderson, zturner Subscribers: srhines, dschuff, mgorny, fedor.sergeev, lemo, clayborg, JDevlieghere, aprantl, lldb-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59291
  992. [BasicAA] Use DenseMap::try_emplace after D59151. NFC
  993. Silence warning about unused variable in builds without asserts [NFC]
  994. [ScalarizeMaskedMemIntrinsics] Reverse some if conditions to reduce indentations to remove curly braces. Pre-commit for D59180
  995. [InstCombine] Add test case for PR41164. NFC
  996. [BasicAA] Reduce no of map seaches [NFCI]. Summary: This is a refactoring patch. - Reduce the number of map searches by reusing the iterator. - Add asserts to check that the entry is in the cache, as this is something BasicAA relies on to avoid infinite recursion. Reviewers: chandlerc, aschwaighofer Subscribers: sanjoy, jlebar, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59151
  997. [instcombine] Add some todos, and arrange code for readibility
  998. [MSSA] Delete move ctor; remove dynamic never-moved verification Code archaeology in D59315 revealed that MSSA should never be moved. Rather than trying to check dynamically that this hasn't happened in the verify() functions of Walkers, it's likely best to just delete its move constructor. Since all these verify() functions did is check that MSSA hasn't moved, this allows us to remove these verify functions. I can readd the verification checks if someone's super concerned about us trying to `memcpy` MemorySSA or something somewhere, but I imagine we have other problems if we're trying anything like that...
  999. [X86] Add CMPXCHG8B feature flag. Set it for all CPUs except i386/i486 including 'generic'. Disable use of CMPXCHG8B when this flag isn't set. CMPXCHG8B was introduced on i586/pentium generation. If its not enabled, limit the atomic width to 32 bits so the AtomicExpandPass will expand to lib calls. Unclear if we should be using a different limit for other configs. The default is 1024 and experimentation shows that using an i256 atomic will cause a crash in SelectionDAG. Differential Revision: https://reviews.llvm.org/D59576
  1000. Fix Mach-O bind and rebase validation errors in libObject Summary: llvm-objdump (via libObject) validates DYLD_INFO rebase and bind entries against the basic structure found in the Mach-O file before evaluating the contents of those entries. Certain malformed Mach-Os can defeat the validation check and force llvm-objdump (libObject) to crash. The previous logic verified a rebase or bind started in a valid Mach-O section, but did not verify that the section wholely contained the fixup. It also generally allows rebases or binds to start immediately after a valid section even if that range is not itself part of a valid section. Finally, bind and rebase opcodes that indicate more than one fixup (apply N times...) are not completely validated: only the first and final fixups are checked. The previous logic also rejected certain binaries as false positives. Some bind and rebase opcodes can modify the state machine such that the next bind or rebase will fail. libObject will reject these opcodes as invalid in order to be helpful and print an error message associated with the instruction that caused the problem, even though the binary is not actually illegal until it consumes the invalid state in the state machine. In other words, libObject may reject a Mach-O binary that Apple's dynamic linker may consider legal. The original version of macho-rebase-add-addr-uleb-too-big is an example of such a binary. I have replaced the existing checkSegAndOffset and checkCountAndSkip functions with a single function, checkSegAndOffsets, which validates all of the fixups realized by a DYLD_INFO opcode. checkSegAndOffsets verifies that a Mach-O section fully contains each fixup. Every fixup realized by an opcode is validated, and some (but not all!) inconsistencies in the state machine are allowed until a fixup is realized. This means that libObject may fail on an opcode that realizes a fixup, not on the opcode that introduced the arithmetic error. Existing test cases have been modified to reflect the changes in error messages returned by libObject. What's more, the test case for macho-rebase-add-addr-uleb-too-big has been modified so that it actually triggers the error condition; the new code in libObject considers the original test binary "legal". rdar://47797757 Reviewers: lhames, pete, ab Reviewed By: pete Subscribers: rupprecht, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59574
  1001. [WebAssembly][NFC] Fix formatting error from rL356610
  1002. [AMDGPU] Do not generate spurious PAL metadata My previous fix rL356591 "[AMDGPU] Added MsgPack format PAL metadata" accidentally caused a spurious PAL metadata .note record to be emitted for any AMDGPU output. That caused failures in the lld test amdgpu-relocs.s. Fixed. Differential Revision: https://reviews.llvm.org/D59613 Change-Id: Ie04a2aaae890dcd490f22c89edf9913a77ce070e
  1003. [InstCombine] Add additional sub nsw inference tests; NFC nsw can be determined based on known bits here, but currently isn't.
  1004. Allow machine dce to remove uses in the same instruction Machine DCE cannot remove a dead definition if there are non-dbg uses. A use however can be in the same instruction: dead %0 = INST %0 Such instructions sometimes created by Detect dead lanes pass. Allow this instruction to be deleted despite the use if the only use belongs to the same instruction. Differential Revision: https://reviews.llvm.org/D59565
  1005. [X86] Call lowerShuffleAsBitMask for 512-bit vectors in lowerShuffleAsBlend. This patch enables the use of lowerShuffleAsBitMask for 512-bit blends before falling back to move immedate, GPR to k-register, and masked op. I had to make some changes to support v8i64 when i64 is not a legal type. And to support floating point types. This trades a load for the move immediate and GPR move which is higher latency. But its probably better for register pressure not having to hop through other register classes. The load+and should play better with LICM and rematerialization I think. Differential Revision: https://reviews.llvm.org/D59479
  1006. [AMDGPU] Fix dependency on `BinaryFormat` Summary: - The linking is broken when this library is built as shared one. Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59610
  1007. AMDGPU: Don't look for constant in insert/extract_vector_elt regbankselect The constantness shouldn't change the register bank choice. We also don't need to restrict this to only indexing VGPRs, since it's possible to index SGPRs (but SelectionDAG made using this difficult). Allow directly indexing SGPRs when appropriate.
  1008. [WebAssembly] Target features section Summary: Implements a new target features section in assembly and object files that records what features are used, required, and disallowed in WebAssembly objects. The linker uses this information to ensure that all objects participating in a link are feature-compatible and records the set of used features in the output binary for use by optimizers and other tools later in the toolchain. The "atomics" feature is always required or disallowed to prevent linking code with stripped atomics into multithreaded binaries. Other features are marked used if they are enabled globally or on any function in a module. Future CLs will add linker flags for ignoring feature compatibility checks and for specifying the set of allowed features, implement using the presence of the "atomics" feature to control the type of memory and segments in the linked binary, and add front-end flags for relaxing the linkage policy for atomics. Reviewers: aheejin, sbc100, dschuff Subscribers: jgravelle-google, hiraditya, sunfish, mgrang, jfb, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59173
  1009. [AMDGPU] Fix clamp bit DAG operand Summary: - Should use `targetconstant` instead of `constant` operand for clamp bit, which is expected as an immediate operand. Under certain conditions, such as a common `i1 false` constant is used in other place and selected before the instruction with clamp bit, register operand may be added instead of immediate one. Use `targetcosntant` to enforce that. Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59608
  1010. [ARC] Add ARCOptAddrMode pass to generate postincrement loads/stores. Build on newly introduced ARC postincrement loads/stores from r356200. Patch By Denis Antrushin! <denis@synopsys.com> Differential Revision: https://reviews.llvm.org/D59409
  1011. [AArch64] Fix formatting (NFC) Indent macro instances properly.
  1012. AMDHSA: Fix COMPUTE_PGM_RSRC2.USER_SGPR calculation when parsing ISA assembly It must match https://llvm.org/docs/AMDGPUUsage.html#initial-kernel-execution-state Differential Revision: https://reviews.llvm.org/D59570
  1013. [ARM] Eliminate redundant "mov rN, sp" instructions in Thumb1. This takes sequences like "mov r4, sp; str r0, [r4]", and optimizes them to something like "str r0, [sp]". For regular stack variables, this optimization was already implemented: we lower loads and stores using frame indexes, which are expanded later. However, when constructing a call frame for a call with more than four arguments, the existing optimization doesn't apply. We need to use stores which are actually relative to the current value of sp, and don't have an associated frame index. This patch adds a special case to handle that construct. At the DAG level, this is an ISD::STORE where the address is a CopyFromReg from SP (plus a small constant offset). This applies only to Thumb1: in Thumb2 or ARM mode, a regular store instruction can access SP directly, so the COPY gets eliminated by existing code. The change to ARMDAGToDAGISel::SelectThumbAddrModeSP is a related cleanup: we shouldn't pretend that it can select anything other than frame indexes. Differential Revision: https://reviews.llvm.org/D59568
  1014. [Linker] Fix crash handling appending linkage Summary: When linking two llvm.used arrays, if the resulting merged array ends up with duplicated elements (with the same name) but with different types, the IRLinker was crashing. This was supposed to be legal, as the IRLinker bitcasts elements to match types in these situations. This bug was exposed by D56928 in clang to support attribute used in member functions of class templates. Crash happened when self-hosting with LTO. Since LLVM depends on attribute used to generate code for the dump() method, ubiquitous in the code base, many input bc had a definition of this method referenced in their llvm.used array. Some of these classes got optimized, changing the type of the first parameter (this) in the dump method, leading to a scenario with a pool of valid definitions but some with a different type, triggering this bug. This is a memory bug: ValueMapper depends on (calls) the materializer provided by IRLinker, and this materializer was freely calling RAUW methods whenever a global definition was updated in the temporary merged output file. However, replaceAllUsesWith may or may not destroy constants that use this global. If the linked definition has a type mismatch regarding the new def and the old def, the materializer would bitcast the old type to the new type and the elements of the llvm.used array, which already uses bitcast to i8*, would end up with elements cascading two bitcasts. RAUW would then indirectly call the constantfolder to update the constant to the new ref, which would, instead of updating the constant, destroy it to be able to create a new constant that folds the two bitcasts into one. The problem is that ValueMapper works with pointers to the same constants that may be getting destroyed by RAUW. Obviously, RAUW can update references in the Module to do not use the old destroyed constant, but it can't update ValueMapper's internal pointers to these constants, which are now invalid. The approach here is to move the task of RAUWing old definitions outside of the materializer. Test Plan: Added LIT test case, tested clang self-hosting with D56928 and verified it works Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D59552
  1015. [NFC] Fix brace indentation.
  1016. Resubmit r356511 "[TailCallElim] Add tailcall elimination pass to LTO pipelines" Failing LLD tests have been fixed in r356593.
  1017. [AMDGPU] Added MsgPack format PAL metadata Summary: PAL metadata now supports both the old linear reg=val pairs format and the new MsgPack format. The MsgPack format uses YAML as its textual representation. On output to YAML, a mnemonic name is provided for some hardware registers. Differential Revision: https://reviews.llvm.org/D57028 Change-Id: I2bbaabaaca4b3574f7e03b80fbef7c7a69d06a94
  1018. Simplify operands of masked stores and scatters based on demanded elements If we know we're not storing a lane, we don't need to compute the lane. This could be improved by using the undef element result to further prune the mask, but I want to separate that into its own change since it's relatively likely to expose other problems. Differential Revision: https://reviews.llvm.org/D57247
  1019. [LICM & MemorySSA] Don't sink/hoist stores in the presence of ordered loads. Summary: Before this patch, if any Use existed in the loop, with a defining access in the loop, we conservatively decide to not move the store. What this approach was missing, is that ordered loads are not Uses, they're Defs in MemorySSA. So, even when the clobbering walker does not find that volatile load to interfere, we still cannot hoist a store past a volatile load. Resolves PR41140. Reviewers: george.burgess.iv Subscribers: sanjoy, jlebar, Prazek, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59564
  1020. [ValueTracking] Compute range for abs without nsw This is a small followup to D59511. The code that was moved into computeConstantRange() there is a bit overly conversative: If the abs is not nsw, it does not compute any range. However, abs without nsw still has a well-defined contiguous unsigned range from 0 to SIGNED_MIN. This is a lot less useful than the usual 0 to SIGNED_MAX range, but if we're already here we might as well specify it... Differential Revision: https://reviews.llvm.org/D59563
  1021. [InstCombine] Fold add nuw + uadd.with.overflow Fold add nuw and uadd.with.overflow with constants if the addition does not overflow. Part of https://bugs.llvm.org/show_bug.cgi?id=38146. Patch by Dan Robertson. Differential Revision: https://reviews.llvm.org/D59471
  1022. [Remarks] Fix mismatched delete due to missing virtual destructor This fixes an asan failure introduced in r356519.
  1023. [AMDGPU] Factored PAL metadata handling out into its own class Summary: This commit introduces a new AMDGPUPALMetadata class that: * is inside the AMDGPU target; * keeps an in-memory representation of PAL metadata; * provides a method to read the frontend-supplied metadata from LLVM IR; * provides methods for the asm printer to set metadata items; * provides methods to write the metadata as a binary blob to put in a .note record or as an asm directive; * provides a method to read the metadata as a binary blob from a .note record. Because llvm-readobj cannot call directly into a target, I had to remove llvm-readobj's ability to dump PAL metadata, pending a resolution to https://reviews.llvm.org/D52821 Differential Revision: https://reviews.llvm.org/D57027 Change-Id: I756dc830894fcb6850324cdcfa87c0120eb2cf64
  1024. Remove HAVE_REALPATH from config.h Its last use was removed in r352916. No behavior change. Differential Revision: https://reviews.llvm.org/D59601
  1025. [AMDGPU][MC] Corrected checks for DS offset0 range See bug 40889: https://bugs.llvm.org/show_bug.cgi?id=40889 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D59313
  1026. [CGP] fix formatting; NFC
  1027. Fix sanitizer failures for 356550. Mark bcmp as having optimized codegen, so that asan can detect it and mark users as nobuiltin.
  1028. gn build: Add build files for some clang-tools-extra Adds clang-change-namespace, clang-move, clang-query, clang-reorder-fields. Differential Revision: https://reviews.llvm.org/D59554
  1029. [CGP] convert chain of 'if' to 'switch'; NFC This should be extended, but CGP does some strange things, so I'm intentionally not changing the potential order of any transforms yet.
  1030. gn build: Merge r356508
  1031. [AMDGPU][MC][GFX9] Added support of operands shared_base, shared_limit, private_base, private_limit, pops_exiting_wave_id See bug 39297: https://bugs.llvm.org/show_bug.cgi?id=39297 Reviewers: artem.tamazov, arsenm, rampitec Differential Revision: https://reviews.llvm.org/D59290
  1032. gn build: Merge r356519
  1033. [CGP][x86] add tests for usubo regression (PR41129); NFC
  1034. Follow up of rL356555 Pacify buildbot that complained about a member function not marked with override.
  1035. [TTI] getMemcpyCost This adds new function getMemcpyCost to TTI so that the cost of a memcpy can be modeled and queried. The default implementation returns Expensive, but targets can override this function to model the cost more accurately. Differential Revision: https://reviews.llvm.org/D59252
  1036. [llvm-objcopy] - Use replaceSectionReferences to update the sections for symbols in symbol table. If the compression was used and we had a symbol not involved in relocation, we never updated its section and it was silently removed from the output. Differential revision: https://reviews.llvm.org/D59542
  1037. Remove out of date comment. NFCI. DAGCombiner::convertBuildVecZextToZext just requires the extractions to be sequential, they don't have to start from 0'th index.
  1038. [ExpandMemCmp] Trigger on bcmp too. Summary: Fixes 41150. Reviewers: gchatelet Subscribers: hiraditya, llvm-commits, ckennelly, sbenza, jyknight Tags: #llvm Differential Revision: https://reviews.llvm.org/D59593
  1039. [X86] Use getConstantOperandAPInt to detect out-of-range shifts.
  1040. [X86] Remove X86 specific dag nodes for RDTSC/RDTSCP/RDPMC. NFCI This patch removes the following dag node opcodes from namespace X86ISD: RDTSC_DAG, RDTSCP_DAG, RDPMC_DAG The logic that expands RDTSC/RDPMC/XGETBV intrinsics is basically the same. The only differences are: RDTSC/RDTSCP don't implicitly read ECX. RDTSCP also implicitly writes ECX. I moved the common expansion logic into a helper function with the goal to get rid of code repetition. That helper is now used for the expansion of RDTSC/RDTSCP/RDPMC/XGETBV intrinsics. No functional change intended. Differential Revision: https://reviews.llvm.org/D59547
  1041. [perf][DebugInfo] follow up for "add SectionedAddress to DebugInfo interfaces" Summary: Fix the build failure when perf jit is enabled Reviewers: avl, dblaikie Reviewed By: avl Subscribers: modocache, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59189
  1042. [AMDGPU] Allow MIMG with no uses in adjustWritemask in isel Summary: If an MIMG instruction has managed to get through to adjustWritemask in isel but has no uses (and doesn't enable TFC) then prevent an assertion by not attempting to adjust the writemask. The instruction will be removed anyway. Change-Id: I9a5dba6bafe1f35ac99c1b73df390936e2ac27a7 Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58964
  1043. [instcombine] Add todos describing missing transforms for masked.* intrinsics
  1044. [X86] Remove X32 check lines from a test that doesn't have an X32 FileCheck prefix. Regenerate the test using update_llc_test_checks. NFC
  1045. Retry to add workaround to build scoped enums with VS2015. NFCI. We need this as we still have internal build bots on VS2015.
  1046. Revert "Add workaround to build scoped enums with VS2015. NFCI." This reverts commit 6080a6fb1949a2bdf053245d6062c7bf58dae7a6 (r356532). Clang does not accept this syntax, so reverting this until I can find something that works across all compilers.
  1047. Add workaround to build scoped enums with VS2015. NFCI. We need this as we still have internal build bots on VS2015.
  1048. [X86] Re-disable cmpxchg16b for 32-bit mode assembly parsing. This was broken recently when I factored the 64 bit mode check into hasCmpxchg16 without thinking about the AssemblerPredicate.
  1049. [ARM] Make sure to save/restore LR when we use tBfar. This change does two things. One, it ensures compilation will abort instead of miscompiling if ARMFrameLowering::determineCalleeSaves chooses not to save LR in a case where it's necessary. Two, it changes the way we estimate the size of a function to be more conservative in the presence of constant pool entries and jump tables. EstimateFunctionSizeInBytes probably still isn't really conservative enough, but I'm not sure how we can come up with a reliable estimate before constant islands runs. Differential Revision: https://reviews.llvm.org/D59439
  1050. [AArch64][GlobalISel] Add an optimization to select vector DUP instructions. This adds pattern matching for the insert+shufflevector sequence so we can generate dup instructions instead of the current TBL sequence. Differential Revision: https://reviews.llvm.org/D59558
  1051. [AArch64][GlobalISel] Make v4s32 G_IMPLICIT_DEF legal.
  1052. Remove MSVC compat hack since the inline keyword was added in 2015 Our minimum MSVC toolchain requirement is greater than 2015, so we don't need this conditional macro anymore. New versions of MSVC apparently have a header, xkeycheck.h, to check that keywords haven't been redefined. Fixes PR41144
  1053. [Remarks] Fix gcc build for r356519 Fails here: http://lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/20046/steps/build%20stage%201/logs/stdio
  1054. [DwarfDebug] Add triple to test.
  1055. [InstSimplify] Add additional cmp of abs without nsw tests; NFC
  1056. Reland "[Remarks] Add a new Remark / RemarkParser abstraction" This adds a Remark class that allows us to share code when working with remarks. The C API has been updated to reflect this. Instead of the parser generating C structs, it's now using a C++ object that is used through opaque pointers in C. This gives us much more flexibility on what changes we can make to the internal state of the object and interacts much better with scenarios where the library is used through dlopen. * C API updates: * move from C structs to opaque pointers and functions * the remark type is now an enum instead of a string * unit tests updates: * use mostly the C++ API * keep one test for the C API * rename to YAMLRemarksParsingTest * a typo was fixed: AnalysisFPCompute -> AnalysisFPCommute. * a new error message was added: "expected a remark tag." * llvm-opt-report has been updated to use the C++ parser instead of the C API Differential Revision: https://reviews.llvm.org/D59049 Original llvm-svn: 356491
  1057. Revert r356511 "[TailCallElim] Add tailcall elimination pass to LTO pipelines" Due to buildbot failures (LLD tests).
  1058. [DwarfDebug] Skip entries to big for 16 bit size field in Dwarf < 5. Nothing prevents entries from being bigger than the 16 bit size field in Dwarf < 5. For entries that are too big, just emit an empty entry instead of crashing. This fixes PR41038. Reviewers: probinson, aprantl, davide Reviewed By: probinson Differential Revision: https://reviews.llvm.org/D59518
  1059. [TailCallElim] Add tailcall elimination pass to LTO pipelines LTO provides additional opportunities for tailcall elimination due to link-time inlining and visibility of nocapture attribute. Testing showed negligible impact on compilation times. Differential Revision: https://reviews.llvm.org/D58391
  1060. Demanded elements support for masked.load and masked.gather Teach instcombine to propagate demanded elements through a masked load or masked gather instruction. This is in the broader context of improving vector pointer instcombine under https://reviews.llvm.org/D57140. Differential Revision: https://reviews.llvm.org/D57372
  1061. CodeGen: Refactor regallocator command line and target selection This will allow targets more flexibility to replace the register allocator core passes. In a future commit, AMDGPU will run the core register assignment passes twice, and will also want to disallow using the standard -regalloc option.
  1062. RegAllocFast: Do not allocate registers for undef uses Do not actually allocate a register for an undef use. Previously we we would create unnecessary reload instruction for undef uses where the register wasn't live. Patch by Matthias Braun
  1063. RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs The 2nd loop calculates spill costs but reports free registers as cost 0 anyway, so there is little benefit from having a separate early loop. Surprisingly this is not NFC, as many register are marked regDisabled so the first loop often picks up later registers unnecessarily instead of the first one available in the allocation order... Patch by Matthias Braun
  1064. Fix for ABS legalization on PPC buildbot.
  1065. Allow unordered loads to be considered invariant in CodeGen The actual code change is fairly straight forward, but exercising it isn't. First, it turned out we weren't adding the appropriate flags in SelectionDAG. Second, it turned out that we've got some optimization gaps, so obvious test cases don't work. My first attempt (in atomic-unordered.ll) points out a deficiency in our peephole-opt folding logic which I plan to fix separately. Instead, I'm exercising this through MachineLICM. Differential Revision: https://reviews.llvm.org/D59375
  1066. Revert "[Remarks] Add a new Remark / RemarkParser abstraction" This reverts commit 51dc6a8c84cd6a58562e320e1828a0158dbbf750. Breaks http://lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/20034/steps/build%20stage%201/logs/stdio.
  1067. [Remarks] Add a new Remark / RemarkParser abstraction This adds a Remark class that allows us to share code when working with remarks. The C API has been updated to reflect this. Instead of the parser generating C structs, it's now using a C++ object that is used through opaque pointers in C. This gives us much more flexibility on what changes we can make to the internal state of the object and interacts much better with scenarios where the library is used through dlopen. * C API updates: * move from C structs to opaque pointers and functions * the remark type is now an enum instead of a string * unit tests updates: * use mostly the C++ API * keep one test for the C API * rename to YAMLRemarksParsingTest * a typo was fixed: AnalysisFPCompute -> AnalysisFPCommute. * a new error message was added: "expected a remark tag." * llvm-opt-report has been updated to use the C++ parser instead of the C API Differential Revision: https://reviews.llvm.org/D59049
  1068. [ValueTracking] Use computeConstantRange() for unsigned add/sub overflow Improve computeOverflowForUnsignedAdd/Sub in ValueTracking by intersecting the computeConstantRange() result into the ConstantRange created from computeKnownBits(). This allows us to detect some additional never/always overflows conditions that can't be determined from known bits. This revision also adds basic handling for constants to computeConstantRange(). Non-splat vectors will be handled in a followup. The signed case will also be handled in a followup, as it needs some more groundwork. Differential Revision: https://reviews.llvm.org/D59386
  1069. gn build: Merge r356387.
  1070. gn build: Merge r356451.
  1071. [X86][SSE] SimplifyDemandedVectorEltsForTargetNode - handle repeated shift amounts If a value with multiple uses is only ever used for SSE shift amounts then we know that only the bottom 64-bits are needed.
  1072. [AtomicExpand] Fix a crash bug when lowering unordered loads to cmpxchg Add tests for wider atomic loads and stores. In the process, fix a crasher where we appearently handled unorder stores, but not loads, when lowering to cmpxchg idioms.
  1073. [MIPS][microMIPS] Enable dynamic stack realignment Dynamic stack realignment was disabled on micromips by checking if target has standard encoding. We simply change the condition to skip Mips16 only. Patch by Mirko Brkusanin. Differential Revision: http://reviews.llvm.org/D59499
  1074. [NFC] Fix unused variable in release builds This was introduced in rL356468.
  1075. [DAGCombine] Fix a miscompile when reducing BUILD_VECTORs to a shuffle In r311255 we added a case where we split vectors whose elements are all derived from the same input vector so that we could shuffle it more efficiently. In doing so, createBuildVecShuffle was taught to adjust for the fact that all indices would be based off of the first vector when this happens, but it's possible for the code that checked that to fire incorrectly if we happen to have a BUILD_VECTOR of extracts from subvectors and don't hit this new optimization. Instead of trying to detect if we've split the vector by checking if we have extracts from the same base vector, we can just pass that information into createBuildVecShuffle, avoiding the miscompile. Differential Revision: https://reviews.llvm.org/D59507
  1076. Fix unused variable warning. NFCI.
  1077. [Tests] Update to newer ISA There are some issues w/missed opts on older platforms, but that's not the purpose of this test. Using a newer API points out that some TODOs are already handled, and allows addition of tests to exercise other issues (future patch.)
  1078. [InstCombine] fold logic-of-nan-fcmps (PR41069) Combine 2 fcmps that are checking for nan-ness: and (fcmp ord X, 0), (and (fcmp ord Y, 0), Z) --> and (fcmp ord X, Y), Z or (fcmp uno X, 0), (or (fcmp uno Y, 0), Z) --> or (fcmp uno X, Y), Z This is an exact match for a minimal reassociation pattern. If we want to handle this more generally that should go in the reassociate pass and allow removing this code. This should fix: https://bugs.llvm.org/show_bug.cgi?id=41069
  1079. [AMDGPU] Add convergent attribute to WWM. Add the convergent attribute to the WWM intrinsic to stop it ever being sunk out of cfg. Differential Revision: https://reviews.llvm.org/D59536
  1080. [SelectionDAG] Handle unary SelectPatternFlavor for ABS case in SelectionDAGBuilder::visitSelect These changes are related to PR37743 and include: SelectionDAGBuilder::visitSelect handles the unary SelectPatternFlavor::SPF_ABS case to build ABS node. Delete the redundant recognizer of the integer ABS pattern from the DAGCombiner. Add promoting the integer ABS node in the LegalizeIntegerType. Expand-based legalization of integer result for the ABS nodes. Expand-based legalization of ABS vector operations. Add some integer abs testcases for different typesizes for Thumb arch Add the custom ABS expanding and change the SAD pattern recognizer for X86 arch: The i64 result of the ABS is expanded to: tmp = (SRA, Hi, 31) Lo = (UADDO tmp, Lo) Hi = (XOR tmp, (ADDCARRY tmp, hi, Lo:1)) Lo = (XOR tmp, Lo) The "detectZextAbsDiff" function is changed for the recognition of pattern with the ABS node. Given a ABS node, detect the following pattern: (ABS (SUB (ZERO_EXTEND a), (ZERO_EXTEND b))). Change integer abs testcases for codegen with the ABS node support for AArch64. Indicate that the ABS is legal for the i64 type when the NEON is supported. Change the integer abs testcases to show changing of codegen. Add combine and legalization of ABS nodes for Thumb arch. Extend 'matchSelectPattern' to recognize the ABS patterns with ICMP_SGE condition. For discussion, see https://bugs.llvm.org/show_bug.cgi?id=37743 Patch by: @ikulagin (Ivan Kulagin) Differential Revision: https://reviews.llvm.org/D49837
  1081. [llvm-ar] Support N [count] modifier Summary: GNU ar supports the 'N' count modifier for the extract (x) and delete (d) operations. When an archive contains multiple members with the same name, this can be used to extract (or delete) them individually. For example: ``` $ llvm-ar t archive.a foo foo $ llvm-ar x archive.a -> Writes foo twice, overwriting it the second time :( :( $ llvm-ar xN 1 archive.a foo && mv foo foo.1 $ llvm-ar xN 2 archive.a foo && mv foo foo.2 -> Write foo twice, renaming it in between invocations to preserve all versions ``` Reviewers: ruiu, MaskRay Reviewed By: ruiu, MaskRay Subscribers: jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59503
  1082. [AMDGPU] Add buffer/load 8/16 bit overloaded intrinsics Summary: Add buffer store/load 8/16 overloaded intrinsics for buffer, raw_buffer and struct_buffer Change-Id: I166a29f071b2ff4e4683fb0392564b1f223ac61d Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59265
  1083. [AMDGPU] Ban i8 min3 promotion. I found this really weird WWM-related case whereby through the WWM transformations our isel lowering was trying to promote 2 min's into a min3 for the i8 type, which our hardware doesn't support. The new min3_i8.ll test case would previously spew the error: PromoteIntegerResult #0: t69: i8 = SMIN3 t70, Constant:i8<0>, t68 Before the simple fix to our isel lowering to not do it for i8 MVT's. Differential Revision: https://reviews.llvm.org/D59543
  1084. [InstCombine] Add missing test for icmp transformation (NFC) This was split out of D59378. There was no testing for the EQ case in foldICmpWithDominatingICmp, add one here.
  1085. [mips] Fix crash on recursive using of .set Switch to the `MCParserUtils::parseAssignmentExpression` for parsing assignment expressions in the `.set` directive reduces code and allows to print an error message instead of crashing in case of incorrect recursive using of the `.set`. Fix for the bug https://bugs.llvm.org/show_bug.cgi?id=41053. Differential Revision: http://reviews.llvm.org/D59452
  1086. [DebugInfo] Move test files added in r356451 Moved the X86 dependant .ll tests added in r356451 from test/DebugInfo/Generic to test/DebugInfo/X86.
Revision 358363 by nico:
llvm-undname: Fix another crash-on-invalid found by oss-fuzz
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Demangle/MicrosoftDemangle.cpptrunk/lib/Demangle/MicrosoftDemangle.cpp
The file was modified/llvm/trunk/test/Demangle/invalid-manglings.testtrunk/test/Demangle/invalid-manglings.test
Revision 358362 by ctopper:
[X86] Redefine KUNPCK instructions to take a narrower source register class than destination register class. Remove copies from the isel output pattern.

There's no reason for the inputs to be the destination register class. This just
forces an unnecessary copy in the output patterns.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.tdtrunk/lib/Target/X86/X86InstrAVX512.td
Revision 358361 by ctopper:
[X86] Put the locked mi8 instrutions above the locked mi/mi32 so they will be prefered.

We want 64mi8 to be prefered over 64mi32. The order for 16mi/32mi doesn't
really matter.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrCompiler.tdtrunk/lib/Target/X86/X86InstrCompiler.td
Revision 358360 by ctopper:
[X86] Change IMUL with immediate instruction order to ri8 instructions come before ri/ri32 instructions.

This will ensure IMUL64ri8 is tried before IMUL64ri32. For IMUL32 and IMUL16 the
order doesn't really matter because only the ri8 versions use a predicate. That
automatically gives them priority.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrArithmetic.tdtrunk/lib/Target/X86/X86InstrArithmetic.td
Revision 358359 by ctopper:
[X86] Move VPTESTM matching from the isel table to custom code in X86ISelDAGToDAG.

We had many tablegen patterns for these instructions. And due to the
commutability of the patterns, tablegen expands them to even more patterns. All
together VPTESTMD patterns accounted for more the 50K of the 610K isel table.
This had gotten bad when we stopped canonicalizing AND to vXi64. This required
a pattern for every combination of bitcast input type.

This change moves the matching to custom code where it is easier to look through
the bitcasts without being concerned with the specific types.

The test changes are because we are now stricter with one use checks as its
required to make load folding legal. We now require the AND and any BITCAST to
only have a single use. This prevents forming VPTESTM and a VPAND with the same
inputs.

We now support broadcast loads for 128/256 patterns without VLX. We'll widen to
512-bit like and still fold the broadcast since the amount of memory read
doesn't change.

There are a few tests that got slightly longer because are now prefering
load + VPTESTM over XOR+VPCMPEQ for (seteq (load), allzeros). Previously we were
able to share the XOR with multiple VPTESTM instructions.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpptrunk/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.tdtrunk/lib/Target/X86/X86InstrAVX512.td
The file was modified/llvm/trunk/test/CodeGen/X86/avx512-vec-cmp.lltrunk/test/CodeGen/X86/avx512-vec-cmp.ll
The file was modified/llvm/trunk/test/CodeGen/X86/kshift.lltrunk/test/CodeGen/X86/kshift.ll
The file was modified/llvm/trunk/test/CodeGen/X86/movmsk-cmp.lltrunk/test/CodeGen/X86/movmsk-cmp.ll
The file was modified/llvm/trunk/test/CodeGen/X86/prefer-avx256-mask-extend.lltrunk/test/CodeGen/X86/prefer-avx256-mask-extend.ll
The file was modified/llvm/trunk/test/CodeGen/X86/prefer-avx256-mask-shuffle.lltrunk/test/CodeGen/X86/prefer-avx256-mask-shuffle.ll
The file was modified/llvm/trunk/test/CodeGen/X86/setcc-lowering.lltrunk/test/CodeGen/X86/setcc-lowering.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-fshl-128.lltrunk/test/CodeGen/X86/vector-fshl-128.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-fshl-256.lltrunk/test/CodeGen/X86/vector-fshl-256.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-fshl-512.lltrunk/test/CodeGen/X86/vector-fshl-512.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-fshr-128.lltrunk/test/CodeGen/X86/vector-fshr-128.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-fshr-256.lltrunk/test/CodeGen/X86/vector-fshr-256.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-fshr-512.lltrunk/test/CodeGen/X86/vector-fshr-512.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-lzcnt-512.lltrunk/test/CodeGen/X86/vector-lzcnt-512.ll
Revision 358358 by ctopper:
[X86] Don't form masked vpcmp/vcmp/vptestm operations if the setcc node has more than one use.

We're better of emitting a single compare + kand rather than a compare for the
other use and a masked compare.

I'm looking into using custom instruction selection for VPTESTM to reduce the
ridiculous number of permutations of patterns in the isel table. Putting a one
use check on all masked compare folding makes load fold matching in the custom
code easier.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.tdtrunk/lib/Target/X86/X86InstrAVX512.td
The file was modified/llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-upgrade.lltrunk/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vec_uaddo.lltrunk/test/CodeGen/X86/vec_uaddo.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-compare-all_of.lltrunk/test/CodeGen/X86/vector-compare-all_of.ll
Revision 358354 by maskray:
[ConstantRange] Simplify unittests after getSetSize was removed

Reviewers: lebedev.ri, nikic

Reviewed By: nikic

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60662
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/unittests/IR/ConstantRangeTest.cpptrunk/unittests/IR/ConstantRangeTest.cpp
Revision 358352 by maskray:
[Mem2Reg] Delete unused PointerAllocaValues

It is unused after AliasSetTracker support was removed.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpptrunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
Revision 358351 by maskray:
[Mem2Reg] Simplify and micro optimize

* Rearrange continu/break
* BBNumbers.lookup(A) -> BBNumbers.find(A)->second
  BBNumbers has been computed, thus we can assume the value exists in the predicate.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpptrunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
Revision 358350 by maskray:
[Mem2Reg] Don't call LBI.deleteValue on AllocInst/DbgVariableIntrinsic

Only StoreInst/LoadInst are assigned numbers. Other types of instructions are not in LBI.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpptrunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
Revision 358349 by maskray:
[Mem2Reg] Simplify rewriteSingleStoreAlloca
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpptrunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
Revision 358348 by maskray:
[ConstantRange] Fix unittest after rL358347
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/unittests/IR/ConstantRangeTest.cpptrunk/unittests/IR/ConstantRangeTest.cpp
Revision 358347 by maskray:
[ConstantRange] Delete unused getSetSize

getSetSize returns an APInt that is 1 bit wider. The APInt is typically 65-bit and requires memory allocation. isSizeStrictlySmallerThan and isSizeLargerThan are preferred. The last use of this helper method was removed by rL302385.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/ConstantRange.htrunk/include/llvm/IR/ConstantRange.h
The file was modified/llvm/trunk/lib/IR/ConstantRange.cpptrunk/lib/IR/ConstantRange.cpp
Revision 358346 by ctopper:
[X86] Update bool_reduction_v8f32 test cases from vector-compare-any_of.ll and vector-compare-all_of.ll to be proper reductions.

One of the shuffles was used twice. While the intended shuffle wasn't connected.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/vector-compare-all_of.lltrunk/test/CodeGen/X86/vector-compare-all_of.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-compare-any_of.lltrunk/test/CodeGen/X86/vector-compare-any_of.ll
Revision 358345 by ctopper:
[X86] Remove some unused tablegen multiclasses. NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.tdtrunk/lib/Target/X86/X86InstrAVX512.td
Revision 358344 by reames:
[Tests] Add tests for D60659, and make adjustments to others to make diff clear

Three related changes:
1) auto-gen several test files
2) Add the new tests at the bottom of said files
3) Adjust a couple of other test files not to use stores to constants when trying to test constexpr address handling
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/gep-custom-dl.lltrunk/test/Transforms/InstCombine/gep-custom-dl.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/getelementptr.lltrunk/test/Transforms/InstCombine/getelementptr.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/memcpy.lltrunk/test/Transforms/InstCombine/memcpy.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/memmove.lltrunk/test/Transforms/InstCombine/memmove.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/memset.lltrunk/test/Transforms/InstCombine/memset.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/store.lltrunk/test/Transforms/InstCombine/store.ll
Revision 358343 by void:
[X86] Use PC-relative mode for the kernel code model

Summary:
The Linux kernel uses PC-relative mode, so allow that when the code model is
"kernel".

Reviewers: craig.topper

Reviewed By: craig.topper

Subscribers: llvm-commits, kees, nickdesaulniers

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60643
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpptrunk/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/codemodel.lltrunk/test/CodeGen/X86/codemodel.ll
The file was modified/llvm/trunk/unittests/Support/VirtualFileSystemTest.cpptrunk/unittests/Support/VirtualFileSystemTest.cpp
Revision 358341 by nikic:
[CVP] Add tests for range of with.overflow result; NFC

Test range of with.overflow result in the no-overflow branch.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/CorrelatedValuePropagation/overflow_predicate.lltrunk/test/Transforms/CorrelatedValuePropagation/overflow_predicate.ll
Revision 358340 by nikic:
[ConstantRange] Disallow NUW | NSW in makeGuaranteedNoWrapRegion()

As motivated in D60598, this drops support for specifying both NUW and
NSW in makeGuaranteedNoWrapRegion(). None of the users of this function
currently make use of this.

When both NUW and NSW are specified, the exact nowrap region has two
disjoint parts and makeGNWR() returns one of them. This result doesn't
seem to be useful for anything, but makes the semantics of the function
fuzzier.

Differential Revision: https://reviews.llvm.org/D60632
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/ConstantRange.htrunk/include/llvm/IR/ConstantRange.h
The file was modified/llvm/trunk/lib/IR/ConstantRange.cpptrunk/lib/IR/ConstantRange.cpp
The file was modified/llvm/trunk/unittests/IR/ConstantRangeTest.cpptrunk/unittests/IR/ConstantRangeTest.cpp
Revision 358339 by nikic:
[InstCombine] Remove redundant/bogus mul_with_overflow combines

As pointed out in D60518 folding mulo(%x, undef) to {undef, undef}
isn't correct. As a correct version of this already exists in
InstructionSimplify (https://github.com/llvm-mirror/llvm/blob/bd8056ef326e075cc500f3f0cfcd1193bc200594/lib/Analysis/InstructionSimplify.cpp#L4750-L4757) this is just
dead code though. Drop it together with the mul(%x, 0) -> {0, false}
fold that is also already handled by InstSimplify.

Differential Revision: https://reviews.llvm.org/D60649
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpptrunk/lib/Transforms/InstCombine/InstCombineCompares.cpp
Revision 358338 by ctopper:
[X86] Use int64_t and isInt<N> instead of APInt operations in foldLoadStoreIntoMemOperand. NFC

We know all our values are limited to 64 bits here so we don't need an APInt.

This should save some generated code checking between large and small size.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpptrunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Revision 358337 by dhinton:
[CommandLineParser] Add DefaultOption flag

Summary: Add DefaultOption flag to CommandLineParser which provides a
default option or alias, but allows users to override it for some
other purpose as needed.

Also, add `-h` as a default alias to `-help`, which can be seamlessly
overridden by applications like llvm-objdump and llvm-readobj which
use `-h` as an alias for other options.

Reviewers: alexfh, klimek

Reviewed By: klimek

Subscribers: MaskRay, mehdi_amini, inglorion, dexonsmith, hiraditya, llvm-commits, jhenderson, arphaman, cfe-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D59746
Change TypePath in RepositoryPath in Workspace
The file was modified/cfe/trunk/lib/Tooling/CommonOptionsParser.cppN/A
The file was modified/llvm/trunk/docs/CommandLine.rsttrunk/docs/CommandLine.rst
The file was modified/llvm/trunk/include/llvm/Support/CommandLine.htrunk/include/llvm/Support/CommandLine.h
The file was modified/llvm/trunk/lib/Support/CommandLine.cpptrunk/lib/Support/CommandLine.cpp
The file was added/llvm/trunk/test/Supporttrunk/test/Support
The file was added/llvm/trunk/test/Support/check-default-options.txttrunk/test/Support/check-default-options.txt
The file was modified/llvm/trunk/tools/llvm-opt-report/OptReport.cpptrunk/tools/llvm-opt-report/OptReport.cpp
The file was modified/llvm/trunk/unittests/Support/CommandLineTest.cpptrunk/unittests/Support/CommandLineTest.cpp
Revision 358336 by aheejin:
[WebAssembly] Use Function::hasOptSize() (NFC)

Summary: Use member function.

Reviewers: aheejin

Subscribers: sunfish, hiraditya, sbc100, jgravelle-google, dschuff, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60651

Patch by Hideto Ueno (uenoku)
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpptrunk/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
Revision 358335 by maskray:
[CallingConvLower] Use SmallVectorImpl::swap
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/CallingConvLower.htrunk/include/llvm/CodeGen/CallingConvLower.h
Revision 358334 by maskray:
[Mem2Reg] Delete unused AllocaPointerVal

It is no longer used after the AliasSetTracker updating logic was removed.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpptrunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
Revision 358332 by maskray:
[ADT] Fix OwningArrayRef's move ctor
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/ADT/ArrayRef.htrunk/include/llvm/ADT/ArrayRef.h
The file was modified/llvm/trunk/unittests/ADT/ArrayRefTest.cpptrunk/unittests/ADT/ArrayRefTest.cpp
Revision 358331 by nikic:
[CVP] Fix inverted predicates in test; NFC

Checked the wrong direction in the umul tests... fix predicated to
line up with the test name.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/CorrelatedValuePropagation/overflow_predicate.lltrunk/test/Transforms/CorrelatedValuePropagation/overflow_predicate.ll
Revision 358330 by nikic:
[CVP] Add tests for with.overflow used as condition; NFC
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/Transforms/CorrelatedValuePropagation/overflow_predicate.lltrunk/test/Transforms/CorrelatedValuePropagation/overflow_predicate.ll
Revision 358328 by shchenz:
[InstCombine] Canonicalize (-X srem Y) to -(X srem Y).

Differential Revision: https://reviews.llvm.org/D60647
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpptrunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/srem-canonicalize.lltrunk/test/Transforms/InstCombine/srem-canonicalize.ll
Revision 358327 by shchenz:
[InstCombine] [NFC] add testcases for canonicalizing (-X srem Y) to -(X srem Y).
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/Transforms/InstCombine/srem-canonicalize.lltrunk/test/Transforms/InstCombine/srem-canonicalize.ll
Revision 358325 by reames:
[StackMaps] Update llvm-readobj to parse V3 Stackmaps

This updates the StackMap parser in the llvm-readobj tool to parse version 3 StackMaps, which were bumped in https://reviews.llvm.org/D32629.

Version 3 StackMaps differ in that they have a uint16 sized "location size" field which was added to the Location block in a StackMap record. The record has additional padding for alignment. This was a backwards incompatible change resulting in a StackMap version bump.

Patch By: jacob.hughes@kcl.ac.uk (with a rewrite of tests by me)
Differential Revision: https://reviews.llvm.org/D59020
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Object/StackMapParser.htrunk/include/llvm/Object/StackMapParser.h
The file was modified/llvm/trunk/test/Object/Inputs/stackmap-test.macho-x86-64trunk/test/Object/Inputs/stackmap-test.macho-x86-64
The file was modified/llvm/trunk/test/Object/stackmap-dump.testtrunk/test/Object/stackmap-dump.test
Revision 358324 by reames:
[StackMaps] Add location size to llvm-readobj -stackmap output

The size field of a location can be different for each entry, so it is useful to have this displayed in the output of llvm-readobj -stackmap. Below is an example of how the output would look:

Record ID: 2882400000, instruction offset: 16
   3 locations:
     #1: Constant 1, size: 8
     #2: Constant 2, size: 8
     #3: Constant 3, size: 8
   0 live-outs: [ ]

Patch By: jacob.hughes@kcl.ac.uk (with heavy modification by me)
Differential Revision: https://reviews.llvm.org/D59169
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Object/StackMapParser.htrunk/include/llvm/Object/StackMapParser.h
The file was modified/llvm/trunk/test/Object/stackmap-dump.testtrunk/test/Object/stackmap-dump.test
The file was modified/llvm/trunk/tools/llvm-readobj/StackMapPrinter.htrunk/tools/llvm-readobj/StackMapPrinter.h
Revision 358323 by reames:
[llvm-readobj] Minor style tweak for consistency sake [NFC]
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-readobj/COFFDumper.cpptrunk/tools/llvm-readobj/COFFDumper.cpp
The file was modified/llvm/trunk/tools/llvm-readobj/MachODumper.cpptrunk/tools/llvm-readobj/MachODumper.cpp
Revision 358322 by reames:
[StackMaps] Remove format version from the class name [NFC]

Motivation is to reduce silly diffs when we change the format.  For instance, this causes most of D59020 to disappear.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Object/StackMapParser.htrunk/include/llvm/Object/StackMapParser.h
The file was modified/llvm/trunk/tools/llvm-readobj/COFFDumper.cpptrunk/tools/llvm-readobj/COFFDumper.cpp
The file was modified/llvm/trunk/tools/llvm-readobj/ELFDumper.cpptrunk/tools/llvm-readobj/ELFDumper.cpp
The file was modified/llvm/trunk/tools/llvm-readobj/MachODumper.cpptrunk/tools/llvm-readobj/MachODumper.cpp
Revision 358319 by reames:
[StackMaps] Add explicit location size accessor to the stackmap parser

The reserved uint8 field in the location block of the stackmap record is used to denote the size of the location.

Patch By: jacob.hughes@kcl.ac.uk
Differential Revision: https://reviews.llvm.org/D59167
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Object/StackMapParser.htrunk/include/llvm/Object/StackMapParser.h
Revision 358318 by Amara Emerson:
[AArch64][GlobalISel] Enable copy elision in the pre-legalizer combine and fix a crash.

This enables the simple copy combine that already exists in the CombinerHelper.
However, it exposed a bug in the GISelChangeObserver where it wouldn't clear a
set of MIs to process, and so would end up causing a crash when deleted MIs were
being added to the combiner worklist again.

Differential Revision: https://reviews.llvm.org/D60579
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/GlobalISel/GISelChangeObserver.cpptrunk/lib/CodeGen/GlobalISel/GISelChangeObserver.cpp
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64PreLegalizerCombiner.cpptrunk/lib/Target/AArch64/AArch64PreLegalizerCombiner.cpp
The file was added/llvm/trunk/test/CodeGen/AArch64/GlobalISel/observer-change-crash.mirtrunk/test/CodeGen/AArch64/GlobalISel/observer-change-crash.mir
Revision 358315 by tlively:
[WebAssembly] Add DataCount section to object files

Summary:
This ensures that object files will continue to validate as
WebAssembly modules in the presence of bulk memory operations. Engines
that don't support bulk memory operations will not recognize the
DataCount section and will report validation errors, but that's ok
because object files aren't supposed to be run directly anyway.

Reviewers: aheejin, dschuff, sbc100

Subscribers: jgravelle-google, hiraditya, sunfish, rupprecht, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60623
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Object/Wasm.htrunk/include/llvm/Object/Wasm.h
The file was modified/llvm/trunk/include/llvm/ObjectYAML/WasmYAML.htrunk/include/llvm/ObjectYAML/WasmYAML.h
The file was modified/llvm/trunk/lib/MC/WasmObjectWriter.cpptrunk/lib/MC/WasmObjectWriter.cpp
The file was modified/llvm/trunk/lib/Object/WasmObjectFile.cpptrunk/lib/Object/WasmObjectFile.cpp
The file was modified/llvm/trunk/lib/ObjectYAML/WasmYAML.cpptrunk/lib/ObjectYAML/WasmYAML.cpp
The file was modified/llvm/trunk/test/MC/WebAssembly/bss.lltrunk/test/MC/WebAssembly/bss.ll
The file was modified/llvm/trunk/test/MC/WebAssembly/comdat.lltrunk/test/MC/WebAssembly/comdat.ll
The file was modified/llvm/trunk/test/MC/WebAssembly/data-section.strunk/test/MC/WebAssembly/data-section.s
The file was modified/llvm/trunk/test/MC/WebAssembly/debug-info.lltrunk/test/MC/WebAssembly/debug-info.ll
The file was modified/llvm/trunk/test/MC/WebAssembly/explicit-sections.lltrunk/test/MC/WebAssembly/explicit-sections.ll
The file was modified/llvm/trunk/test/MC/WebAssembly/external-data.lltrunk/test/MC/WebAssembly/external-data.ll
The file was modified/llvm/trunk/test/MC/WebAssembly/external-func-address.lltrunk/test/MC/WebAssembly/external-func-address.ll
The file was modified/llvm/trunk/test/MC/WebAssembly/global-ctor-dtor.lltrunk/test/MC/WebAssembly/global-ctor-dtor.ll
The file was modified/llvm/trunk/test/MC/WebAssembly/reloc-code.lltrunk/test/MC/WebAssembly/reloc-code.ll
The file was modified/llvm/trunk/test/MC/WebAssembly/reloc-data.lltrunk/test/MC/WebAssembly/reloc-data.ll
The file was modified/llvm/trunk/test/MC/WebAssembly/reloc-pic.strunk/test/MC/WebAssembly/reloc-pic.s
The file was modified/llvm/trunk/test/MC/WebAssembly/unnamed-data.lltrunk/test/MC/WebAssembly/unnamed-data.ll
The file was modified/llvm/trunk/test/MC/WebAssembly/weak-alias.lltrunk/test/MC/WebAssembly/weak-alias.ll
The file was modified/llvm/trunk/tools/llvm-readobj/WasmDumper.cpptrunk/tools/llvm-readobj/WasmDumper.cpp
The file was modified/llvm/trunk/tools/obj2yaml/wasm2yaml.cpptrunk/tools/obj2yaml/wasm2yaml.cpp
The file was modified/llvm/trunk/tools/yaml2obj/yaml2wasm.cpptrunk/tools/yaml2obj/yaml2wasm.cpp
Revision 358314 by Amara Emerson:
[GlobalISel] Fix a crash when handling an invalid MVT during call lowering.

This crash was introduced in r358032 as we try to construct an EVT from an MVT
in order to find the register type for the calling conv. Fall back instead of
trying to do this with an invalid MVT coming from i256.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/GlobalISel/CallLowering.cpptrunk/lib/CodeGen/GlobalISel/CallLowering.cpp
The file was added/llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-lowering-i256-crash.lltrunk/test/CodeGen/AArch64/GlobalISel/call-lowering-i256-crash.ll
Revision 358313 by asbirlea:
[MemorySSA] Add previous def to cache when found, even if trivial.

Summary:
When inserting a new Def, MemorySSA may be have non-minimal number of Phis.
While inserting, the walk to find the previous definition may cleanup minimal Phis.
When the last definition is trivial to obtain, we do not cache it.

It is possible while getting the previous definition for a Def to get two different answers:
- one that was straight-forward to find when walking the first path (a trivial phi in this case), and
- another that follows a cleanup of the trivial phi, it determines it may need additional Phi nodes, it inserts them and returns a new phi in the same position as the former trivial one.
While the Phis added for the second path are all redundant, they are not complete (the walk is only done upwards), and they are not properly cleaned up afterwards.

A way to fix this problem is to cache the straight-forward answer we got on the first walk.
The caching is only kept for the duration of a getPreviousDef call, and for Phis we use TrackingVH, so removing the trivial phi will lead to replacing it with the next dominating phi in the cache.
Resolves PR40749.

Reviewers: george.burgess.iv

Subscribers: jlebar, Prazek, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60634
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Analysis/MemorySSAUpdater.cpptrunk/lib/Analysis/MemorySSAUpdater.cpp
The file was added/llvm/trunk/test/Analysis/MemorySSA/pr40749_2.lltrunk/test/Analysis/MemorySSA/pr40749_2.ll
Revision 358312 by Amara Emerson:
[AArch64][GlobalISel] Fix a crash when selecting shufflevectors with an undef mask element.

If a shufflevector's mask vector has an element with "undef" then the generic
instruction defining that element register is a G_IMPLICT_DEF instead of G_CONSTANT.
This fixes the selector to handle this case, and for now assumes that undef just means
zero. In future we'll optimize this case properly.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpptrunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
The file was added/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mirtrunk/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
Revision 358310 by tlively:
[WebAssembly] Add mutable-globals to bleeding-edge CPU

Summary: This brings the backend in line with Clang.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60594
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/WebAssembly/WebAssembly.tdtrunk/lib/Target/WebAssembly/WebAssembly.td
The file was modified/llvm/trunk/test/CodeGen/WebAssembly/target-features.lltrunk/test/CodeGen/WebAssembly/target-features.ll
Revision 358305 by nikic:
[ConstantRange] Clarify makeGuaranteedNoWrapRegion() guarantees; NFC

makeGuaranteedNoWrapRegion() is actually makeExactNoWrapRegion() as
long as only one of NUW or NSW is specified. This is not obvious from
the current documentation, and some code seems to think that it is
only exact for single-element ranges. Clarify docs and add tests to
be more confident this really holds.

There are currently no users of makeGuaranteedNoWrapRegion() that
pass both NUW and NSW. I think it would be best to drop support for
this entirely and then rename the function to makeExactNoWrapRegion().

Knowing that the no-wrap region is exact is useful, because we can
backwards-constrain values. What I have in mind in particular is
that LVI should be able to constrain values on edges where the
with.overflow overflow flag is false.

Differential Revision: https://reviews.llvm.org/D60598
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/ConstantRange.htrunk/include/llvm/IR/ConstantRange.h
The file was modified/llvm/trunk/lib/IR/ConstantRange.cpptrunk/lib/IR/ConstantRange.cpp
The file was modified/llvm/trunk/unittests/IR/ConstantRangeTest.cpptrunk/unittests/IR/ConstantRangeTest.cpp
Revision 358304 by asbirlea:
[SCEV] Add option to forget everything in SCEV.

Summary:
Create a method to forget everything in SCEV.
Add a cl::opt and PassManagerBuilder option to use this in LoopUnroll.

Motivation: Certain Halide applications spend a very long time compiling in forgetLoop, and prefer to forget everything and rebuild SCEV from scratch.
Sample difference in compile time reduction: 21.04 to 14.78 using current ToT release build.
Testcase showcasing this cannot be opensourced and is fairly large.

The option disabled by default, but it may be desirable to enable by
default. Evidence in favor (two difference runs on different days/ToT state):

File Before (s) After (s)
clang-9.bc 7267.91 6639.14
llvm-as.bc 194.12 194.12
llvm-dis.bc 62.50 62.50
opt.bc 1855.85 1857.53

File Before (s) After (s)
clang-9.bc 8588.70 7812.83
llvm-as.bc 196.20 194.78
llvm-dis.bc 61.55 61.97
opt.bc 1739.78 1886.26

Reviewers: sanjoy

Subscribers: mehdi_amini, jlebar, zzheng, javed.absar, dmgreen, jdoerfert, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60144
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Analysis/ScalarEvolution.htrunk/include/llvm/Analysis/ScalarEvolution.h
The file was modified/llvm/trunk/include/llvm/Transforms/IPO/PassManagerBuilder.htrunk/include/llvm/Transforms/IPO/PassManagerBuilder.h
The file was modified/llvm/trunk/include/llvm/Transforms/Scalar.htrunk/include/llvm/Transforms/Scalar.h
The file was modified/llvm/trunk/include/llvm/Transforms/Utils/UnrollLoop.htrunk/include/llvm/Transforms/Utils/UnrollLoop.h
The file was modified/llvm/trunk/lib/Analysis/ScalarEvolution.cpptrunk/lib/Analysis/ScalarEvolution.cpp
The file was modified/llvm/trunk/lib/Transforms/IPO/PassManagerBuilder.cpptrunk/lib/Transforms/IPO/PassManagerBuilder.cpp
The file was modified/llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpptrunk/lib/Transforms/Scalar/LoopUnrollPass.cpp
The file was modified/llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpptrunk/lib/Transforms/Utils/LoopUnroll.cpp
The file was modified/llvm/trunk/lib/Transforms/Utils/LoopUnrollAndJam.cpptrunk/lib/Transforms/Utils/LoopUnrollAndJam.cpp
The file was modified/llvm/trunk/lib/Transforms/Utils/LoopUnrollRuntime.cpptrunk/lib/Transforms/Utils/LoopUnrollRuntime.cpp
The file was modified/llvm/trunk/unittests/Transforms/Utils/UnrollLoopTest.cpptrunk/unittests/Transforms/Utils/UnrollLoopTest.cpp
Revision 358303 by asbirlea:
[MemorySSA] Small fix for the clobber limit.

Summary:
After introducing the limit for clobber walking, `walkToPhiOrClobber` would assert that the limit is at least 1 on entry.
The test included triggered that assert.

The callsite in `tryOptimizePhi` making the calls to `walkToPhiOrClobber` is structured like this:
```
while (true) {
   if (getBlockingAccess()) { // calls walkToPhiOrClobber
   }
   for (...) {
     walkToPhiOrClobber();
   }
}
```

The cleanest fix is to check if the limit was reached inside `walkToPhiOrClobber`, and give an allowence of 1.
This approach not make any alias() calls (no calls to instructionClobbersQuery), so the performance condition is enforced.
The limit is set back to 0 if not used, as this provides info on the fact that we stopped before reaching a true clobber.

Reviewers: george.burgess.iv

Subscribers: jlebar, Prazek, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60479
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Analysis/MemorySSA.cpptrunk/lib/Analysis/MemorySSA.cpp
The file was added/llvm/trunk/test/Analysis/MemorySSA/reduce_clobber_limit.lltrunk/test/Analysis/MemorySSA/reduce_clobber_limit.ll
Revision 358299 by reames:
[InstCombine] Fix a nasty miscompile introduced w/masked.gather demanded elts

This fixes a miscompile which was introduced in r356510 (https://reviews.llvm.org/D57372).

The problem is that the original patch removed pointer operands where the load results we're demanded, but without considering the legality of the load itself.  If the masked.gather had active, but undemanded, lanes, then we could end up creating a load which loaded from an undef address.  The result could be a segfault, or, in theory, an arbitrary read from a random memory location into an used register.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpptrunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/masked_intrinsics.lltrunk/test/Transforms/InstCombine/masked_intrinsics.ll
Revision 358298 by nikic:
[CVP] Set NSW/NUW flags when simplifying with.overflow

When CVP determines that a with.overflow intrinsic cannot overflow,
it currently inserts a simple add/sub. As we already determined that
there can be no overflow, we should add the appropriate NUW/NSW flag.

Differential Revision: https://reviews.llvm.org/D60585
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpptrunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
The file was modified/llvm/trunk/test/Transforms/CorrelatedValuePropagation/overflows.lltrunk/test/Transforms/CorrelatedValuePropagation/overflows.ll
Revision 358297 by nikic:
[KnownBits] Add computeForAddCarry()

This is for D60460. computeForAddSub() essentially already supports
carries because it has to deal with subtractions. This revision
extracts a lower-level computeForAddCarry() function, which allows
computing the known bits for add (carry known zero), sub (carry known
one) and addcarry (carry unknown).

As we don't seem to have any yet, I've added a unit test file for
KnownBits and exhaustive tests for the new computeForAddCarry()
functionality, as well the existing computeForAddSub() function.

Differential Revision: https://reviews.llvm.org/D60522
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Support/KnownBits.htrunk/include/llvm/Support/KnownBits.h
The file was modified/llvm/trunk/lib/Support/KnownBits.cpptrunk/lib/Support/KnownBits.cpp
The file was modified/llvm/trunk/unittests/Support/CMakeLists.txttrunk/unittests/Support/CMakeLists.txt
The file was added/llvm/trunk/unittests/Support/KnownBitsTest.cpptrunk/unittests/Support/KnownBitsTest.cpp
Revision 358296 by reames:
[Tests] Checkin a test demonstrating a miscompile so that patch which fixes it shows a clear diff
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/masked_intrinsics.lltrunk/test/Transforms/InstCombine/masked_intrinsics.ll
Revision 358295 by Lang Hames:
Simplify decoupling between RuntimeDyld/RuntimeDyldChecker, add 'got_addr' util.

This patch reduces the number of functions in the interface between RuntimeDyld
and RuntimeDyldChecker by combining "GetXAddress" and "GetXContent" functions
into "GetXInfo" functions that return a struct describing both the address and
content. The GetStubOffset function is also replaced with a pair of utilities,
GetStubInfo and GetGOTInfo, that fit the new scheme. For RuntimeDyld both of
these functions will return the same result, but for the new JITLink linker
(https://reviews.llvm.org/D58704) these will provide the addresses of PLT stubs
and GOT entries respectively.

For JITLink's use, a 'got_addr' utility has been added to the rtdyld-check
language, and the syntax of 'got_addr' and 'stub_addr' has been changed: both
functions now take two arguments, a 'stub container name' and a target symbol
name. For llvm-rtdyld/RuntimeDyld the stub container name is the object file
name and section name, separated by a slash. E.g.:

rtdyld-check: *{8}(stub_addr(foo.o/__text, y)) = y

For the upcoming llvm-jitlink utility, which creates stubs on a per-file basis
rather than a per-section basis, the container name is just the file name. E.g.:

jitlink-check: *{8}(got_addr(foo.o, y)) = y
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.htrunk/include/llvm/ExecutionEngine/RuntimeDyld.h
The file was modified/llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyldChecker.htrunk/include/llvm/ExecutionEngine/RuntimeDyldChecker.h
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpptrunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpptrunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCheckerImpl.htrunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCheckerImpl.h
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.htrunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.htrunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFI386.htrunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFI386.h
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFThumb.htrunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFThumb.h
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFX86_64.htrunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFX86_64.h
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.htrunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.htrunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.h
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOI386.htrunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOI386.h
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOX86_64.htrunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOX86_64.h
The file was modified/llvm/trunk/test/ExecutionEngine/RuntimeDyld/AArch64/MachO_ARM64_relocations.strunk/test/ExecutionEngine/RuntimeDyld/AArch64/MachO_ARM64_relocations.s
The file was modified/llvm/trunk/test/ExecutionEngine/RuntimeDyld/ARM/MachO_ARM_PIC_relocations.strunk/test/ExecutionEngine/RuntimeDyld/ARM/MachO_ARM_PIC_relocations.s
The file was modified/llvm/trunk/test/ExecutionEngine/RuntimeDyld/ARM/MachO_Thumb_Relocations.strunk/test/ExecutionEngine/RuntimeDyld/ARM/MachO_Thumb_Relocations.s
The file was modified/llvm/trunk/test/ExecutionEngine/RuntimeDyld/Mips/ELF_Mips64r2N64_PIC_relocations.strunk/test/ExecutionEngine/RuntimeDyld/Mips/ELF_Mips64r2N64_PIC_relocations.s
The file was modified/llvm/trunk/test/ExecutionEngine/RuntimeDyld/Mips/ELF_N32_relocations.strunk/test/ExecutionEngine/RuntimeDyld/Mips/ELF_N32_relocations.s
The file was modified/llvm/trunk/test/ExecutionEngine/RuntimeDyld/Mips/ELF_O32_PIC_relocations.strunk/test/ExecutionEngine/RuntimeDyld/Mips/ELF_O32_PIC_relocations.s
The file was modified/llvm/trunk/test/ExecutionEngine/RuntimeDyld/PowerPC/ppc64_elf.strunk/test/ExecutionEngine/RuntimeDyld/PowerPC/ppc64_elf.s
The file was modified/llvm/trunk/test/ExecutionEngine/RuntimeDyld/X86/MachO_x86-64_PIC_relocations.strunk/test/ExecutionEngine/RuntimeDyld/X86/MachO_x86-64_PIC_relocations.s
The file was modified/llvm/trunk/tools/llvm-rtdyld/llvm-rtdyld.cpptrunk/tools/llvm-rtdyld/llvm-rtdyld.cpp
Revision 358292 by bcahoon:
[Hexagon] Fix reuse bug in Vector Loop Carried Reuse pass

The Hexagon Vector Loop Carried Reuse pass was allowing reuse between
two shufflevectors with different masks. The reason is that the masks
are not instruction objects, so the code that checks each operand
just skipped over the operands.

This patch fixes the bug by checking if the operands are the same
when they are not instruction objects. If the objects are not the
same, then the code assumes that reuse cannot occur.

Differential Revision: https://reviews.llvm.org/D60019
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpptrunk/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp
The file was added/llvm/trunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_invalid.lltrunk/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_invalid.ll
Revision 358291 by spatel:
[DAGCombiner] narrow shuffle of concatenated vectors

// shuffle (concat X, undef), (concat Y, undef), Mask -->
// concat (shuffle X, Y, Mask0), (shuffle X, Y, Mask1)

The ARM changes with 'vtrn' and narrowed 'vuzp' are improvements.

The x86 changes look neutral or better. There's one test with an
extra instruction, but that could be reversed for a subtarget with
the right attributes. But by default, we want to avoid the 256-bit
op when possible (in my motivating benchmark, a handful of ymm ops
sprinkled into a sequence of xmm ops are triggering frequency
throttling on Haswell resulting in significantly worse perf).

Differential Revision: https://reviews.llvm.org/D60545
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpptrunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modified/llvm/trunk/test/CodeGen/ARM/vuzp.lltrunk/test/CodeGen/ARM/vuzp.ll
The file was modified/llvm/trunk/test/CodeGen/ARM/vzip.lltrunk/test/CodeGen/ARM/vzip.ll
The file was modified/llvm/trunk/test/CodeGen/X86/mulvi32.lltrunk/test/CodeGen/X86/mulvi32.ll
The file was modified/llvm/trunk/test/CodeGen/X86/oddshuffles.lltrunk/test/CodeGen/X86/oddshuffles.ll
Revision 358289 by zturner:
[PDB Docs] Add some prose describing public and global symbols.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/PDB/CodeViewSymbols.rsttrunk/docs/PDB/CodeViewSymbols.rst
Revision 358287 by yamauchi:
Add options for MaxLoadsPerMemcmp(OptSize).

Reviewers: davidxl

Reviewed By: davidxl

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60587
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/ExpandMemCmp.cpptrunk/lib/CodeGen/ExpandMemCmp.cpp
Revision 358286 by rksimon:
[X86][SSE] Recognise vXi1 boolean anyof/allof reduction patterns

Currently combineHorizontalPredicateResult only handles anyof/allof reduction patterns of legal types, which can be tricky to match as type legalization of bools can introduce bitcasts/truncs/extensions.

This patch extends combineHorizontalPredicateResult to recognise vXi1 bool reductions as well and uses the existing combineBitcastvxi1 helper to create the MOVMSK necessary to then compare the signmask result.

This ensures the accuracy of the reduction costs added in D60403 which assume the MOVMSK generation.

Differential Revision: https://reviews.llvm.org/D60610
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/vector-compare-all_of.lltrunk/test/CodeGen/X86/vector-compare-all_of.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-compare-any_of.lltrunk/test/CodeGen/X86/vector-compare-any_of.ll
Revision 358281 by hans:
Revert r358268 "[DebugInfo] DW_OP_deref_size in PrologEpilogInserter."

It causes clang to crash while building Chromium. See https://crbug.com/952230
for reproducer.

> The PrologEpilogInserter need to insert a DW_OP_deref_size before
> prepending a memory location expression to an already implicit
> expression to avoid having the existing expression act on the memory
> address instead of the value behind it.
>
> The reason for using DW_OP_deref_size and not plain DW_OP_deref is that
> big-endian targets need to read the right size as simply truncating a
> larger read would yield the wrong result (LSB bytes are not at the lower
> address).
>
> Differential Revision: https://reviews.llvm.org/D59687
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/DebugInfoMetadata.htrunk/include/llvm/IR/DebugInfoMetadata.h
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfExpression.cpptrunk/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
The file was modified/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpptrunk/lib/CodeGen/MIRParser/MIParser.cpp
The file was modified/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpptrunk/lib/CodeGen/PrologEpilogInserter.cpp
The file was modified/llvm/trunk/lib/IR/DebugInfoMetadata.cpptrunk/lib/IR/DebugInfoMetadata.cpp
The file was removed/llvm/trunk/test/CodeGen/X86/prologepilog_deref_size.mirtrunk/test/CodeGen/X86/prologepilog_deref_size.mir
Revision 358278 by evgeny777:
[llvm-objcopy] Fill .symtab_shndx section correctly

Differential revision: https://reviews.llvm.org/D60555
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/tools/llvm-objcopy/ELF/many-sections.testtrunk/test/tools/llvm-objcopy/ELF/many-sections.test
The file was modified/llvm/trunk/tools/llvm-objcopy/ELF/Object.cpptrunk/tools/llvm-objcopy/ELF/Object.cpp
The file was modified/llvm/trunk/tools/llvm-objcopy/ELF/Object.htrunk/tools/llvm-objcopy/ELF/Object.h
Revision 358277 by maskray:
Use llvm::upper_bound. NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/ExecutionDomainFix.cpptrunk/lib/CodeGen/ExecutionDomainFix.cpp
The file was modified/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerInfo.cpptrunk/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
The file was modified/llvm/trunk/lib/CodeGen/LiveInterval.cpptrunk/lib/CodeGen/LiveInterval.cpp
The file was modified/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpptrunk/lib/CodeGen/RegisterCoalescer.cpp
Revision 358271 by zhangkang:
[PowerPC] Add initialization for some ppc passes

Summary:

Some llc debug options need pass-name as the parameters.
But if we use the pass-name ppc-early-ret, we will get below error:
llc test.ll -stop-after ppc-early-ret
LLVM ERROR: "ppc-early-ret" pass is not registered.
Below pass-names have the pass is not registered error:
ppc-ctr-loops
ppc-ctr-loops-verify
ppc-loop-preinc-prep
ppc-toc-reg-deps
ppc-vsx-copy
ppc-early-ret
ppc-vsx-fma-mutate
ppc-vsx-swaps
ppc-reduce-cr-ops
ppc-qpx-load-splat
ppc-branch-coalescing
ppc-branch-select

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D60248
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/PowerPC/PPC.htrunk/lib/Target/PowerPC/PPC.h
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpptrunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpptrunk/lib/Target/PowerPC/PPCBranchSelector.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpptrunk/lib/Target/PowerPC/PPCCTRLoops.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCEarlyReturn.cpptrunk/lib/Target/PowerPC/PPCEarlyReturn.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCLoopPreIncPrep.cpptrunk/lib/Target/PowerPC/PPCLoopPreIncPrep.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCQPXLoadSplat.cpptrunk/lib/Target/PowerPC/PPCQPXLoadSplat.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCReduceCRLogicals.cpptrunk/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCTLSDynamicCall.cpptrunk/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCTOCRegDeps.cpptrunk/lib/Target/PowerPC/PPCTOCRegDeps.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpptrunk/lib/Target/PowerPC/PPCTargetMachine.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCVSXCopy.cpptrunk/lib/Target/PowerPC/PPCVSXCopy.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCVSXSwapRemoval.cpptrunk/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
The file was added/llvm/trunk/test/CodeGen/PowerPC/ppc-passname-assert.lltrunk/test/CodeGen/PowerPC/ppc-passname-assert.ll
The file was added/llvm/trunk/test/CodeGen/PowerPC/ppc-passname.lltrunk/test/CodeGen/PowerPC/ppc-passname.ll
Revision 358270 by jmorse:
[DebugInfo] Fix pr41175 Dead Store Elimination missing debug loc

Bug: https://bugs.llvm.org/show_bug.cgi?id=41175

In the bug test case the DSE pass is shortening the range of memory that a
memset is working on. A getelementptr is generated so that the new
starting address can be passed to memset. This instruction was not given
a DebugLoc.

To fix the bug, copy the DebugLoc from the memset instruction.

Patch by Orlando Cazalet-Hyams!

Differential Revision: https://reviews.llvm.org/D60556
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpptrunk/lib/Transforms/Scalar/DeadStoreElimination.cpp
The file was added/llvm/trunk/test/Transforms/DeadStoreElimination/memset-missing-debugloc.lltrunk/test/Transforms/DeadStoreElimination/memset-missing-debugloc.ll
Revision 358268 by markus:
[DebugInfo] DW_OP_deref_size in PrologEpilogInserter.

The PrologEpilogInserter need to insert a DW_OP_deref_size before
prepending a memory location expression to an already implicit
expression to avoid having the existing expression act on the memory
address instead of the value behind it.

The reason for using DW_OP_deref_size and not plain DW_OP_deref is that
big-endian targets need to read the right size as simply truncating a
larger read would yield the wrong result (LSB bytes are not at the lower
address).

Differential Revision: https://reviews.llvm.org/D59687
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/DebugInfoMetadata.htrunk/include/llvm/IR/DebugInfoMetadata.h
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfExpression.cpptrunk/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
The file was modified/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpptrunk/lib/CodeGen/MIRParser/MIParser.cpp
The file was modified/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpptrunk/lib/CodeGen/PrologEpilogInserter.cpp
The file was modified/llvm/trunk/lib/IR/DebugInfoMetadata.cpptrunk/lib/IR/DebugInfoMetadata.cpp
The file was added/llvm/trunk/test/CodeGen/X86/prologepilog_deref_size.mirtrunk/test/CodeGen/X86/prologepilog_deref_size.mir
Revision 358267 by hans:
Fix missing arguments in tutorial

In tutorial "8. Kaleidoscope: Compiling to Object Code" a call to
TargetMachine->addPassesToEmitFile(pass, dest, FileType) is missing
nullptr as its 3rd value.

Patch by Sajjad Heydari!

Differential revision: https://reviews.llvm.org/D60369
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/tutorial/LangImpl08.rsttrunk/docs/tutorial/LangImpl08.rst
Revision 358264 by echristo:
Move getNumFrameInfos and getDwarfFrameInfos out of line and remove
the MCDwarf.h include.

This removes 50 transitive dependencies for a modification of
MCDwarf.h in a build of llc for a pair of out of line functions
and reduces the build overhead of 'touch MCDwarf.h" by 15% without
impacting test time of check-llvm.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/MC/MCStreamer.htrunk/include/llvm/MC/MCStreamer.h
The file was modified/llvm/trunk/lib/MC/MCStreamer.cpptrunk/lib/MC/MCStreamer.cpp
Revision 358263 by echristo:
Add explicit dependencies on MCSection.h and MCDwarf.h to the .cpp
files rather than rely on transitive includes from MCStreamer.h.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpptrunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
The file was modified/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpptrunk/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
The file was modified/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpptrunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
The file was modified/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpptrunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
The file was modified/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpptrunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
Revision 358262 by maskray:
[ConstantFold] Don't evaluate FP or FP vector casts or truncations when simplifying icmp

Fix PR41476
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/IR/ConstantFold.cpptrunk/lib/IR/ConstantFold.cpp
The file was modified/llvm/trunk/test/Transforms/InstSimplify/bitcast-vector-fold.lltrunk/test/Transforms/InstSimplify/bitcast-vector-fold.ll
Revision 358260 by echristo:
Revert "[PowerPC] Add initialization for some ppc passes"

This reverts commit 6f8f98ce8de7c0e4ebd7fa2e1fd9507fe8d1c317 as it
is breaking nearly every bot.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/PowerPC/PPC.htrunk/lib/Target/PowerPC/PPC.h
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpptrunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpptrunk/lib/Target/PowerPC/PPCBranchSelector.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpptrunk/lib/Target/PowerPC/PPCCTRLoops.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCEarlyReturn.cpptrunk/lib/Target/PowerPC/PPCEarlyReturn.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCLoopPreIncPrep.cpptrunk/lib/Target/PowerPC/PPCLoopPreIncPrep.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCQPXLoadSplat.cpptrunk/lib/Target/PowerPC/PPCQPXLoadSplat.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCReduceCRLogicals.cpptrunk/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCTLSDynamicCall.cpptrunk/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCTOCRegDeps.cpptrunk/lib/Target/PowerPC/PPCTOCRegDeps.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpptrunk/lib/Target/PowerPC/PPCTargetMachine.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCVSXCopy.cpptrunk/lib/Target/PowerPC/PPCVSXCopy.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCVSXSwapRemoval.cpptrunk/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
The file was removed/llvm/trunk/test/CodeGen/PowerPC/ppc-passname-assert.lltrunk/test/CodeGen/PowerPC/ppc-passname-assert.ll
The file was removed/llvm/trunk/test/CodeGen/PowerPC/ppc-passname.lltrunk/test/CodeGen/PowerPC/ppc-passname.ll
Revision 358259 by Xing:
[llvm-readobj] Change variables' name to match LLVM-style. NFC.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-readobj/ELFDumper.cpptrunk/tools/llvm-readobj/ELFDumper.cpp
Revision 358258 by echristo:
Move addInitialFrameState out of line and remove the MCDwarf.h include.

This removes 50 transitive dependencies for a modification of
MCDwarf.h in a build of llc for a single out of line function
and reduces the build overhead by 20% without impacting test
time of check-llvm.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/MC/MCAsmInfo.htrunk/include/llvm/MC/MCAsmInfo.h
The file was modified/llvm/trunk/lib/MC/MCAsmInfo.cpptrunk/lib/MC/MCAsmInfo.cpp
Revision 358257 by ctopper:
[TargetLowering][X86] Teach SimplifyDemandedBits to use ShrinkDemandedOp on ISD::SHL nodes.

If the upper bits of the SHL result aren't used, we might be able to use a narrower shift. For example, on X86 this can turn a 64-bit into 32-bit enabling a smaller encoding.

Differential Revision: https://reviews.llvm.org/D60358
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpptrunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/btc_bts_btr.lltrunk/test/CodeGen/X86/btc_bts_btr.ll
The file was modified/llvm/trunk/test/CodeGen/X86/narrow-shl-cst.lltrunk/test/CodeGen/X86/narrow-shl-cst.ll
The file was modified/llvm/trunk/test/CodeGen/X86/scheduler-backtracking.lltrunk/test/CodeGen/X86/scheduler-backtracking.ll
The file was modified/llvm/trunk/test/CodeGen/X86/zext-logicop-shift-load.lltrunk/test/CodeGen/X86/zext-logicop-shift-load.ll
Revision 358256 by zhangkang:
[PowerPC] Add initialization for some ppc passes

Summary:

Some llc debug options need pass-name as the parameters.
But if we use the pass-name ppc-early-ret, we will get below error:
llc test.ll -stop-after ppc-early-ret
LLVM ERROR: "ppc-early-ret" pass is not registered.
Below pass-names have the pass is not registered error:
ppc-ctr-loops
ppc-ctr-loops-verify
ppc-loop-preinc-prep
ppc-toc-reg-deps
ppc-vsx-copy
ppc-early-ret
ppc-vsx-fma-mutate
ppc-vsx-swaps
ppc-reduce-cr-ops
ppc-qpx-load-splat
ppc-branch-coalescing
ppc-branch-select

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D60248
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/PowerPC/PPC.htrunk/lib/Target/PowerPC/PPC.h
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCBranchCoalescing.cpptrunk/lib/Target/PowerPC/PPCBranchCoalescing.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpptrunk/lib/Target/PowerPC/PPCBranchSelector.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpptrunk/lib/Target/PowerPC/PPCCTRLoops.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCEarlyReturn.cpptrunk/lib/Target/PowerPC/PPCEarlyReturn.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCLoopPreIncPrep.cpptrunk/lib/Target/PowerPC/PPCLoopPreIncPrep.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCQPXLoadSplat.cpptrunk/lib/Target/PowerPC/PPCQPXLoadSplat.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCReduceCRLogicals.cpptrunk/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCTLSDynamicCall.cpptrunk/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCTOCRegDeps.cpptrunk/lib/Target/PowerPC/PPCTOCRegDeps.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpptrunk/lib/Target/PowerPC/PPCTargetMachine.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCVSXCopy.cpptrunk/lib/Target/PowerPC/PPCVSXCopy.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCVSXSwapRemoval.cpptrunk/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
The file was added/llvm/trunk/test/CodeGen/PowerPC/ppc-passname-assert.lltrunk/test/CodeGen/PowerPC/ppc-passname-assert.ll
The file was added/llvm/trunk/test/CodeGen/PowerPC/ppc-passname.lltrunk/test/CodeGen/PowerPC/ppc-passname.ll
Revision 358255 by echristo:
Move addFrameInst out of line and remove the MCDwarf.h include.

This removes 500 transitive dependencies for a modification of
MCDwarf.h in a build of llc for a single out of line function
and reduces the build overhead by more than half without impacting
test time of check-llvm.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/MachineFunction.htrunk/include/llvm/CodeGen/MachineFunction.h
The file was modified/llvm/trunk/lib/CodeGen/MachineFunction.cpptrunk/lib/CodeGen/MachineFunction.cpp
Revision 358254 by echristo:
Include what's used in a few cpp files - these were getting transitive
includes from MCDwarf.h.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/CodeGenPrepare.cpptrunk/lib/CodeGen/CodeGenPrepare.cpp
The file was modified/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpptrunk/lib/CodeGen/LiveDebugVariables.cpp
The file was modified/llvm/trunk/lib/CodeGen/MachineOperand.cpptrunk/lib/CodeGen/MachineOperand.cpp
The file was modified/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpptrunk/lib/Target/Sparc/SparcISelLowering.cpp
Revision 358253 by wuzish:
[PowerPC] More precise exploitation of P9 maddld instruction when operands are constant

There are 3 operands of maddld, (add (mul %1, %2), %3) and sometimes
they are constant. If there is constant operand, it takes extra li to
materialize the operand, and one more extra register too. So it's not
profitable to use maddld to optimize mul-add pattern.

Differential Revision: https://reviews.llvm.org/D60181
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.tdtrunk/lib/Target/PowerPC/PPCInstr64Bit.td
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.tdtrunk/lib/Target/PowerPC/PPCInstrInfo.td
The file was modified/llvm/trunk/test/CodeGen/PowerPC/maddld.lltrunk/test/CodeGen/PowerPC/maddld.ll
Revision 358251 by maskray:
MCDwarfLineTableheader::tryGetFile : replace a loop with llvm::find

Note, `DirIndex++` below is incorrect for DWARF 5, but it can be fixed
later after the file index is fixed.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/MC/MCDwarf.cpptrunk/lib/MC/MCDwarf.cpp
Revision 358250 by echristo:
Move a couple of optional references to just optional to make the
forwarding APIs look similar.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/MC/MCDwarf.htrunk/include/llvm/MC/MCDwarf.h
The file was modified/llvm/trunk/lib/MC/MCDwarf.cpptrunk/lib/MC/MCDwarf.cpp
Revision 358247 by maskray:
[MC] Fix typo: .symtab_shndxr -> .symtab_shndx

This special section is named .symtab_shndx, according to gABI Chapter 4
Sections, and the name is used by some other tools. Though the section
type SHT_SYMTAB_SHNDX is what really matters, let's fix the typo
introduced in rL204769 :)
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/MC/ELFObjectWriter.cpptrunk/lib/MC/ELFObjectWriter.cpp
Revision 358246 by maskray:
Use llvm::lower_bound. NFC

This reapplies rL358161. That commit inadvertently reverted an exegesis file to an old version.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/DebugInfo/DWARF/DWARFUnit.htrunk/include/llvm/DebugInfo/DWARF/DWARFUnit.h
The file was modified/llvm/trunk/lib/Analysis/TargetLibraryInfo.cpptrunk/lib/Analysis/TargetLibraryInfo.cpp
The file was modified/llvm/trunk/lib/Bitcode/Reader/ValueList.cpptrunk/lib/Bitcode/Reader/ValueList.cpp
The file was modified/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpptrunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modified/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpptrunk/lib/CodeGen/RegAllocGreedy.cpp
The file was modified/llvm/trunk/lib/DebugInfo/DWARF/DWARFDebugLoc.cpptrunk/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp
The file was modified/llvm/trunk/lib/Transforms/Utils/LowerSwitch.cpptrunk/lib/Transforms/Utils/LowerSwitch.cpp
The file was modified/llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpptrunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
Revision 358244 by echristo:
Remove a parameter that was being passed around that we had at the
local callsite.

NFC.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/MC/MCDwarf.htrunk/include/llvm/MC/MCDwarf.h
The file was modified/llvm/trunk/lib/MC/MCDwarf.cpptrunk/lib/MC/MCDwarf.cpp
Revision 358241 by nico:
llvm-undname: Use UNREACHABLE after exhaustive switch returning everywhere

No behavior change.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Demangle/MicrosoftDemangle.cpptrunk/lib/Demangle/MicrosoftDemangle.cpp
Revision 358240 by nico:
llvm-undname: Name a bool param, no behavior change
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Demangle/MicrosoftDemangle.cpptrunk/lib/Demangle/MicrosoftDemangle.cpp
Revision 358239 by nico:
llvm-undname: Fix out-of-bounds read on invalid intrinsic function code

Found by inspection.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Demangle/MicrosoftDemangle.htrunk/include/llvm/Demangle/MicrosoftDemangle.h
The file was modified/llvm/trunk/lib/Demangle/MicrosoftDemangle.cpptrunk/lib/Demangle/MicrosoftDemangle.cpp
The file was modified/llvm/trunk/test/Demangle/invalid-manglings.testtrunk/test/Demangle/invalid-manglings.test
Revision 358238 by nico:
llvm-undname: Don't crash on incomplete enum tag manglings

Found by inspection.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Demangle/MicrosoftDemangle.cpptrunk/lib/Demangle/MicrosoftDemangle.cpp
The file was modified/llvm/trunk/test/Demangle/invalid-manglings.testtrunk/test/Demangle/invalid-manglings.test
Revision 358237 by nico:
llvm-undname: Fix crash on incomplete virtual this adjusts

Found by oss-fuzz.

Also remove an else-after-return, this part has no behavior change.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Demangle/MicrosoftDemangle.cpptrunk/lib/Demangle/MicrosoftDemangle.cpp
The file was modified/llvm/trunk/test/Demangle/invalid-manglings.testtrunk/test/Demangle/invalid-manglings.test
Revision 358236 by nickdesaulniers:
[X86AsmPrinter] refactor static functions into private methods. NFC

Summary:
A lot of the code for printing special cases of operands in this
translation unit are static functions. While I too have suffered many
years of abuse at the hands of C, we should prefer private methods,
particularly when you start passing around *this as your first argument,
which is a code smell.

This will help make generic vs arch specific asm printing easier, as it
brings X86AsmPrinter more in line with other arch's derived AsmPrinters.
We will then be able to more easily move architecture generic code to
the base class, and architecture specific code to the derived classes.

Some other small refactorings while we're here:
- the parameter Op is now consistently OpNo
- add spaces around binary expressions. I know we're not millionaires
  but c'mon.

Reviewers: echristo

Reviewed By: echristo

Subscribers: smeenai, hiraditya, llvm-commits, srhines, craig.topper

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60577
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86AsmPrinter.cpptrunk/lib/Target/X86/X86AsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86AsmPrinter.htrunk/lib/Target/X86/X86AsmPrinter.h
Revision 358234 by nico:
llvm-undname: Fix crash on invalid name in a template parameter pointer to member arg

Found by oss-fuzz.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Demangle/MicrosoftDemangle.cpptrunk/lib/Demangle/MicrosoftDemangle.cpp
The file was modified/llvm/trunk/test/Demangle/invalid-manglings.testtrunk/test/Demangle/invalid-manglings.test
Revision 358233 by bcahoon:
[Pipeliner] Fix incorrect loop carried dependence calculation

The isLoopCarriedDep function does not correctly compute loop
carried dependences when the array index offset is negative
or the stride is smallar than the access size.

Patch by Denis Antrushin.

Differential Revision: https://reviews.llvm.org/D60135
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/MachinePipeliner.cpptrunk/lib/CodeGen/MachinePipeliner.cpp
The file was added/llvm/trunk/test/CodeGen/Hexagon/swp-carried-dep1.mirtrunk/test/CodeGen/Hexagon/swp-carried-dep1.mir
The file was added/llvm/trunk/test/CodeGen/Hexagon/swp-carried-dep2.mirtrunk/test/CodeGen/Hexagon/swp-carried-dep2.mir
The file was modified/llvm/trunk/test/CodeGen/Hexagon/swp-epilog-phi8.lltrunk/test/CodeGen/Hexagon/swp-epilog-phi8.ll
Revision 358229 by nikic:
[CVP] Generate full test checks for overflows.ll; NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/CorrelatedValuePropagation/overflows.lltrunk/test/Transforms/CorrelatedValuePropagation/overflows.ll
Revision 358228 by nikic:
[ConstantRange] Add unsignedMulMayOverflow()

Same as the other ConstantRange overflow checking methods, but for
unsigned mul. In this case there is no cheap overflow criterion, so
using umul_ov for the implementation.

Differential Revision: https://reviews.llvm.org/D60574
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/ConstantRange.htrunk/include/llvm/IR/ConstantRange.h
The file was modified/llvm/trunk/lib/IR/ConstantRange.cpptrunk/lib/IR/ConstantRange.cpp
The file was modified/llvm/trunk/unittests/IR/ConstantRangeTest.cpptrunk/unittests/IR/ConstantRangeTest.cpp
Revision 358227 by nikic:
[ConstantRangeTest] Fix typos in test names; NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/unittests/IR/ConstantRangeTest.cpptrunk/unittests/IR/ConstantRangeTest.cpp
Revision 358226 by pzheng:
[cmake] Fix dependency issue in TableGen

Summary:
There is a bug in add_tablegen which causes cmake to fail with the following
error message if LLVM_TABLEGEN is set.

CMake Error at cmake/modules/TableGen.cmake:147 (add_dependencies):
  The dependency target "LLVM-tablegen-host" of target "CLANG-tablegen-host"
  does not exist.
Call Stack (most recent call first):
  tools/clang/utils/TableGen/CMakeLists.txt:3 (add_tablegen)

The issue happens because setting LLVM_TABLEGEN causes cmake to skip generating
the LLVM-tablegen-host target. As a result, a non-existent target was added for
CLANG-tablegen-host causing cmake to fail.

In order to fix this issue, this patch adds a guard to check the validity of the
dependency target before adding it as a dependency.

Reviewers: aganea, smeenai

Reviewed By: aganea

Subscribers: mgorny, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60576
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/cmake/modules/TableGen.cmaketrunk/cmake/modules/TableGen.cmake
Revision 358225 by xur:
[PGO] Better handling of profile hash mismatch

We currently assume profile hash conflicts will be caught by an upfront
check and we assert for the cases that escape the check. The assumption
is not always true as there are chances of conflict. This patch prints
a warning and skips annotating the function for the escaped cases,.

Differential Revision: https://reviews.llvm.org/D60154
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/Instrumentation/PGOInstrumentation.cpptrunk/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
The file was added/llvm/trunk/test/Transforms/PGOProfile/Inputs/select_hash_conflict.proftexttrunk/test/Transforms/PGOProfile/Inputs/select_hash_conflict.proftext
The file was added/llvm/trunk/test/Transforms/PGOProfile/select_hash_conflict.lltrunk/test/Transforms/PGOProfile/select_hash_conflict.ll
Revision 358223 by Amara Emerson:
[AArch64][GlobalISel] Flesh out vector load/store support for more types.

Some of these were legalizing into smaller vector types unnecessarily,
others were simply not supported yet.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpptrunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mirtrunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mirtrunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
The file was removed/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-vector.mirtrunk/test/CodeGen/AArch64/GlobalISel/legalize-load-vector.mir
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mirtrunk/test/CodeGen/AArch64/GlobalISel/select-load.mir
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-store.mirtrunk/test/CodeGen/AArch64/GlobalISel/select-store.mir
Revision 358221 by Amara Emerson:
[AArch64][GlobalISel] Legalization and ISel support for load/stores of vectors of pointers.

Loads and store of values with type like <2 x p0> currently don't get imported
because SelectionDAG has no knowledge of pointer types. To leverage the existing
support for vector load/stores, we can bitcast the value to have s64 element
types instead. We do this as a custom legalization.

This patch also adds support for general loads of <2 x s64>, and relaxes some
type conditions on selecting G_BITCAST.

Differential Revision: https://reviews.llvm.org/D60534
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpptrunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpptrunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.htrunk/lib/Target/AArch64/AArch64LegalizerInfo.h
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.lltrunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mirtrunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir
The file was added/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mirtrunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
The file was added/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mirtrunk/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mirtrunk/test/CodeGen/AArch64/GlobalISel/select-load.mir
Revision 358220 by asmith:
[DebugInfo] Combine Trivial and NonTrivial flags

Summary:
Companion to https://reviews.llvm.org/D59347


Reviewers: rnk, zturner, probinson, dblaikie, deadalnix

Subscribers: aprantl, jdoerfert, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59348
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm-c/DebugInfo.htrunk/include/llvm-c/DebugInfo.h
The file was modified/llvm/trunk/include/llvm/IR/DebugInfoFlags.deftrunk/include/llvm/IR/DebugInfoFlags.def
The file was modified/llvm/trunk/test/CodeGen/X86/pr39243.lltrunk/test/CodeGen/X86/pr39243.ll
The file was modified/llvm/trunk/test/DebugInfo/COFF/class-options-common.lltrunk/test/DebugInfo/COFF/class-options-common.ll
The file was modified/llvm/trunk/test/DebugInfo/COFF/enum-co.lltrunk/test/DebugInfo/COFF/enum-co.ll
The file was modified/llvm/trunk/test/DebugInfo/COFF/frameproc-flags.lltrunk/test/DebugInfo/COFF/frameproc-flags.ll
The file was modified/llvm/trunk/test/DebugInfo/COFF/function-options.lltrunk/test/DebugInfo/COFF/function-options.ll
The file was modified/llvm/trunk/test/DebugInfo/COFF/global_visibility.lltrunk/test/DebugInfo/COFF/global_visibility.ll
The file was modified/llvm/trunk/test/DebugInfo/COFF/types-method-ref-qualifiers.lltrunk/test/DebugInfo/COFF/types-method-ref-qualifiers.ll
The file was modified/llvm/trunk/test/DebugInfo/COFF/types-this-not-ptr.lltrunk/test/DebugInfo/COFF/types-this-not-ptr.ll
The file was modified/llvm/trunk/test/DebugInfo/COFF/udts-complete.lltrunk/test/DebugInfo/COFF/udts-complete.ll
The file was modified/llvm/trunk/test/DebugInfo/X86/nested_types.lltrunk/test/DebugInfo/X86/nested_types.ll
The file was modified/llvm/trunk/test/DebugInfo/X86/template_function_decl.lltrunk/test/DebugInfo/X86/template_function_decl.ll
The file was modified/llvm/trunk/test/DebugInfo/X86/v5-loc.lltrunk/test/DebugInfo/X86/v5-loc.ll
Revision 358218 by ctopper:
[X86] Restrict vselect handling in scalarizeExtEltFP to only case to pre type legalization where the setcc result type is vXi1.

If the vector setcc has been legalized then we will need to convert a vector boolean of 0 or -1 to a scalar boolean of 0 or 1.

The added test case previously crashed in 32-bit mode by creating a setcc with an i64 condition that type legalization couldn't expand.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/extractelement-fp.lltrunk/test/CodeGen/X86/extractelement-fp.ll
Revision 358217 by ctopper:
[X86] Add 32-bit command line to extractelement-fp.ll so I can add a test case for a 32-bit only crasher. NFC

This is a bit ugly for ABI reasons about how floats/doubles are returned.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/extractelement-fp.lltrunk/test/CodeGen/X86/extractelement-fp.ll
Revision 358215 by ctopper:
[X86] Add patterns for using movss/movsd for atomic load/store of f32/64. Remove atomic fadd pseudos use isel patterns instead.

This patch adds patterns for turning bitcasted atomic load/store into movss/sd.

It also removes the pseudo instructions for atomic RMW fadd. Instead just adding isel patterns for folding an atomic load into addss/sd. And relying on the new movss/sd store pattern to handle the write part.

This also makes the fadd patterns use VEX and EVEX instructions when AVX or AVX512F are enabled.

Differential Revision: https://reviews.llvm.org/D60394
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86InstrCompiler.tdtrunk/lib/Target/X86/X86InstrCompiler.td
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-fp.lltrunk/test/CodeGen/X86/atomic-fp.ll
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-non-integer.lltrunk/test/CodeGen/X86/atomic-non-integer.ll
Revision 358214 by ctopper:
Recommit r358211 "[X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87, but no SSE2"

With correct test checks this time.

If we have X87, but not SSE2 we can atomicaly load an i64 value into the significand of an 80-bit extended precision x87 register using fild. We can then use a fist instruction to convert it back to an i64 integ

This matches what gcc and icc do for this case and removes an existing FIXME.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.htrunk/lib/Target/X86/X86ISelLowering.h
The file was modified/llvm/trunk/lib/Target/X86/X86InstrFPStack.tdtrunk/lib/Target/X86/X86InstrFPStack.td
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-fp.lltrunk/test/CodeGen/X86/atomic-fp.ll
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-load-store-wide.lltrunk/test/CodeGen/X86/atomic-load-store-wide.ll
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-mi.lltrunk/test/CodeGen/X86/atomic-mi.ll
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-non-integer.lltrunk/test/CodeGen/X86/atomic-non-integer.ll
The file was modified/llvm/trunk/test/CodeGen/X86/misched_phys_reg_assign_order.lltrunk/test/CodeGen/X86/misched_phys_reg_assign_order.ll
Revision 358212 by ctopper:
Revert r358211 "[X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87, but no SSE2"

I seem to have messed up the test checks.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.htrunk/lib/Target/X86/X86ISelLowering.h
The file was modified/llvm/trunk/lib/Target/X86/X86InstrFPStack.tdtrunk/lib/Target/X86/X86InstrFPStack.td
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-fp.lltrunk/test/CodeGen/X86/atomic-fp.ll
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-load-store-wide.lltrunk/test/CodeGen/X86/atomic-load-store-wide.ll
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-mi.lltrunk/test/CodeGen/X86/atomic-mi.ll
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-non-integer.lltrunk/test/CodeGen/X86/atomic-non-integer.ll
The file was modified/llvm/trunk/test/CodeGen/X86/misched_phys_reg_assign_order.lltrunk/test/CodeGen/X86/misched_phys_reg_assign_order.ll
Revision 358211 by ctopper:
[X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87, but no SSE2

If we have X87, but not SSE2 we can atomicaly load an i64 value into the significand of an 80-bit extended precision x87 register using fild. We can then use a fist instruction to convert it back to an i64 integer and store it to a stack temporary. From there we can do two 32-bit loads to get the value into integer registers without worrying about atomicness.

This matches what gcc and icc do for this case and removes an existing FIXME.

Differential Revision: https://reviews.llvm.org/D60156
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.htrunk/lib/Target/X86/X86ISelLowering.h
The file was modified/llvm/trunk/lib/Target/X86/X86InstrFPStack.tdtrunk/lib/Target/X86/X86InstrFPStack.td
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-fp.lltrunk/test/CodeGen/X86/atomic-fp.ll
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-load-store-wide.lltrunk/test/CodeGen/X86/atomic-load-store-wide.ll
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-mi.lltrunk/test/CodeGen/X86/atomic-mi.ll
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-non-integer.lltrunk/test/CodeGen/X86/atomic-non-integer.ll
The file was modified/llvm/trunk/test/CodeGen/X86/misched_phys_reg_assign_order.lltrunk/test/CodeGen/X86/misched_phys_reg_assign_order.ll
Revision 358210 by ctopper:
[X86] Pre-commit i64 volatile test case for D60156. NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-load-store-wide.lltrunk/test/CodeGen/X86/atomic-load-store-wide.ll
Revision 358199 by tamur:
Revert "Use llvm::lower_bound. NFC"

This reverts commit rL358161.

This patch have broken the test:
llvm/test/tools/llvm-exegesis/X86/uops-CMOV16rm-noreg.s
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/DebugInfo/DWARF/DWARFUnit.htrunk/include/llvm/DebugInfo/DWARF/DWARFUnit.h
The file was modified/llvm/trunk/lib/Analysis/TargetLibraryInfo.cpptrunk/lib/Analysis/TargetLibraryInfo.cpp
The file was modified/llvm/trunk/lib/Bitcode/Reader/ValueList.cpptrunk/lib/Bitcode/Reader/ValueList.cpp
The file was modified/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpptrunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modified/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpptrunk/lib/CodeGen/RegAllocGreedy.cpp
The file was modified/llvm/trunk/lib/DebugInfo/DWARF/DWARFDebugLoc.cpptrunk/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp
The file was modified/llvm/trunk/lib/Transforms/Utils/LowerSwitch.cpptrunk/lib/Transforms/Utils/LowerSwitch.cpp
The file was modified/llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpptrunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
The file was modified/llvm/trunk/tools/llvm-exegesis/lib/BenchmarkResult.cpptrunk/tools/llvm-exegesis/lib/BenchmarkResult.cpp
Revision 358198 by zturner:
Fix sphinx documentation warning.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/AddingConstrainedIntrinsics.rsttrunk/docs/AddingConstrainedIntrinsics.rst
Revision 358197 by zturner:
[PDB Docs] Add skeleton of documentation for CodeView symbols.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/PDB/CodeViewSymbols.rsttrunk/docs/PDB/CodeViewSymbols.rst
The file was modified/llvm/trunk/docs/PDB/CodeViewTypes.rsttrunk/docs/PDB/CodeViewTypes.rst
Revision 358194 by kpn:
New document skeleton describing how to add a constrained floating-point
intrinsic.

Reviewed by: andrew.w.kaylor, cameron.mcinally
Differential Revision: https://reviews.llvm.org/D59833
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/docs/AddingConstrainedIntrinsics.rsttrunk/docs/AddingConstrainedIntrinsics.rst
The file was modified/llvm/trunk/docs/index.rsttrunk/docs/index.rst
Revision 358192 by rksimon:
[ConstantFold] ExtractConstantBytes - handle shifts on large integer types

Use APInt instead of getZExtValue from the ConstantInt until we can confirm that the shift amount is in range.

Reduced from OSS-Fuzz #14169 - https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=14169
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/IR/ConstantFold.cpptrunk/lib/IR/ConstantFold.cpp
The file was added/llvm/trunk/test/Transforms/InstCombine/constant-fold-shifts.lltrunk/test/Transforms/InstCombine/constant-fold-shifts.ll
Revision 358187 by spatel:
[DAGCombiner] refactor narrowing of extracted vector binop; NFC

There's a TODO comment about handling patterns with insert_subvector,
and we do want to match that.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpptrunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Revision 358186 by rksimon:
[X86] SimplifyDemandedVectorElts - add X86ISD::VPERMV3 mask support

Completes SimplifyDemandedVectorElts's basic variable shuffle mask support which should help D60512 + D60562
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx512bw.lltrunk/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
Revision 358185 by serge_sans_paille:
Make llvm-nm -help great again

Only display help from the llvm-nm category instead of all llvm options, which make it much more usable.
There's still an issue with -s, which is probably a bug in llvm::cl and worth another commit.

Differential Revision: https://reviews.llvm.org/D60411
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/tools/llvm-nm/help.testtrunk/test/tools/llvm-nm/help.test
The file was modified/llvm/trunk/tools/llvm-nm/llvm-nm.cpptrunk/tools/llvm-nm/llvm-nm.cpp
Revision 358183 by rogfer01:
[RISCV] Diagnose invalid second input register operand when using %tprel_add

RISCVMCCodeEmitter::expandAddTPRel asserts that the second operand must be
x4/tp. As we are not currently checking this in the RISCVAsmParser, the assert
is easy to trigger due to wrong assembly input.

This patch does a late check of this constraint.

An alternative could be using a singleton register class for x4/tp similar to
the current one for sp. Unfortunately it does not result in a good diagnostic.
Because add is an overloaded mnemonic, if no matching is possible, the
diagnostic of the first failing alternative seems to be used as the diagnostic
itself. This means that this case the %tprel_add is diagnosed as an invalid
operand (because the real add instruction only has 3 operands).

Differential Revision: https://reviews.llvm.org/D60528
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpptrunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modified/llvm/trunk/test/MC/RISCV/rv32i-invalid.strunk/test/MC/RISCV/rv32i-invalid.s
Revision 358182 by rksimon:
[X86][AVX] Tweak X86ISD::VPERMV3 demandedelts test

Original test was too dependent on the order of the combines that could cause the inserted element being demanded after all
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx512bw.lltrunk/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
Revision 358179 by luoyuanke:
[X86] Add MM register mapping from CodeView to MC register id

Differential Revision: https://reviews.llvm.org/D60437

Change-Id: I2183a6d825d0284b22705d423b88882992b236c5
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpptrunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
Revision 358177 by mgorny:
[llvm] [lit] Add target-x86* features

Add a 'target-x86' and 'target-x86_64' feature sthat indicates that
the default target is 32-bit or 64-bit x86, appropriately.  Combined
with 'native' feature, we're going to use this to control x86-specific
LLDB native process tests.

Differential Revision: https://reviews.llvm.org/D60474
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/utils/lit/lit/llvm/config.pytrunk/utils/lit/lit/llvm/config.py
Revision 358176 by labath:
YAMLIO: Fix serialization of strings with embedded nuls

Summary:
A bug/typo in Output::scalarString caused us to round-trip a StringRef
through a const char *. This meant that any strings with embedded nuls
were unintentionally cut short at the first such character. (It also
could have caused accidental buffer overruns, but it seems that all
StringRefs coming into this functions were formed from null-terminated
strings.)

This patch fixes the bug and adds an appropriate test.

Reviewers: sammccall, jhenderson

Subscribers: kristina, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60505
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Support/YAMLTraits.cpptrunk/lib/Support/YAMLTraits.cpp
The file was modified/llvm/trunk/unittests/Support/YAMLIOTest.cpptrunk/unittests/Support/YAMLIOTest.cpp
Revision 358175 by rksimon:
[X86][AVX] Add X86ISD::VPERMV3 demandedelts test
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx512bw.lltrunk/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
Revision 358174 by rksimon:
[X86] SimplifyDemandedVectorElts - add X86ISD::VPERMV mask support
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx2.lltrunk/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
Revision 358173 by rksimon:
[X86][AVX] Add X86ISD::VPERMV demandedelts test
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx2.lltrunk/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
Revision 358172 by spatel:
[DAGCombiner][x86] scalarize inserted vector FP ops

// bo (build_vec ...undef, x, undef...), (build_vec ...undef, y, undef...) -->
// build_vec ...undef, (bo x, y), undef...

The lifetime of the nodes in these examples is different for variables versus constants,
but they are all build vectors briefly, so I'm proposing to catch them in this form to
handle all of the leading examples in the motivating test file.

Before we have build vectors, we might have insert_vector_element. After that, we might
have scalar_to_vector and constant pool loads.

It's going to take more work to ensure that FP vector operands are getting simplified
with undef elements, so this transform can apply more widely. In a non-loose FP environment,
we are likely simplifying FP elements to NaN values rather than undefs.

We also need to allow more opcodes down this path. Eg, we don't handle FP min/max flavors
yet.

Differential Revision: https://reviews.llvm.org/D60514
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpptrunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/scalarize-fp.lltrunk/test/CodeGen/X86/scalarize-fp.ll
Revision 358171 by dnsampaio:
[AArch64] Add lowering pattern for llvm.aarch64.neon.vcvtfxs2fp.f16.i64

Summary:  Add lowering pattern for llvm.aarch64.neon.vcvtfxs2fp.f16.i64

Reviewers: pbarrio, DavidSpickett, LukeGeeson

Reviewed By: LukeGeeson

Subscribers: javed.absar, kristof.beyls, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60259
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.tdtrunk/lib/Target/AArch64/AArch64InstrInfo.td
The file was modified/llvm/trunk/test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.lltrunk/test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll
Revision 358170 by rksimon:
[X86] SimplifyDemandedVectorElts - add X86ISD::VPERMILPV mask support
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx.lltrunk/test/CodeGen/X86/vector-shuffle-combining-avx.ll
Revision 358168 by rksimon:
[X86][AVX] Add X86ISD::VPERMILPV demandedelts tests
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx.lltrunk/test/CodeGen/X86/vector-shuffle-combining-avx.ll
Revision 358167 by rksimon:
[X86] SimplifyDemandedVectorElts - add X86ISD::VPERMIL2 mask support
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-xop.lltrunk/test/CodeGen/X86/vector-shuffle-combining-xop.ll
Revision 358166 by rksimon:
[X86][XOP] Add X86ISD::VPERMIL2 demandedelts test
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-xop.lltrunk/test/CodeGen/X86/vector-shuffle-combining-xop.ll
Revision 358165 by rksimon:
[X86] SimplifyDemandedVectorElts - add VPPERM support

We need to add support for all variable shuffle mask ops, but VPPERM is the only one that already has test coverage.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/oddshuffles.lltrunk/test/CodeGen/X86/oddshuffles.ll
Revision 358163 by s.desmalen:
[ValueTracking] Change if-else chain into switch in computeKnownBitsFromAssume
   
This is a follow-up patch to D60504 to further improve
performance issues in computeKnownBitsFromAssume.
   
The patch is NFC, but may improve compile-time performance
if the compiler isn't clever enough to do the optimization
itself.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Analysis/ValueTracking.cpptrunk/lib/Analysis/ValueTracking.cpp
Revision 358162 by ostannard:
Test commit access
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpptrunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Revision 358161 by maskray:
Use llvm::lower_bound. NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/DebugInfo/DWARF/DWARFUnit.htrunk/include/llvm/DebugInfo/DWARF/DWARFUnit.h
The file was modified/llvm/trunk/lib/Analysis/TargetLibraryInfo.cpptrunk/lib/Analysis/TargetLibraryInfo.cpp
The file was modified/llvm/trunk/lib/Bitcode/Reader/ValueList.cpptrunk/lib/Bitcode/Reader/ValueList.cpp
The file was modified/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpptrunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modified/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpptrunk/lib/CodeGen/RegAllocGreedy.cpp
The file was modified/llvm/trunk/lib/DebugInfo/DWARF/DWARFDebugLoc.cpptrunk/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp
The file was modified/llvm/trunk/lib/Transforms/Utils/LowerSwitch.cpptrunk/lib/Transforms/Utils/LowerSwitch.cpp
The file was modified/llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpptrunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
The file was modified/llvm/trunk/tools/llvm-exegesis/lib/BenchmarkResult.cpptrunk/tools/llvm-exegesis/lib/BenchmarkResult.cpp
Revision 358160 by adibiagio:
[MCA] Remove wrong comments from a test. NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/int-to-fpu-forwarding-2.strunk/test/tools/llvm-mca/X86/BtVer2/int-to-fpu-forwarding-2.s
Revision 358158 by ibiryukov:
[ADT] Fix template parameter names of llvm::{upper|lower}_bound

Summary:
Rename template parameter for a search value from 'ForwardIt' to 'T'.
While here, also use perfect forwarding to pass the value to STL algos.

Reviewers: sammccall

Reviewed By: sammccall

Subscribers: dexonsmith, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60510
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/ADT/STLExtras.htrunk/include/llvm/ADT/STLExtras.h
Revision 358156 by hans:
try to fix the sphinx build some more
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl01.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl01.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl02.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl02.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl03.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl03.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl04.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl04.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl05.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl05.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl06.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl06.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl07.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl07.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl09.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl09.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl10.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl10.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/index.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/index.rst
Revision 358154 by hans:
Try to fix the shpinx build
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/tutorial/LangImpl02.rsttrunk/docs/tutorial/LangImpl02.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl02.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl02.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl03.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl03.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl04.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl04.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl05.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl05.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl06.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl06.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl07.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl07.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl09.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl09.rst
Revision 358153 by lebedevri:
[llvm-exegesis] Fix serialization/deserialization of special NoRegister register (PR41448)

Summary:
A *lot* of instructions have this special register.
It seems this never really worked, but i finally noticed it only
because it happened to break for `CMOV16rm` instruction.

We serialized that register as "" (empty string), which is naturally
'ignored' during deserialization, so we re-create a `MCInst` with
too few operands.

And when we then happened to try to resolve variant sched class
for this mis-serialized instruction, and the variant predicate
tried to read an operand that was out of bounds since we got less operands,
we crashed.

Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=41448 | PR41448 ]].

Reviewers: craig.topper, courbet

Reviewed By: courbet

Subscribers: tschuett, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60517
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/tools/llvm-exegesis/X86/uops-CMOV16rm-noreg.strunk/test/tools/llvm-exegesis/X86/uops-CMOV16rm-noreg.s
The file was modified/llvm/trunk/tools/llvm-exegesis/lib/BenchmarkResult.cpptrunk/tools/llvm-exegesis/lib/BenchmarkResult.cpp
Revision 358150 by shiva:
[RISCV] Put data smaller than eight bytes to small data section

Because of gp = sdata_start_address + 0x800, gp with signed twelve-bit offset
could covert most of the small data section. Linker relaxation could transfer
the multiple data accessing instructions to a gp base with signed twelve-bit
offset instruction.

Differential Revision: https://reviews.llvm.org/D57493
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.htrunk/include/llvm/Target/TargetLoweringObjectFile.h
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpptrunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/RISCV/RISCVTargetObjectFile.cpptrunk/lib/Target/RISCV/RISCVTargetObjectFile.cpp
The file was modified/llvm/trunk/lib/Target/RISCV/RISCVTargetObjectFile.htrunk/lib/Target/RISCV/RISCVTargetObjectFile.h
The file was added/llvm/trunk/test/CodeGen/RISCV/sdata-limit-0.lltrunk/test/CodeGen/RISCV/sdata-limit-0.ll
The file was added/llvm/trunk/test/CodeGen/RISCV/sdata-limit-4.lltrunk/test/CodeGen/RISCV/sdata-limit-4.ll
The file was added/llvm/trunk/test/CodeGen/RISCV/sdata-limit-8.lltrunk/test/CodeGen/RISCV/sdata-limit-8.ll
The file was added/llvm/trunk/test/CodeGen/RISCV/sdata-local-sym.lltrunk/test/CodeGen/RISCV/sdata-local-sym.ll
Revision 358148 by maskray:
[DWARF] Set discriminator to 0 for DW_LNS_copy

Summary:
Make DW_LNS_copy set the discriminator register to 0, to conform to
DWARF 4 & 5: "Then it sets the discriminator register to 0, and sets the
basic_block, prologue_end and epilogue_begin registers to false."

Because all of DW_LNE_end_sequence, DN_LNS_copy, and special opcodes reset
discriminator to 0, we can move discriminator=0 to appendRowToMatrix.

Also, make DW_LNS_copy print before appending the row, as it is similar
to a address+=0,line+=0 special opcode, which prints before appending
the row.

Reviewers: dblaikie, probinson, aprantl

Reviewed By: dblaikie

Subscribers: danielcdh, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60364
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/DebugInfo/DWARF/DWARFDebugLine.cpptrunk/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
The file was added/llvm/trunk/test/tools/llvm-dwarfdump/X86/debug-line-dw-lns-copy.strunk/test/tools/llvm-dwarfdump/X86/debug-line-dw-lns-copy.s
Revision 358146 by epilk:
Fix a hang when lowering __builtin_dynamic_object_size

If the ObjectSizeOffsetEvaluator fails to fold the object size call, then it may
litter some unused instructions in the function. When done repeatably in
InstCombine, this results in an infinite loop. Fix this by tracking the set of
instructions that were inserted, then removing them on failure.

rdar://49172227

Differential revision: https://reviews.llvm.org/D60298
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Analysis/MemoryBuiltins.htrunk/include/llvm/Analysis/MemoryBuiltins.h
The file was modified/llvm/trunk/lib/Analysis/MemoryBuiltins.cpptrunk/lib/Analysis/MemoryBuiltins.cpp
The file was modified/llvm/trunk/test/Instrumentation/BoundsChecking/phi.lltrunk/test/Instrumentation/BoundsChecking/phi.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/builtin-dynamic-object-size.lltrunk/test/Transforms/InstCombine/builtin-dynamic-object-size.ll
Revision 358144 by Amara Emerson:
[AArch64][GlobalISel] Make <2 x p0> = G_BUILD_VECTOR legal.

The existing isel support already works for p0 once the legalizer accepts it.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpptrunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mirtrunk/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-build-vector.mirtrunk/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
Revision 358143 by Amara Emerson:
[AArch64][GlobalISel] Add legalizer support for <8 x s16> and <16 x s8> G_ADD.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpptrunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mirtrunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-binop.mirtrunk/test/CodeGen/AArch64/GlobalISel/select-binop.mir
Revision 358142 by Amara Emerson:
[AArch64][GlobalISel] Scalarize vector SDIV.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpptrunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpptrunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mirtrunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
Revision 358141 by ctopper:
[X86] Add SSE1 command line to atomic-fp.ll and atomic-non-integer.ll. NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-fp.lltrunk/test/CodeGen/X86/atomic-fp.ll
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-non-integer.lltrunk/test/CodeGen/X86/atomic-non-integer.ll
Revision 358140 by ctopper:
[X86] Autogenerate complete checks. NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/atomic6432.lltrunk/test/CodeGen/X86/atomic6432.ll
Revision 358139 by ctopper:
[X86] Teach foldMaskedShiftToScaledMask to look through an any_extend from i32 to i64 between the and & shl

foldMaskedShiftToScaledMask tries to reorder and & shl to enable the shl to fold into an LEA. But if there is an any_extend between them it doesn't work.

This patch modifies the code to look through any_extend from i32 to i64 when the and mask only uses bits that weren't from the extended part.

This will prevent a regression from D60358 caused by 64-bit SHL being narrowed to 32-bits when their upper bits aren't demanded.

Differential Revision: https://reviews.llvm.org/D60532
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpptrunk/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/fold-and-shift-x86_64.lltrunk/test/CodeGen/X86/fold-and-shift-x86_64.ll
Revision 358138 by ctopper:
[X86] Make _Int instructions the preferred instructon for the assembly parser and disassembly parser to remove inconsistencies between VEX and EVEX.

Many of our instructions have both a _Int form used by intrinsics and a form
used by other IR constructs. In the EVEX space the _Int versions usually cover
all the capabilities include broadcasting and rounding. While the other version
only covers simple register/register or register/load forms. For this reason
in EVEX, the non intrinsic form is usually marked isCodeGenOnly=1.

In the VEX encoding space we were less consistent, but usually the _Int version
was the isCodeGenOnly version.

This commit makes the VEX instructions match the EVEX instructions. This was
done by manually studying the AsmMatcher table so its possible I missed some
cases, but we should be closer now.

I'm thinking about using the isCodeGenOnly bit to simplify the EVEX2VEX
tablegen code that disambiguates the _Int and non _Int versions. Currently it
checks register class sizes and Record the memory operands come from. I have
some other changes I was looking into for D59266 that may break the memory check.

I had to make a few scheduler hacks to keep the _Int versions from being treated
differently than the non _Int version.

Differential Revision: https://reviews.llvm.org/D60441
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.tdtrunk/lib/Target/X86/X86InstrAVX512.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrFMA.tdtrunk/lib/Target/X86/X86InstrFMA.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrSSE.tdtrunk/lib/Target/X86/X86InstrSSE.td
The file was modified/llvm/trunk/lib/Target/X86/X86SchedBroadwell.tdtrunk/lib/Target/X86/X86SchedBroadwell.td
The file was modified/llvm/trunk/lib/Target/X86/X86SchedHaswell.tdtrunk/lib/Target/X86/X86SchedHaswell.td
The file was modified/llvm/trunk/lib/Target/X86/X86ScheduleBdVer2.tdtrunk/lib/Target/X86/X86ScheduleBdVer2.td
The file was modified/llvm/trunk/test/tools/llvm-mca/X86/BdVer2/int-to-fpu-forwarding-2.strunk/test/tools/llvm-mca/X86/BdVer2/int-to-fpu-forwarding-2.s
The file was modified/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/int-to-fpu-forwarding-2.strunk/test/tools/llvm-mca/X86/BtVer2/int-to-fpu-forwarding-2.s
Revision 358128 by dmgreen:
[ARM] Add an extra test for constant hoist. NFC
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/CodeGen/Thumb2/constant-hoisting.lltrunk/test/CodeGen/Thumb2/constant-hoisting.ll
Revision 358124 by ctopper:
[X86] Add test case for LEA formation regression seen with D60358. NFC

If we have an (add X, (and (aext (shl Y, C1)), C2)), we can pull the shift through and+aext to fold into an LEA with the.
Assuming C1 is small enough and C2 masks off all of the extend bits.

This pattern showed up in D60358. And we need to handle it to prevent a regression.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/fold-and-shift-x86_64.lltrunk/test/CodeGen/X86/fold-and-shift-x86_64.ll
Revision 358123 by ctopper:
[X86] Replace some if statements in isel address matching that should never be true with asserts. And move them earlier before we looked through operands that don't change size. NFC

These ifs were ensuring we don't have to handle types larger than 64 bits probably because we use getZExtValue in several places below them.

None of the callers of this code pass types larger than 64-bits so we can just assert instead of branching in release code.

I've also moved them earlier since we're just looking through operations that don't effect bit width.

This is prep work for some refactoring I plan to do to the (and (shl)) handling code.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpptrunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Revision 358122 by nickdesaulniers:
[X86AsmPrinter] refactor to limit use of Modifier. NFC

Summary:
The Modifier memory operands is used in 2 cases of memory references
(H & P ExtraCodes). Rather than pass around the likely nullptr Modifier,
refactor the handling of the Modifier out from printOperand().

The refactorings in this patch:
- Don't forward declare printOperand, move its definition up.
  - The diff makes it look like there's a change to printPCRelImm
    (narrator: there's not).
- Create printModifiedOperand()
  - Move logic for Modifier to there from printOperand
  - Use printModifiedOperand in 3 call sites that actually create
    Modifiers.
- Remove now unused Modifier parameter from printOperand
- Remove default parameter from printLeaMemReference as it only has 1
  call site that explicitly passes a parameter.
- Remove default parameter from printMemReference, make call lone call
  site explicitly pass nullptr.
- Drop Modifier parameter from printIntelMemReference, as Intel style
  memory references don't support the Modifiers in question.

This will allow future changes to printOperand() to make it a pure virtual
method on the base AsmPrinter class, allowing for more generic handling
of some architecture generic constraints. X86AsmPrinter was the only
derived class of AsmPrinter to have additional parameters on its
printOperand function.

Reviewers: craig.topper, echristo

Reviewed By: echristo

Subscribers: hiraditya, llvm-commits, srhines

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60526
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86AsmPrinter.cpptrunk/lib/Target/X86/X86AsmPrinter.cpp
Revision 358120 by tamur:
[llvm] Non-functional change: declared a local variable as const.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/MC/MCAsmStreamer.cpptrunk/lib/MC/MCAsmStreamer.cpp
Revision 358119 by zturner:
[PDB Docs] Start documenting CodeView Type Records.

This puts the general layout of the document in place and fully
describes 1 simple type record.  Followups will fill out more
pieces.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/PDB/CodeViewTypes.rsttrunk/docs/PDB/CodeViewTypes.rst
Revision 358118 by lebedevri:
[X86] X86ScheduleBdVer2: use !listsplat operator to cleanup loadres calculation

The problem is that one can't concatenate an empty list
(implied all-ones) with non-empty list here. The result
will be the non-empty list, and it won't match the length
of the ExePorts list.

The problems begin when LoadRes != 1 here,
which is the case in PdWriteResYMMPair,
and more importantly i think it will be the case for PdWriteResExPair.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ScheduleBdVer2.tdtrunk/lib/Target/X86/X86ScheduleBdVer2.td
Revision 358117 by lebedevri:
[TableGen] Introduce !listsplat 'binary' operator

Summary:
```
``!listsplat(a, size)``
    A list value that contains the value ``a`` ``size`` times.
    Example: ``!listsplat(0, 2)`` results in ``[0, 0]``.
```

I plan to use this in X86ScheduleBdVer2.td for LoadRes handling.

This is a little bit controversial because unlike every other binary operator
the types aren't identical.

Reviewers: stoklund, javed.absar, nhaehnle, craig.topper

Reviewed By: javed.absar

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60367
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/TableGen/LangIntro.rsttrunk/docs/TableGen/LangIntro.rst
The file was modified/llvm/trunk/docs/TableGen/LangRef.rsttrunk/docs/TableGen/LangRef.rst
The file was modified/llvm/trunk/include/llvm/TableGen/Record.htrunk/include/llvm/TableGen/Record.h
The file was modified/llvm/trunk/lib/TableGen/Record.cpptrunk/lib/TableGen/Record.cpp
The file was modified/llvm/trunk/lib/TableGen/TGLexer.cpptrunk/lib/TableGen/TGLexer.cpp
The file was modified/llvm/trunk/lib/TableGen/TGLexer.htrunk/lib/TableGen/TGLexer.h
The file was modified/llvm/trunk/lib/TableGen/TGParser.cpptrunk/lib/TableGen/TGParser.cpp
The file was added/llvm/trunk/test/TableGen/listsplat.tdtrunk/test/TableGen/listsplat.td
The file was modified/llvm/trunk/utils/kate/llvm-tablegen.xmltrunk/utils/kate/llvm-tablegen.xml
Revision 358116 by lebedevri:
[kate] Add '!mul' operator that was introduced in D58775
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/utils/kate/llvm-tablegen.xmltrunk/utils/kate/llvm-tablegen.xml
Revision 358114 by dmgreen:
[ARM] Add an extra constant hoisting test. NFC

This adds a simple extra test for constant hoisting to show it's
usefulness with constant addresses like those seen in memory
mapped registers in embedded systems.
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/CodeGen/Thumb/consthoist-physical-addr.lltrunk/test/CodeGen/Thumb/consthoist-physical-addr.ll
Revision 358113 by dmgreen:
Revert rL357745: [SelectionDAG] Compute known bits of CopyFromReg

Certain optimisations from ConstantHoisting and CGP rely on Selection DAG not
seeing through to the constant in other blocks. Revert this patch while we come
up with a better way to handle that.

I will try to follow this up with some better tests.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpptrunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.lltrunk/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
The file was modified/llvm/trunk/test/CodeGen/ARM/atomic-op.lltrunk/test/CodeGen/ARM/atomic-op.ll
The file was modified/llvm/trunk/test/CodeGen/PowerPC/pr35688.lltrunk/test/CodeGen/PowerPC/pr35688.ll
The file was modified/llvm/trunk/test/CodeGen/SystemZ/subregliveness-04.lltrunk/test/CodeGen/SystemZ/subregliveness-04.ll
The file was modified/llvm/trunk/test/CodeGen/X86/fold-tied-op.lltrunk/test/CodeGen/X86/fold-tied-op.ll
The file was modified/llvm/trunk/test/CodeGen/X86/pr28444.lltrunk/test/CodeGen/X86/pr28444.ll
Revision 358112 by nico:
llvm-undname: Fix another crash-on-invalid

This fixes a regression from https://reviews.llvm.org/D60354. We used to

  SymbolNode *Symbol = demangleEncodedSymbol(MangledName, QN);
  if (Symbol) {
    Symbol->Name = QN;
  }

but changed that to
  SymbolNode *Symbol = demangleEncodedSymbol(MangledName, QN);
  if (Error)
    return nullptr;
  Symbol->Name = QN;

and one branch somewhere returned a nullptr without setting Error.

Looking at the code changed in r340083 and r340710 that branch looks
like a remnant from an earlier attempt to demangle RTTI descriptors
that has since been rewritten -- so just remove this branch. It
shouldn't change behavior for correctly mangled symbols.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Demangle/MicrosoftDemangle.cpptrunk/lib/Demangle/MicrosoftDemangle.cpp
The file was modified/llvm/trunk/test/Demangle/invalid-manglings.testtrunk/test/Demangle/invalid-manglings.test
Revision 358111 by arsenm:
GlobalISel: Move computeValueLLTs

Call lowering should use this directly instead of going through the
EVT version, but more work is needed to deal with this (mostly the
passing of the IR type pointer instead of the relevant properties in
ArgInfo).
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/Analysis.htrunk/include/llvm/CodeGen/Analysis.h
The file was modified/llvm/trunk/lib/CodeGen/Analysis.cpptrunk/lib/CodeGen/Analysis.cpp
The file was modified/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpptrunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
Revision 358110 by arsenm:
GlobalISel: Fix invoke lowering creating invalid type registers

Unlike the call handling, this wasn't checking for void results and
creating a register with the invalid LLT
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/GlobalISel/CallLowering.htrunk/include/llvm/CodeGen/GlobalISel/CallLowering.h
The file was modified/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpptrunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
Revision 358109 by arsenm:
GlobalISel: Support legalizing G_CONSTANT with irregular breakdown
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpptrunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.lltrunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mirtrunk/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
Revision 358108 by ctopper:
[AArch64] Teach getTestBitOperand to look through ANY_EXTENDS

This patch teach getTestBitOperand to look through ANY_EXTENDs when the extended bits aren't used. The test case changed here is based what D60358 did to test16 in tbz-tbnz.ll. So this patch will avoid that regression.

Differential Revision: https://reviews.llvm.org/D60482
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpptrunk/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/tbz-tbnz.lltrunk/test/CodeGen/AArch64/tbz-tbnz.ll
Revision 358105 by arsenm:
GlobalISel: Handle odd breakdowns for bit ops
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerHelper.htrunk/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
The file was modified/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpptrunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mirtrunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mirtrunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mirtrunk/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
Revision 358102 by nickdesaulniers:
add FIXME: as per echristo
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/MachineInstr.htrunk/include/llvm/CodeGen/MachineInstr.h
Revision 358101 by nickdesaulniers:
[AsmPrinter] refactor to remove remove AsmVariant. NFC

Summary:
The InlineAsm::AsmDialect is only required for X86; no architecture
makes use of it and as such it gets passed around between arch-specific
and general code while being unused for all architectures but X86.

Since the AsmDialect is queried from a MachineInstr, which we also pass
around, remove the additional AsmDialect parameter and query for it deep
in the X86AsmPrinter only when needed/as late as possible.

This refactor should help later planned refactors to AsmPrinter, as this
difference in the X86AsmPrinter makes it harder to make AsmPrinter more
generic.

Reviewers: craig.topper

Subscribers: jholewinski, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, sbc100, jgravelle-google, eraman, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, llvm-commits, peter.smith, srhines

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60488
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/AsmPrinter.htrunk/include/llvm/CodeGen/AsmPrinter.h
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpptrunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpptrunk/lib/Target/AArch64/AArch64AsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpptrunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.htrunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
The file was modified/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpptrunk/lib/Target/ARM/ARMAsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.htrunk/lib/Target/ARM/ARMAsmPrinter.h
The file was modified/llvm/trunk/lib/Target/AVR/AVRAsmPrinter.cpptrunk/lib/Target/AVR/AVRAsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/BPF/BPFAsmPrinter.cpptrunk/lib/Target/BPF/BPFAsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpptrunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.htrunk/lib/Target/Hexagon/HexagonAsmPrinter.h
The file was modified/llvm/trunk/lib/Target/Lanai/LanaiAsmPrinter.cpptrunk/lib/Target/Lanai/LanaiAsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpptrunk/lib/Target/MSP430/MSP430AsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpptrunk/lib/Target/Mips/MipsAsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.htrunk/lib/Target/Mips/MipsAsmPrinter.h
The file was modified/llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpptrunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.htrunk/lib/Target/NVPTX/NVPTXAsmPrinter.h
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpptrunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/RISCV/RISCVAsmPrinter.cpptrunk/lib/Target/RISCV/RISCVAsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpptrunk/lib/Target/Sparc/SparcAsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpptrunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.htrunk/lib/Target/SystemZ/SystemZAsmPrinter.h
The file was modified/llvm/trunk/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpptrunk/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/WebAssembly/WebAssemblyAsmPrinter.htrunk/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h
The file was modified/llvm/trunk/lib/Target/X86/X86AsmPrinter.cpptrunk/lib/Target/X86/X86AsmPrinter.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86AsmPrinter.htrunk/lib/Target/X86/X86AsmPrinter.h
The file was modified/llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpptrunk/lib/Target/XCore/XCoreAsmPrinter.cpp
Revision 358100 by nikic:
[InstCombine] Handle ssubo always overflow

Following D60483 and D60497, this adds support for AlwaysOverflows
handling for ssubo. This is the last case we can handle right now.

Differential Revision: https://reviews.llvm.org/D60518
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpptrunk/lib/Transforms/InstCombine/InstCombineCompares.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/with_overflow.lltrunk/test/Transforms/InstCombine/with_overflow.ll
Revision 358099 by nikic:
[InstCombine] ssubo X, C -> saddo X, -C

ssubo X, C is equivalent to saddo X, -C. Make the transformation in
InstCombine and allow the logic implemented for saddo to fold prior
usages of add nsw or sub nsw with constants.

Patch by Dan Robertson.

Differential Revision: https://reviews.llvm.org/D60061
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpptrunk/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/ssub-with-overflow.lltrunk/test/Transforms/InstCombine/ssub-with-overflow.ll
Revision 358097 by s.desmalen:
Improve compile-time performance in computeKnownBitsFromAssume.

This patch changes the order of pattern matching by first testing
a compare instruction's predicate, before doing the pattern
match for the whole expression tree.

Patch by Paul Walker.

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D60504
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Analysis/ValueTracking.cpptrunk/lib/Analysis/ValueTracking.cpp
Revision 358096 by rksimon:
[X86][AVX] getTargetConstantBitsFromNode - extract bits from X86ISD::SUBV_BROADCAST
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/combine-bitselect.lltrunk/test/CodeGen/X86/combine-bitselect.ll
Revision 358095 by nikic:
[InstCombine] Handle saddo always overflow

Followup to D60483: Handle AlwaysOverflow conditions for saddo as
well.

Differential Revision: https://reviews.llvm.org/D60497
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpptrunk/lib/Transforms/InstCombine/InstCombineCompares.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/with_overflow.lltrunk/test/Transforms/InstCombine/with_overflow.ll
Revision 358092 by alexfh:
Fix a typo
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm-c/Object.htrunk/include/llvm-c/Object.h
Revision 358089 by maskray:
[MachineOutliner] Replace ostringstream based string concatenation with Twine

This makes my libLLVMCodeGen.so.9svn 4936 bytes smaller.

While here, delete unused #include <map>
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/MachineOutliner.cpptrunk/lib/CodeGen/MachineOutliner.cpp
Revision 358086 by codafi:
[LLVM-C] Correct The Current Debug Location Accessors (Again)

Summary: Resubmitting D60484 with the conflicting Go bindings renamed to avoid collisions.

Reviewers: whitequark, deadalnix

Subscribers: hiraditya, llvm-commits, sammccall

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60511
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/bindings/go/llvm/IRBindings.cpptrunk/bindings/go/llvm/IRBindings.cpp
The file was modified/llvm/trunk/bindings/go/llvm/IRBindings.htrunk/bindings/go/llvm/IRBindings.h
The file was modified/llvm/trunk/bindings/go/llvm/ir.gotrunk/bindings/go/llvm/ir.go
The file was modified/llvm/trunk/include/llvm-c/Core.htrunk/include/llvm-c/Core.h
The file was modified/llvm/trunk/include/llvm-c/DebugInfo.htrunk/include/llvm-c/DebugInfo.h
The file was modified/llvm/trunk/lib/IR/Core.cpptrunk/lib/IR/Core.cpp
The file was modified/llvm/trunk/lib/IR/DebugInfo.cpptrunk/lib/IR/DebugInfo.cpp
Revision 358083 by dnsampaio:
[AArch64] Add lowering pattern for scalar fp16 facge and facgt

Summary: The fp16 scalar version of facge and facgt requires a custom patter matching, as the result type is not the same width of the operands.

Reviewers: olista01, javed.absar, pbarrio

Reviewed By: javed.absar

Subscribers: kristof.beyls, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60212
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.tdtrunk/lib/Target/AArch64/AArch64InstrInfo.td
The file was modified/llvm/trunk/test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.lltrunk/test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll
Revision 358082 by sammccall:
Revert "[LLVM-C] Correct The Current Debug Location Accessors"

This reverts commit r358039, which added symbols that conflict with the
Go bindings.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm-c/Core.htrunk/include/llvm-c/Core.h
The file was modified/llvm/trunk/lib/IR/Core.cpptrunk/lib/IR/Core.cpp
Revision 358081 by dnsampaio:
[ARM] [FIX] Add missing f16 vector operations lowering

Summary:
Add missing <8xhalf> shufflevectors pattern, when using concat_vector dag node.
As well, allows <8xhalf> and <4xhalf> vldup1 operations.

These instructions are required for v8.2a fp16 lowering of vmul_n_f16, vmulq_n_f16 and vmulq_lane_f16 intrinsics.

Reviewers: olista01, pbarrio, LukeGeeson, efriedma

Reviewed By: efriedma

Subscribers: efriedma, javed.absar, kristof.beyls, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60319
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpptrunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstrNEON.tdtrunk/lib/Target/ARM/ARMInstrNEON.td
The file was modified/llvm/trunk/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.lltrunk/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
Revision 358080 by courbet:
[NFC] Fix unused variable warning.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpptrunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
Revision 358079 by lebedevri:
[llvm-exegesis] Pacify bots - don't std::move() - prevents copy elision
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-exegesis/lib/BenchmarkResult.cpptrunk/tools/llvm-exegesis/lib/BenchmarkResult.cpp
Revision 358078 by Xing:
[llvm-readobj] Should declare `ListScope` for `verneed` entries.

Summary: YAML mappings require keys to be unique. See: https://yaml.org/spec/1.2/spec.html#id2764652

Reviewers: jhenderson, grimar, rupprecht, espindola, ruiu

Reviewed By: ruiu

Subscribers: ruiu, emaste, arichardson, MaskRay, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60438
Change TypePath in RepositoryPath in Workspace
The file was modified/lld/trunk/test/ELF/verdef-defaultver.sN/A
The file was modified/lld/trunk/test/ELF/verneed.sN/A
The file was modified/llvm/trunk/test/tools/llvm-readobj/elf-versioninfo.testtrunk/test/tools/llvm-readobj/elf-versioninfo.test
The file was modified/llvm/trunk/test/tools/yaml2obj/verneed-section.yamltrunk/test/tools/yaml2obj/verneed-section.yaml
The file was modified/llvm/trunk/test/tools/yaml2obj/versym-section.yamltrunk/test/tools/yaml2obj/versym-section.yaml
The file was modified/llvm/trunk/tools/llvm-readobj/ELFDumper.cpptrunk/tools/llvm-readobj/ELFDumper.cpp
Revision 358077 by lebedevri:
[llvm-exegesis] YamlContext: fix some missing spaces/quotes/newlines in error strings
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-exegesis/lib/BenchmarkResult.cpptrunk/tools/llvm-exegesis/lib/BenchmarkResult.cpp
Revision 358076 by lebedevri:
[llvm-exegesis] Fix error propagation from yaml writing (from serialization)

Investigating https://bugs.llvm.org/show_bug.cgi?id=41448
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-exegesis/lib/BenchmarkResult.cpptrunk/tools/llvm-exegesis/lib/BenchmarkResult.cpp
The file was modified/llvm/trunk/tools/llvm-exegesis/lib/BenchmarkResult.htrunk/tools/llvm-exegesis/lib/BenchmarkResult.h
Revision 358073 by dstenb:
[DebugInfo] Track multiple registers in DbgEntityHistoryCalculator

Summary:
When calculating the debug value history, DbgEntityHistoryCalculator
would only keep track of register clobbering for the latest debug value
per inlined entity. This meant that preceding register-described debug
value fragments would live on until the next overlapping debug value,
ignoring any potential clobbering. This patch amends
DbgEntityHistoryCalculator so that it keeps track of all registers that
a inlined entity's currently live debug values are described by.

The DebugInfo/COFF/pieces.ll test case has had to be changed since
previously a register-described fragment would incorrectly outlive its
basic block.

The parent patch D59941 is expected to increase the coverage slightly,
as it makes sure that location list entries are inserted after clobbered
fragments, and this patch is expected to decrease it, as it stops
preceding register-described from living longer than they should. All in
all, this patch and the preceding patch has a negligible effect on the
output from `llvm-dwarfdump -statistics' for a clang-3.4 binary built
using the RelWithDebInfo build profile. "Scope bytes covered" increases
by 0.5%, and "variables with location" increases from 2212083 to
2212088, but it should improve the accuracy quite a bit.

This fixes PR40283.

Reviewers: aprantl, probinson, dblaikie, rnk, bjope

Reviewed By: aprantl

Subscribers: llvm-commits

Tags: #debug-info, #llvm

Differential Revision: https://reviews.llvm.org/D59942
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/DbgEntityHistoryCalculator.htrunk/include/llvm/CodeGen/DbgEntityHistoryCalculator.h
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpptrunk/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp
The file was modified/llvm/trunk/test/DebugInfo/COFF/pieces.lltrunk/test/DebugInfo/COFF/pieces.ll
The file was modified/llvm/trunk/test/DebugInfo/MIR/X86/clobbered-fragments.mirtrunk/test/DebugInfo/MIR/X86/clobbered-fragments.mir
Revision 358072 by dstenb:
[DebugInfo] Improve handling of clobbered fragments

Summary:
Currently the DbgValueHistorymap only keeps track of clobbered registers
for the last debug value that it has encountered. This could lead to
preceding register-described debug values living on longer in the
location lists than they should. See PR40283 for an example.  This
patch does not introduce tracking of multiple registers, but changes
the DbgValueHistoryMap structure to allow for that in a follow-up
patch. This patch is not NFC, as it at least fixes two bugs in
DwarfDebug (both are covered in the new clobbered-fragments.mir test):

* If a debug value was clobbered (its End pointer set), the value would
  still be added to OpenRanges, meaning that the succeeding location list
  entries could potentially contain stale values.

* If a debug value was clobbered, and there were non-overlapping
  fragments that were still live after the clobbering, DwarfDebug would
  not create a location list entry starting directly after the
  clobbering instruction. This meant that the location list could have
  a gap until the next debug value for the variable was encountered.

Before this patch, the history map was represented by <Begin, End>
pairs, where a new pair was created for each new debug value. When
dealing with partially overlapping register-described debug values, such
as in the following example:

  DBG_VALUE $reg2, $noreg, !1, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
  [...]
  DBG_VALUE $reg3, $noreg, !1, !DIExpression(DW_OP_LLVM_fragment, 64, 32)
  [...]
  $reg2 = insn1
  [...]
  $reg3 = insn2

the history map would then contain the entries `[<DV1, insn1>, [<DV2, insn2>]`.
This would leave it up to the users of the map to be aware of
the relative order of the instructions, which e.g. could make
DwarfDebug::buildLocationList() needlessly complex. Instead, this patch
makes the history map structure monotonically increasing by dropping the
End pointer, and replacing that with explicit clobbering entries in the
vector. Each debug value has an "end index", which if set, points to the
entry in the vector that ends the debug value. The ending entry can
either be an overlapping debug value, or an instruction which clobbers
the register that the debug value is described by. The ending entry's
instruction can thus either be excluded or included in the debug value's
range. If the end index is not set, the debug value that the entry
introduces is valid until the end of the function.

Changes to test cases:

* DebugInfo/X86/pieces-3.ll: The range of the first DBG_VALUE, which
   describes that the fragment (0, 64) is located in RDI, was
   incorrectly ended by the clobbering of RAX, which the second
   (non-overlapping) DBG_VALUE was described by. With this patch we
   get a second entry that only describes RDI after that clobbering.

* DebugInfo/ARM/partial-subreg.ll: This test seems to indiciate a bug
   in LiveDebugValues that is caused by it not being aware of fragments.
   I have added some comments in the test case about that. Also, before
   this patch DwarfDebug would incorrectly include a register-described
   debug value from a preceding block in a location list entry.

Reviewers: aprantl, probinson, dblaikie, rnk, bjope

Reviewed By: aprantl

Subscribers: javed.absar, kristof.beyls, jdoerfert, llvm-commits

Tags: #debug-info, #llvm

Differential Revision: https://reviews.llvm.org/D59941
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/DbgEntityHistoryCalculator.htrunk/include/llvm/CodeGen/DbgEntityHistoryCalculator.h
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/CodeViewDebug.cpptrunk/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpptrunk/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpptrunk/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpptrunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
The file was modified/llvm/trunk/test/DebugInfo/ARM/partial-subreg.lltrunk/test/DebugInfo/ARM/partial-subreg.ll
The file was added/llvm/trunk/test/DebugInfo/MIR/X86/clobbered-fragments.mirtrunk/test/DebugInfo/MIR/X86/clobbered-fragments.mir
The file was modified/llvm/trunk/test/DebugInfo/X86/pieces-3.lltrunk/test/DebugInfo/X86/pieces-3.ll
Revision 358071 by rksimon:
[TargetLowering] Move shouldFoldShiftPairToMask next to preferShiftsToClearExtremeBits. NFCI.

As discussed on PR41359, we're probably going to keep both of these but we need to make it more explicit how they complement each other.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/TargetLowering.htrunk/include/llvm/CodeGen/TargetLowering.h
Revision 358068 by maskray:
[AsmPrinter] Delete unused RangeSpanList::addRange
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfFile.htrunk/lib/CodeGen/AsmPrinter/DwarfFile.h
Revision 358067 by maskray:
MCSymbolicELF: simplify. (Flags & (x << s)) >> s is equivalent to Flags >> s & x
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/MC/MCSymbolELF.cpptrunk/lib/MC/MCSymbolELF.cpp
Revision 358066 by maskray:
MCDwarf: use write_zeroes for MCDwarfLineAddr::FixedEncode

This is more efficient than allocating a std::vector<uint8_t>.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/MC/MCDwarf.cpptrunk/lib/MC/MCDwarf.cpp
Revision 358065 by rovka:
Fixup r358063

Fix warning/error about mixed signedness.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpptrunk/lib/Target/ARM/ARMInstructionSelector.cpp
Revision 358064 by rovka:
[ARM GlobalISel] Add some asserts. NFC.

Make sure some arm opcodes don't unintentionally sneak into thumb mode.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpptrunk/lib/Target/ARM/ARMInstructionSelector.cpp
Revision 358063 by rovka:
[ARM GlobalISel] Select G_FCONSTANT for VFP3

Make it possible to TableGen code for FCONSTS and FCONSTD.

We need to make two changes to the TableGen descriptions of vfp_f32imm
and vfp_f64imm respectively:
* add GISelPredicateCode to check that the immediate fits in 8 bits;
* extract the SDNodeXForms into separate definitions and create a
GISDNodeXFormEquiv and a custom renderer function for each of them.

There's a lot of boilerplate to get the actual value of the immediate,
but it basically just boils down to calling ARM_AM::getFP32Imm or
ARM_AM::getFP64Imm.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstrVFP.tdtrunk/lib/Target/ARM/ARMInstrVFP.td
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpptrunk/lib/Target/ARM/ARMInstructionSelector.cpp
The file was modified/llvm/trunk/test/CodeGen/ARM/GlobalISel/select-fp-const.mirtrunk/test/CodeGen/ARM/GlobalISel/select-fp-const.mir
Revision 358062 by rovka:
[ARM GlobalISel] Select G_FCONSTANT into pools

Put all floating point constants into constant pools and load their
values from there.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpptrunk/lib/Target/ARM/ARMInstructionSelector.cpp
The file was added/llvm/trunk/test/CodeGen/ARM/GlobalISel/select-fp-const.mirtrunk/test/CodeGen/ARM/GlobalISel/select-fp-const.mir
Revision 358061 by rovka:
[ARM GlobalISel] Map G_FCONSTANT
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpptrunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
The file was modified/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mirtrunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
Revision 358060 by dstenb:
[DebugInfo] Rename DbgValueHistoryMap::{InstrRange -> Entry}, NFC

Summary:
In an upcoming commit the history map will be changed so that it
contains explicit entries for instructions that clobber preceding debug
values, rather than Begin- End range pairs, so generalize the name to
"Entry".

Also, prefix the iterator variable names in buildLocationList() with
"E". In an upcoming commit the entry will have query functions such as
"isD(e)b(u)gValue", which could at a glance make one confuse it for
iterations over MachineInstrs, so make the iterator names a bit more
distinct to avoid that.

Reviewers: aprantl

Reviewed By: aprantl

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59939
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/DbgEntityHistoryCalculator.htrunk/include/llvm/CodeGen/DbgEntityHistoryCalculator.h
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/CodeViewDebug.cpptrunk/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/CodeViewDebug.htrunk/lib/CodeGen/AsmPrinter/CodeViewDebug.h
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpptrunk/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpptrunk/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpptrunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.htrunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
Revision 358059 by dstenb:
[DebugInfo] Make InstrRange into a class, NFC

Summary:
Replace use of std::pair by creating a class for the debug value
instruction ranges instead. This is a preparatory refactoring for
improving handling of clobbered fragments.

In an upcoming commit the Begin pointer will become a PointerIntPair, so
it will be cleaner to have a getter for that.

Reviewers: aprantl

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59938
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/DbgEntityHistoryCalculator.htrunk/include/llvm/CodeGen/DbgEntityHistoryCalculator.h
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/CodeViewDebug.cpptrunk/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpptrunk/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpptrunk/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpptrunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Revision 358058 by fhahn:
[ScheduleDAG] Add statistics for maintaining the topological order.

This is helpful to measure the impact of D60125 on maintaining
topological orders.

Reviewers: MatzeB, atrick, efriedma, niravd

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D60187
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/ScheduleDAG.cpptrunk/lib/CodeGen/ScheduleDAG.cpp
Revision 358057 by dstenb:
Add REQUIRES: asserts to test using -debug-only
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/LoopVectorize/vplan-stress-test-no-explict-vf.lltrunk/test/Transforms/LoopVectorize/vplan-stress-test-no-explict-vf.ll
Revision 358056 by fhahn:
[VPLAN] Minor improvement to testing and debug messages.

1. Use computed VF for stress testing.
2. If the computed VF does not produce vector code (VF smaller than 2), force VF to be 4.
3. Test vectorization of i64 data on AArch64 to make sure we generate VF != 4 (on X86 that was already tested on AVX).

Patch by Francesco Petrogalli <francesco.petrogalli@arm.com>

Differential Revision: https://reviews.llvm.org/D59952
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpptrunk/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modified/llvm/trunk/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.lltrunk/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
The file was modified/llvm/trunk/test/Transforms/LoopVectorize/explicit_outer_detection.lltrunk/test/Transforms/LoopVectorize/explicit_outer_detection.ll
The file was added/llvm/trunk/test/Transforms/LoopVectorize/vplan-stress-test-no-explict-vf.lltrunk/test/Transforms/LoopVectorize/vplan-stress-test-no-explict-vf.ll
Revision 358053 by maskray:
[DWARF] Simplify LineTable::findRowInSeq

We want the last row whose address is less than or equal to Address.
This can be computed as upper_bound - 1, which is simpler than
lower_bound followed by skipping equal rows in a loop.

Since FirstRow (LowPC) does not satisfy the predicate (OrderByAddress)
while LastRow-1 (HighPC) satisfies the predicate. We can decrease the
search range by two, i.e.

upper_bound [FirstRow,LastRow) = upper_bound [FirstRow+1,LastRow-1)
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/DebugInfo/DWARF/DWARFDebugLine.cpptrunk/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
Revision 358052 by nikic:
[InstCombine] Handle usubo always overflow

Check AlwaysOverflow condition for usubo. The implementation is the
same as the existing handling for uaddo and umulo. Handling for saddo
and ssubo will follow (smulo doesn't have the necessary ValueTracking
support).

Differential Revision: https://reviews.llvm.org/D60483
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpptrunk/lib/Transforms/InstCombine/InstCombineCompares.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/with_overflow.lltrunk/test/Transforms/InstCombine/with_overflow.ll
Revision 358051 by nikic:
[InstCombine] Directly call computeOverflow methods in OptimizeOverflowCheck; NFC

Instead of using the willOverflow helpers. This makes it easier to
extend handling of AlwaysOverflows.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpptrunk/lib/Transforms/InstCombine/InstCombineCompares.cpp
Revision 358050 by shchenz:
[InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y).

Differential Revision: https://reviews.llvm.org/D60395
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpptrunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/div.lltrunk/test/Transforms/InstCombine/div.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/sdiv-canonicalize.lltrunk/test/Transforms/InstCombine/sdiv-canonicalize.ll
Revision 358047 by ahatanak:
[ObjC][ARC] Convert the retainRV marker that is passed as a named
metadata into a module flag in the auto-upgrader and make the ARC
contract pass read the marker as a module flag.

This is needed to fix a bug where ARC contract wasn't inserting the
retainRV marker when LTO was enabled, which caused objects returned
from a function to be auto-released.

rdar://problem/49464214

Differential Revision: https://reviews.llvm.org/D60303
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/IR/AutoUpgrade.cpptrunk/lib/IR/AutoUpgrade.cpp
The file was modified/llvm/trunk/lib/Transforms/ObjCARC/ObjCARCContract.cpptrunk/lib/Transforms/ObjCARC/ObjCARCContract.cpp
The file was modified/llvm/trunk/test/Bitcode/upgrade-objcretainrelease.lltrunk/test/Bitcode/upgrade-objcretainrelease.ll
The file was modified/llvm/trunk/test/Transforms/ObjCARC/contract-marker-funclet.lltrunk/test/Transforms/ObjCARC/contract-marker-funclet.ll
The file was modified/llvm/trunk/test/Transforms/ObjCARC/contract-marker.lltrunk/test/Transforms/ObjCARC/contract-marker.ll
The file was modified/llvm/trunk/test/Transforms/ObjCARC/contract-testcases.lltrunk/test/Transforms/ObjCARC/contract-testcases.ll
Revision 358046 by ctopper:
[X86] Move the 2 byte VEX optimization for MOV instructions back to the X86AsmParser::processInstruction where it used to be. Block when {vex3} prefix is present.

Years ago I moved this to an InstAlias using VR128H/VR128L. But now that we support {vex3} pseudo prefix, we need to block the optimization when it is set to match gas behavior.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpptrunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86InstrSSE.tdtrunk/lib/Target/X86/X86InstrSSE.td
The file was modified/llvm/trunk/lib/Target/X86/X86RegisterInfo.tdtrunk/lib/Target/X86/X86RegisterInfo.td
The file was modified/llvm/trunk/test/MC/X86/x86_64-avx-encoding.strunk/test/MC/X86/x86_64-avx-encoding.s
Revision 358045 by maskray:
[llvm-objdump] Don't print trailing space in dumpBytes

In disassembly output, dumpBytes prints a space, followed by a tab
printed by printInstr. Remove the extra space.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/MC/MCInstPrinter.cpptrunk/lib/MC/MCInstPrinter.cpp
The file was modified/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpptrunk/tools/llvm-objdump/llvm-objdump.cpp
Revision 358043 by maskray:
[llvm-objdump] Accept and ignore --wide/-w

This is similar to what we do for llvm-readobj (--wide/-W is for GNU
readelf compatibility).

The test will be added in D60376.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpptrunk/tools/llvm-objdump/llvm-objdump.cpp
Revision 358042 by jimlin:
[Sparc] Fix incorrect MI insertion position for spilling f128.

Summary:
Obviously, new built MI (sethi+add or sethi+xor+add) for constructing large offset
should be inserted before new created MI for storing even register into memory.
So the insertion position should be *StMI instead of II.

before fixed:

std %f0, [%g1+80]
sethi 4, %g1        <<<
add %g1, %sp, %g1   <<< this two instructions should be put before "std %f0, [%g1+80]".
sethi 4, %g1
add %g1, %sp, %g1
std %f2, [%g1+88]

after fixed:

sethi 4, %g1
add %g1, %sp, %g1
std %f0, [%g1+80]
sethi 4, %g1
add %g1, %sp, %g1
std %f2, [%g1+88]

Reviewers: venkatra, jyknight

Reviewed By: jyknight

Subscribers: jyknight, fedor.sergeev, jrtc27, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60397
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpptrunk/lib/Target/Sparc/SparcRegisterInfo.cpp
The file was modified/llvm/trunk/test/CodeGen/SPARC/fp128.lltrunk/test/CodeGen/SPARC/fp128.ll
Revision 358041 by ctopper:
[X86] Support the EVEX versions vcvt(t)ss2si and vcvt(t)sd2si with the {evex} pseudo prefix in the assembler.

The EVEX versions are ambiguous with the VEX versions based on operands alone so we had explicitly dropped
them from the AsmMatcher table. Unfortunately, when we add them they incorrectly show in the table before
their VEX counterparts. This is different how the prioritization normally works.

To fix this we have to explicitly reject the instructions unless the {evex} prefix has been seen.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpptrunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.tdtrunk/lib/Target/X86/X86InstrAVX512.td
The file was modified/llvm/trunk/test/MC/X86/AVX512F_SCALAR-64.strunk/test/MC/X86/AVX512F_SCALAR-64.s
Revision 358040 by ctopper:
[X86] Add VEX_LIG to scalar VEX/EVEX instructions that were missing it.

Scalar VEX/EVEX instructions don't use the L bit and don't look at it for decoding either.
So we should ignore it in our disassembler.

The missing instructions here were found by grepping the raw tablegen class definitions in
the tablegen debug output.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrAVX512.tdtrunk/lib/Target/X86/X86InstrAVX512.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrSSE.tdtrunk/lib/Target/X86/X86InstrSSE.td
Revision 358039 by codafi:
[LLVM-C] Correct The Current Debug Location Accessors

Summary: Deprecate the existing accessors for the "current debug location" of an IRBuilder.  The setter could not handle being reset to NULL, and the getter would create bogus metadata if the NULL location was returned.  Provide direct metadata-based accessors instead.

Reviewers: whitequark, deadalnix

Reviewed By: whitequark

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60484
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm-c/Core.htrunk/include/llvm-c/Core.h
The file was modified/llvm/trunk/lib/IR/Core.cpptrunk/lib/IR/Core.cpp
Revision 358038 by codafi:
[LLVM-C] Add Bindings to Access an Instruction's DebugLoc

Summary: Provide direct accessors to supplement LLVMSetInstDebugLocation.  In addition, properly accept and return the NULL location.  The old accessors provided no way to do this, so the current debug location cannot currently be cleared.

Reviewers: whitequark, deadalnix

Reviewed By: whitequark

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60481
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm-c/DebugInfo.htrunk/include/llvm-c/DebugInfo.h
The file was modified/llvm/trunk/lib/IR/DebugInfo.cpptrunk/lib/IR/DebugInfo.cpp
Revision 358037 by codafi:
[LLVM-C] Add Section and Symbol Iterator Accessors for Object File Binaries

Summary: This brings us to full feature parity with the old API, so I've deprecated it and updated the tests.  I'll do a follow-up patch to do some more cleanup and documentation work in this header.

Reviewers: whitequark, deadalnix

Reviewed By: whitequark

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60407
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm-c/Object.htrunk/include/llvm-c/Object.h
The file was modified/llvm/trunk/lib/Object/Object.cpptrunk/lib/Object/Object.cpp
The file was modified/llvm/trunk/tools/llvm-c-test/object.ctrunk/tools/llvm-c-test/object.c
Revision 358036 by ctopper:
[X86] Fix a dangling StringRef issue introduced in r358029.

I was attempting to convert mnemonics to lower case after processing a pseudo prefix. But the ParseOperands just hold a StringRef for tokens so there is no where to allocate the memory.

Add FIXMEs for the lower case issue which also exists in the prefix parsing code.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpptrunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
Revision 358035 by Amara Emerson:
[AArch64][GlobalISel] Add isel support for vector G_ICMP and G_ASHR & G_SHL

The selection for G_ICMP is unfortunately not currently importable from SDAG
due to the use of custom SDNodes. To support this, this selection method has an
opcode table which has been generated by a script, indexed by various
instruction properties. Ideally in future we will have a GISel native selection
patterns that we can write in tablegen to improve on this.

For selection of some types we also need support for G_ASHR and G_SHL which are
generated as a result of legalization. This patch also adds support for them,
generating the same code as SelectionDAG currently does.

Differential Revision: https://reviews.llvm.org/D60436
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpptrunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
The file was added/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mirtrunk/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir
The file was added/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mirtrunk/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir
Revision 358034 by Amara Emerson:
[AArch64][GlobalISel] Legalize vector G_ICMP.

Selection support will be coming in a later patch.

Differential Revision: https://reviews.llvm.org/D60435
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerInfo.htrunk/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpptrunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-select.mirtrunk/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
The file was added/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-vector-icmp.mirtrunk/test/CodeGen/AArch64/GlobalISel/legalize-vector-icmp.mir
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mirtrunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
Revision 358033 by Amara Emerson:
[AArch64][GlobalISel] Add legalization for some vector G_SHL and G_ASHR.

This is needed for some future support for vector ICMP.

Differential Revision: https://reviews.llvm.org/D60433
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerInfo.htrunk/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpptrunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mirtrunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mirtrunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
Revision 358032 by Amara Emerson:
[GlobalISel][AArch64] Allow CallLowering to handle types which are normally
required to be passed as different register types. E.g. <2 x i16> may need to
be passed as a larger <2 x i32> type, so formal arg lowering needs to be able
truncate it back. Likewise, when dealing with returns of these types, they need
to be widened in the appropriate way back.

Differential Revision: https://reviews.llvm.org/D60425
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/GlobalISel/CallLowering.htrunk/include/llvm/CodeGen/GlobalISel/CallLowering.h
The file was modified/llvm/trunk/lib/CodeGen/GlobalISel/CallLowering.cpptrunk/lib/CodeGen/GlobalISel/CallLowering.cpp
The file was modified/llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpptrunk/lib/Target/AArch64/AArch64CallLowering.cpp
The file was modified/llvm/trunk/lib/Target/ARM/ARMCallLowering.cpptrunk/lib/Target/ARM/ARMCallLowering.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86CallLowering.cpptrunk/lib/Target/X86/X86CallLowering.cpp
The file was added/llvm/trunk/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.lltrunk/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
The file was added/llvm/trunk/test/CodeGen/AArch64/GlobalISel/vec-s16-param.lltrunk/test/CodeGen/AArch64/GlobalISel/vec-s16-param.ll
The file was modified/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-unsupported.lltrunk/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll
Revision 358031 by nikic:
[InstCombine] Add with.overflow always overflow tests; NFC

The uadd and umul cases are currently handled, the usub, sadd, ssub
and smul cases are not. usub, sadd and ssub already have the
necessary ValueTracking support, smul doesn't.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/with_overflow.lltrunk/test/Transforms/InstCombine/with_overflow.ll
Revision 358030 by ctopper:
[AArch64] Add test case to show missed opportunity to remove a shift before tbnz when the shift has been zero extended from i32 to i64. NFC

This pattern showed up in D60358 and it was suggested I had a test and fix that separately.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/AArch64/tbz-tbnz.lltrunk/test/CodeGen/AArch64/tbz-tbnz.ll
Revision 358029 by ctopper:
[X86] Add support for {vex2}, {vex3}, and {evex} to the assembler to match gas. Use {evex} to improve the one our 32-bit AVX512 tests.

These can be used to force the encoding used for instructions.

{vex2} will fail if the instruction is not VEX encoded, but otherwise won't do anything since we prefer vex2 when possible. Might need to skip use of the _REV MOV instructions for this too, but I haven't done that yet.

{vex3} will force the instruction to use the 3 byte VEX encoding or fail if there is no VEX form.

{evex} will force the instruction to use the EVEX version or fail if there is no EVEX version.

Differential Revision: https://reviews.llvm.org/D59266
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpptrunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
The file was modified/llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.htrunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
The file was modified/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpptrunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
The file was modified/llvm/trunk/test/MC/X86/AVX-32.strunk/test/MC/X86/AVX-32.s
The file was modified/llvm/trunk/test/MC/X86/AVX512F_SCALAR-32.strunk/test/MC/X86/AVX512F_SCALAR-32.s
The file was modified/llvm/trunk/test/MC/X86/x86_errors.strunk/test/MC/X86/x86_errors.s
Revision 358027 by ctopper:
[DAGCombiner][X86][SystemZ] Canonicalize SSUBO with immediate RHS to SADDO by negating the immediate.

This lines up with what we do for regular subtract and it matches up better with X86 assumptions in isel patterns that add with immediate is more canonical than sub with immediate.

Differential Revision: https://reviews.llvm.org/D60020
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpptrunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modified/llvm/trunk/test/CodeGen/SystemZ/int-ssub-07.lltrunk/test/CodeGen/SystemZ/int-ssub-07.ll
The file was modified/llvm/trunk/test/CodeGen/X86/sub-with-overflow.lltrunk/test/CodeGen/X86/sub-with-overflow.ll
The file was modified/llvm/trunk/test/CodeGen/X86/xaluo.lltrunk/test/CodeGen/X86/xaluo.ll
Revision 358026 by nikic:
Revert "[InstCombine] [InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y)."

This reverts commit 1383a9168948aabfd827220c9445ce0ce5765800.

sdiv-canonicalize.ll fails after this revision. The fold needs to be
moved outside the branch handling constant operands. However when this
is done there are further test changes, so I'm reverting this in the
meantime.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpptrunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/sdiv-canonicalize.lltrunk/test/Transforms/InstCombine/sdiv-canonicalize.ll
Revision 358025 by nikic:
[InstCombine] Restructure OptimizeOverflowCheck; NFC

Change the code to always handle the unsigned+signed cases together
with the same basic structure for add/sub/mul. The simple folds are
always handled first and then the ValueTracking overflow checks are
used.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpptrunk/lib/Transforms/InstCombine/InstCombineCompares.cpp
Revision 358024 by echristo:
Remove the unit at a time option
Removes the code from opt and the pass manager builder.
The code was unused - even by the C library code that was supposed to set
it and had been removed previously.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Transforms/IPO/PassManagerBuilder.htrunk/include/llvm/Transforms/IPO/PassManagerBuilder.h
The file was modified/llvm/trunk/tools/opt/opt.cpptrunk/tools/opt/opt.cpp
Revision 358022 by zturner:
[PDB Docs] Clarifications and fixes for DBI Stream.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/PDB/DbiStream.rsttrunk/docs/PDB/DbiStream.rst
Revision 358021 by Kristina Brooks:
Update modulemaps for Analysis/VecFuncs.def.

Avoid a warning while building modular LLVM due to a new
textual header missing in the modulemap:

TargetLibraryInfo.cpp:1485:6: warning: missing submodule
  'LLVM_Analysis.VecFuncs' [-Wincomplete-umbrella]

Added VecFuncs.def as a textual header in LLVM_Analysis.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/module.modulemaptrunk/include/llvm/module.modulemap
Revision 358020 by nikic:
[ValueTracking] Use computeConstantRange() for signed sub overflow determination

This is the same change as D60420 but for signed sub rather than
signed add: Range information is intersected into the known bits
result, allows to detect more no/always overflow conditions.

Differential Revision: https://reviews.llvm.org/D60469
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Analysis/ValueTracking.cpptrunk/lib/Analysis/ValueTracking.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/saturating-add-sub.lltrunk/test/Transforms/InstCombine/saturating-add-sub.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/ssub-with-overflow.lltrunk/test/Transforms/InstCombine/ssub-with-overflow.ll
Revision 358019 by rksimon:
[TargetLowering] SimplifyDemandedBits - add ISD::INSERT_SUBVECTOR support
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpptrunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/avx512-mask-op.lltrunk/test/CodeGen/X86/avx512-mask-op.ll
Revision 358017 by shchenz:
[InstCombine] [InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y).

Differential Revision: https://reviews.llvm.org/D60395
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpptrunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/sdiv-canonicalize.lltrunk/test/Transforms/InstCombine/sdiv-canonicalize.ll
Revision 358015 by rampitec:
Revert LIS handling in MachineDCE

One of out of tree targets has regressed with this patch. Reverting
it for now and let liveness to be fully reconstructed in case pass
was used after the LIS is created to resolve the regression.

Differential Revision: https://reviews.llvm.org/D60466
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpptrunk/lib/CodeGen/DeadMachineInstructionElim.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/bswap.lltrunk/test/CodeGen/AMDGPU/bswap.ll
The file was added/llvm/trunk/test/CodeGen/AMDGPU/dce-disjoint-intervals.mirtrunk/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.lltrunk/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll
Revision 358014 by nikic:
[ValueTracking] Use computeConstantRange() in signed add overflow determination

This is D59386 for the signed add case. The computeConstantRange()
result is now intersected into the existing known bits information,
allowing to detect additional no-overflow/always-overflow conditions
(though the latter isn't used yet).

This (finally...) covers the motivating case from D59071.

Differential Revision: https://reviews.llvm.org/D60420
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Analysis/ValueTracking.cpptrunk/lib/Analysis/ValueTracking.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/and2.lltrunk/test/Transforms/InstCombine/and2.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/icmp-add.lltrunk/test/Transforms/InstCombine/icmp-add.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/minmax-fold.lltrunk/test/Transforms/InstCombine/minmax-fold.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/sadd-with-overflow.lltrunk/test/Transforms/InstCombine/sadd-with-overflow.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/saturating-add-sub.lltrunk/test/Transforms/InstCombine/saturating-add-sub.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/sub.lltrunk/test/Transforms/InstCombine/sub.ll
Revision 358013 by spatel:
[InstCombine] prevent possible miscompile with sdiv+negate of vector op

Similar to:
rL358005

Forego folding arbitrary vector constants to fix a possible miscompile bug.
We can enhance the transform if we do want to handle the more complicated
vector case.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpptrunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/div.lltrunk/test/Transforms/InstCombine/div.ll
Revision 358012 by maskray:
[DWARF] DWARFDebugLine: replace Sequence::orderByLowPC with orderByHighPC

In a sorted list of non-overlapping [LowPC,HighPC) ranges, locating an address with
upper_bound on HighPC is simpler than lower_bound on LowPC.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/DebugInfo/DWARF/DWARFDebugLine.htrunk/include/llvm/DebugInfo/DWARF/DWARFDebugLine.h
The file was modified/llvm/trunk/lib/DebugInfo/DWARF/DWARFDebugLine.cpptrunk/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
Revision 358010 by spatel:
[InstCombine] add tests for sdiv with negated dividend and constant divisor; NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/div.lltrunk/test/Transforms/InstCombine/div.ll
Revision 358008 by spatel:
[InstCombine] add tests for sdiv-by-int-min; NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/div.lltrunk/test/Transforms/InstCombine/div.ll
Revision 358007 by spatel:
[InstCombine] auto-generate complete test checks; NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/sdiv-1.lltrunk/test/Transforms/InstCombine/sdiv-1.ll
Revision 358005 by spatel:
[InstCombine] prevent possible miscompile with negate+sdiv of vector op

// 0 - (X sdiv C)  -> (X sdiv -C)  provided the negation doesn't overflow.

This fold has been around for many years and nobody noticed the potential
vector miscompile from overflow until recently...
So it seems unlikely that there's much demand for a vector sdiv optimization
on arbitrary vector constants, so just limit the matching to splat constants
to avoid the possible bug.

Differential Revision: https://reviews.llvm.org/D60426
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineAddSub.cpptrunk/lib/Transforms/InstCombine/InstCombineAddSub.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/div.lltrunk/test/Transforms/InstCombine/div.ll
Revision 358004 by nico:
gn build: Fix Windows builds after r357797
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpptrunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
The file was modified/llvm/trunk/utils/gn/build/BUILD.gntrunk/utils/gn/build/BUILD.gn
Revision 358003 by spatel:
[InstCombine] add tests/comments for negate+sdiv; NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/div.lltrunk/test/Transforms/InstCombine/div.ll
Revision 358001 by nemanjai:
NFC: Refactor library-specific mappings of scalar maths functions to their vector counterparts

This patch factors out mappings of scalar maths functions to their vector
counterparts from TargetLibraryInfo.cpp to a separate VecFuncs.def file. Such
mappings are currently available for Accelerate framework, and SVML library.

This is in support of the follow-up: https://reviews.llvm.org/D59881

Patch by pjeeva01

Differential revision: https://reviews.llvm.org/D60211
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/include/llvm/Analysis/VecFuncs.deftrunk/include/llvm/Analysis/VecFuncs.def
The file was modified/llvm/trunk/lib/Analysis/TargetLibraryInfo.cpptrunk/lib/Analysis/TargetLibraryInfo.cpp
Revision 358000 by shchenz:
[InstCombine] add more testcases for canonicalize (-X s/ Y) to -(X s/ Y).
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/sdiv-canonicalize.lltrunk/test/Transforms/InstCombine/sdiv-canonicalize.ll
Revision 357999 by rksimon:
[TargetLowering] SimplifyDemandedBits - Remove GetDemandedSrcMask lambda. NFCI.

An older version of this could return false but now that this always succeeds we can just inline and simplify it.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpptrunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Revision 357998 by anton-afanasyev:
Improve hashing for time profiler

Summary:
Use optimized hashing while writing time trace by join two hashes to one.
Used for -ftime-trace option.

Reviewers: rnk, takuto.ikuta

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60404
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Support/TimeProfiler.cpptrunk/lib/Support/TimeProfiler.cpp
Revision 357992 by rksimon:
[TargetLowering] SimplifyDemandedBits - call SimplifyDemandedBits in bitcast handling

When bitcasting from a source op to a larger bitwidth op, split the demanded bits and OR them on top of one another and demand those merged bits in the SimplifyDemandedBits call on the source op.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpptrunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/urem-seteq-vec-nonsplat.lltrunk/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
Revision 357990 by rksimon:
[llvm-rtdyld] Fix missing include on MSVC builds.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-rtdyld/llvm-rtdyld.cpptrunk/tools/llvm-rtdyld/llvm-rtdyld.cpp
Revision 357988 by dstenb:
[DebugInfo] Pass all values in DebugLocEntry's constructor, NFC

Summary:
With MergeValues() removed, amend DebugLocEntry's constructor so that it
takes multiple values rather than a single, and keep non-fragment values
in OpenRanges, as this allows some cleanup of the code in
buildLocationList().

Reviewers: aprantl, dblaikie, loladiro

Reviewed By: aprantl

Subscribers: hiraditya, llvm-commits

Tags: #debug-info, #llvm

Differential Revision: https://reviews.llvm.org/D59303
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DebugLocEntry.htrunk/lib/CodeGen/AsmPrinter/DebugLocEntry.h
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpptrunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Revision 357987 by rksimon:
Fix Wdocumentation warning. NFCI.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/DIBuilder.htrunk/include/llvm/IR/DIBuilder.h
Revision 357981 by inouehrs:
[PowerPC] fix trivial typos in comment, NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpptrunk/lib/Target/PowerPC/PPCFrameLowering.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpptrunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.htrunk/lib/Target/PowerPC/PPCISelLowering.h
Revision 357979 by mstorsjo:
[CMake] Fix accidentally swapped input/output parameters of string(REPLACE) for mingw
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/cmake/modules/HandleLLVMOptions.cmaketrunk/cmake/modules/HandleLLVMOptions.cmake
Revision 357976 by Justin Bogner:
[CMake] Move configuration of LLVM_CXX_STD to HandleLLVMOptions.cmake

Standalone builds of projects other than llvm itself (lldb, libcxx,
etc) include HandleLLVMOptions but not the top level llvm CMakeLists,
so we need to set this variable here to ensure that it always has a
value.

This should fix the build issues some folks have been seeing.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/CMakeLists.txttrunk/CMakeLists.txt
The file was modified/llvm/trunk/cmake/modules/HandleLLVMOptions.cmaketrunk/cmake/modules/HandleLLVMOptions.cmake
Revision 357974 by dstenb:
[DebugInfo] Remove redundant DebugLocEntry::MergeValues() function, NFC

Summary:
The MergeValues() function would try to merge two entries if they shared
the same beginning label. Having the same beginning label means that the
former entry's range would be empty; however, after D55919 we no longer
create entries for empty ranges, so we can no longer land in a situation
where that check in MergeValues would succeed. Instead, the "merging" is
done by keeping the live values from the preceding empty ranges in
OpenRanges, and adding them to the first non-empty range.

Reviewers: aprantl, dblaikie, loladiro

Reviewed By: aprantl

Subscribers: llvm-commits

Tags: #debug-info, #llvm

Differential Revision: https://reviews.llvm.org/D59301
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DebugLocEntry.htrunk/lib/CodeGen/AsmPrinter/DebugLocEntry.h
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpptrunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Revision 357973 by ctopper:
[X86] Remove check on isAsmParserOnly from EVEX2VEX tablegenerator. NFCI

There are no instructions VEX or EVEX instructions that set this field.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/utils/TableGen/X86EVEX2VEXTablesEmitter.cpptrunk/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
Revision 357972 by ctopper:
[X86] Have EVEX2VEX tablegenerator use HasVEX_L and HasEVEX_L2 fields instead of the composite EVEX_LL field. Remove the EVEX_LL field. NFCI

The composite existed to simplify some other tablegen code and not really in an
important way. Remove the combined field and just calculate the vector size
using two ifs.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrFormats.tdtrunk/lib/Target/X86/X86InstrFormats.td
The file was modified/llvm/trunk/utils/TableGen/X86EVEX2VEXTablesEmitter.cpptrunk/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
Revision 357971 by ctopper:
[X86] Use VEX_WIG for VPINSRB/W and VPEXTRB/W to match what is done for EVEX.

The instruction's document this as W0 for the VEX encoding. But there's a
footnote mentioning that VEX.W is ignored in 64-bit mode. And the main VEX
encoding description says the VEX.W bit is ignored for instructions that are
equivalent to a legacy SSE instruction that uses REX.W to select a GPR which
would apply here.

By making this match EVEX we can remove a special case of allowing EVEX2VEX to
turn an EVEX.WIG instruction into VEX.W0.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrSSE.tdtrunk/lib/Target/X86/X86InstrSSE.td
The file was modified/llvm/trunk/utils/TableGen/X86EVEX2VEXTablesEmitter.cpptrunk/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
Revision 357970 by ctopper:
[X86] Split the VEX_WPrefix in X86Inst tablegen class into 3 separate fields with clear meanings.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrFormats.tdtrunk/lib/Target/X86/X86InstrFormats.td
The file was modified/llvm/trunk/utils/TableGen/X86EVEX2VEXTablesEmitter.cpptrunk/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
The file was modified/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpptrunk/utils/TableGen/X86RecognizableInstr.cpp
The file was modified/llvm/trunk/utils/TableGen/X86RecognizableInstr.htrunk/utils/TableGen/X86RecognizableInstr.h
Revision 357969 by nikic:
[ValueTracking] Use ConstantRange methods; NFC

Switch part of the computeOverflowForSignedAdd() implementation to
use Range.isAllNegative() rather than KnownBits.isNegative() and
similar. They do the same thing, but using the ConstantRange methods
allows dropping the KnownBits variables more easily in D60420.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Analysis/ValueTracking.cpptrunk/lib/Analysis/ValueTracking.cpp
Revision 357968 by nikic:
[ValueTracking] Explicitly specify intersection type; NFC

Preparation for D60420.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Analysis/ValueTracking.cpptrunk/lib/Analysis/ValueTracking.cpp
Revision 357967 by echristo:
Include omitted word in comment.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Transforms/IPO/PassManagerBuilder.htrunk/include/llvm/Transforms/IPO/PassManagerBuilder.h
Revision 357965 by maskray:
[llvm-objdump] Migrate some functions from std::error_code to Error
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-objdump/COFFDump.cpptrunk/tools/llvm-objdump/COFFDump.cpp
The file was modified/llvm/trunk/tools/llvm-objdump/MachODump.cpptrunk/tools/llvm-objdump/MachODump.cpp
The file was modified/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpptrunk/tools/llvm-objdump/llvm-objdump.cpp
The file was modified/llvm/trunk/tools/llvm-objdump/llvm-objdump.htrunk/tools/llvm-objdump/llvm-objdump.h
Revision 357964 by tstellar:
AMDGPU/GlobalISel: Implement call lowering for shaders returning values

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, jvesely, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, volkan, llvm-commits

Differential Revision: https://reviews.llvm.org/D57166
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpptrunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.lltrunk/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
The file was removed/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/todo.lltrunk/test/CodeGen/AMDGPU/GlobalISel/todo.ll
Revision 357962 by shchenz:
[PowerPC] initialize SchedModel according to platform.
Differential Revision: https://reviews.llvm.org/D60177
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpptrunk/lib/Target/PowerPC/PPCCTRLoops.cpp
The file was modified/llvm/trunk/test/CodeGen/PowerPC/ctrloop-shortLoops.lltrunk/test/CodeGen/PowerPC/ctrloop-shortLoops.ll
Revision 357960 by pcc:
hwasan: Enable -hwasan-allow-ifunc by default.

It's been on in Android for a while without causing problems, so it's time
to make it the default and remove the flag.

Differential Revision: https://reviews.llvm.org/D60355
Change TypePath in RepositoryPath in Workspace
The file was modified/compiler-rt/trunk/test/hwasan/lit.cfgN/A
The file was modified/llvm/trunk/lib/Transforms/Instrumentation/HWAddressSanitizer.cpptrunk/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
The file was modified/llvm/trunk/test/Instrumentation/HWAddressSanitizer/lazy-thread-init.lltrunk/test/Instrumentation/HWAddressSanitizer/lazy-thread-init.ll
The file was modified/llvm/trunk/test/Instrumentation/HWAddressSanitizer/prologue.lltrunk/test/Instrumentation/HWAddressSanitizer/prologue.ll
Revision 357959 by ctopper:
[X86] Derive ssmem and sdmem from X86MemOperand. NFCI

This changes the operand type from v4f32/v2f64 to iPTR which seems more correct. But that doesn't seem to do anything other than change the comments in X86GenDAGISel.inc. Probably because we use a ComplexPattern to do the matching so there's no autogenerated code to change.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.tdtrunk/lib/Target/X86/X86InstrFragmentsSIMD.td
Revision 357953 by spatel:
[InstCombine] add tests for negate+sdiv; NFC

PR41425:
https://bugs.llvm.org/show_bug.cgi?id=41425
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/div.lltrunk/test/Transforms/InstCombine/div.ll
Revision 357950 by Lang Hames:
[RuntimeDyld] Fix an ambiguous make_unique call.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpptrunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
Revision 357947 by Lang Hames:
[RuntimeDyld] Decouple RuntimeDyldChecker from RuntimeDyld.

This will allow RuntimeDyldChecker (and rtdyld-check tests) to test a new JIT
linker: JITLink (https://reviews.llvm.org/D58704).
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.htrunk/include/llvm/ExecutionEngine/RuntimeDyld.h
The file was modified/llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyldChecker.htrunk/include/llvm/ExecutionEngine/RuntimeDyldChecker.h
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpptrunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpptrunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCheckerImpl.htrunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCheckerImpl.h
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpptrunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.htrunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h
The file was modified/llvm/trunk/tools/llvm-rtdyld/llvm-rtdyld.cpptrunk/tools/llvm-rtdyld/llvm-rtdyld.cpp
Revision 357945 by smeenai:
[BinaryFormat] Update Mach-O ARM64E CPU subtype and dumping

The new value is taken from <mach/machine.h> in the MacOSX10.14 SDK from
Xcode 10.1. Update llvm-objdump and llvm-readobj accordingly.

Differential Revision: https://reviews.llvm.org/D58636
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/BinaryFormat/MachO.htrunk/include/llvm/BinaryFormat/MachO.h
The file was added/llvm/trunk/test/tools/llvm-objdump/AArch64/Inputs/arm64e.macho.yamltrunk/test/tools/llvm-objdump/AArch64/Inputs/arm64e.macho.yaml
The file was added/llvm/trunk/test/tools/llvm-objdump/AArch64/macho-arm64e.testtrunk/test/tools/llvm-objdump/AArch64/macho-arm64e.test
The file was modified/llvm/trunk/tools/llvm-objdump/MachODump.cpptrunk/tools/llvm-objdump/MachODump.cpp
The file was modified/llvm/trunk/tools/llvm-readobj/MachODumper.cpptrunk/tools/llvm-readobj/MachODumper.cpp
Revision 357943 by spatel:
[InstCombine] peek through fdiv to find a squared sqrt

A more general canonicalization between fdiv and fmul would not
handle this case because that would have to be limited by uses
to prevent 2 values from becoming 3 values:
(x/y) * (x/y) --> (x*x) / (y*y)

(But we probably should still have that limited -- but more general --
canonicalization independently of this change.)
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpptrunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/fmul-sqrt.lltrunk/test/Transforms/InstCombine/fmul-sqrt.ll
Revision 357942 by rksimon:
[TargetLowering] SimplifyDemandedBits - use DemandedElts in bitcast handling

Be more selective in the SimplifyDemandedBits -> SimplifyDemandedVectorElts bitcast call based on the demanded elts.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpptrunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/extract-insert.lltrunk/test/CodeGen/X86/extract-insert.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-mul-widen.lltrunk/test/CodeGen/X86/vector-reduce-mul-widen.ll
The file was modified/llvm/trunk/test/CodeGen/X86/widen_load-2.lltrunk/test/CodeGen/X86/widen_load-2.ll
Revision 357939 by spatel:
[InstCombine] add extra-use tests for fmul+sqrt; NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/fmul-sqrt.lltrunk/test/Transforms/InstCombine/fmul-sqrt.ll
Revision 357938 by nikic:
[InstCombine] Add more tests for signed saturing math overflow; NFC

Overflow conditions for sadd.sat and ssub.sat which can be determined
based on constant ranges, but not necessarily known bits.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/saturating-add-sub.lltrunk/test/Transforms/InstCombine/saturating-add-sub.ll
Revision 357936 by nico:
llvm-undname: Fix more crashes and asserts on invalid inputs

For functions whose callers don't check that enough input is present,
add checks at the start of the function that enough input is there and
set Error otherwise.

For functions that return AST objects, return nullptr instead of
incomplete AST objects with nullptr fields if an error occurred during
the function.

Introduce a new function demangleDeclarator() for the sequence
demangleFullyQualifiedSymbolName(); demangleEncodedSymbol() and
use it in the two places that had this sequence. Let this new function
check that ConversionOperatorIdentifiers have a valid TargetType.

Some of the bad inputs found by oss-fuzz, others by inspection.

Differential Revision: https://reviews.llvm.org/D60354
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Demangle/MicrosoftDemangle.htrunk/include/llvm/Demangle/MicrosoftDemangle.h
The file was modified/llvm/trunk/lib/Demangle/MicrosoftDemangle.cpptrunk/lib/Demangle/MicrosoftDemangle.cpp
The file was modified/llvm/trunk/test/Demangle/invalid-manglings.testtrunk/test/Demangle/invalid-manglings.test
Revision 357935 by ctopper:
[X86] Fix a couple lowering functions that called ReplaceAllUsesOfValueWith for the newly created code and then return SDValue(). Use MERGE_VALUES instead.

Returning SDValue() makes the caller think custom lowering was unsuccessful and then it will fall back to trying to expand the original node. This expanded code will end up with no users and end up being pruned later. But it was useless unnecessary work to create it.

Instead return a MERGE_VALUES with all the results so the caller knows something changed. The caller can handle the replacements.

For one of the cases I had to use UNDEF has a dummy value for a result we know is unused. This should get pruned later.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
Revision 357934 by Adrian Prantl:
Add LLVM IR debug info support for Fortran COMMON blocks

    COMMON blocks are a feature of Fortran that has no direct analog in C languages, but they are similar to data sections in assembly language programming. A COMMON block is a named area of memory that holds a collection of variables. Fortran subprograms may map the COMMON block memory area to their own, possibly distinct, non-empty list of variables. A Fortran COMMON block might look like the following example.

    COMMON /ALPHA/ I, J

    For this construct, the compiler generates a new scope-like DI construct (!DICommonBlock) into which variables (see I, J above) can be placed. As the common block implies a range of storage with global lifetime, the !DICommonBlock refers to a !DIGlobalVariable. The Fortran variable that comprise the COMMON block are also linked via metadata to offsets within the global variable that stands for the entire common block.

    @alpha_ = common global %alphabytes_ zeroinitializer, align 64, !dbg !27, !dbg !30, !dbg !33
    !14 = distinct !DISubprogram(…)
    !20 = distinct !DICommonBlock(scope: !14, declaration: !25, name: "alpha")
    !25 = distinct !DIGlobalVariable(scope: !20, name: "common alpha", type: !24)
    !27 = !DIGlobalVariableExpression(var: !25, expr: !DIExpression())
    !29 = distinct !DIGlobalVariable(scope: !20, name: "i", file: !3, type: !28)
    !30 = !DIGlobalVariableExpression(var: !29, expr: !DIExpression())
    !31 = distinct !DIGlobalVariable(scope: !20, name: "j", file: !3, type: !28)
    !32 = !DIExpression(DW_OP_plus_uconst, 4)
    !33 = !DIGlobalVariableExpression(var: !31, expr: !32)

    The DWARF generated for this is as follows.

    DW_TAG_common_block:
    DW_AT_name: alpha
    DW_AT_location: @alpha_+0
    DW_TAG_variable:
    DW_AT_name: common alpha
    DW_AT_type: array of 8 bytes
    DW_AT_location: @alpha_+0
    DW_TAG_variable:
    DW_AT_name: i
    DW_AT_type: integer*4
    DW_AT_location: @Alpha+0
    DW_TAG_variable:
    DW_AT_name: j
    DW_AT_type: integer*4
    DW_AT_location: @Alpha+4

Patch by Eric Schweitz!

Differential Revision: https://reviews.llvm.org/D54327
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm-c/DebugInfo.htrunk/include/llvm-c/DebugInfo.h
The file was modified/llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.htrunk/include/llvm/Bitcode/LLVMBitCodes.h
The file was modified/llvm/trunk/include/llvm/IR/DIBuilder.htrunk/include/llvm/IR/DIBuilder.h
The file was modified/llvm/trunk/include/llvm/IR/DebugInfoMetadata.htrunk/include/llvm/IR/DebugInfoMetadata.h
The file was modified/llvm/trunk/include/llvm/IR/Metadata.deftrunk/include/llvm/IR/Metadata.def
The file was modified/llvm/trunk/lib/AsmParser/LLParser.cpptrunk/lib/AsmParser/LLParser.cpp
The file was modified/llvm/trunk/lib/Bitcode/Reader/MetadataLoader.cpptrunk/lib/Bitcode/Reader/MetadataLoader.cpp
The file was modified/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpptrunk/lib/Bitcode/Writer/BitcodeWriter.cpp
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpptrunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.htrunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
The file was modified/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfUnit.cpptrunk/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
The file was modified/llvm/trunk/lib/IR/AsmWriter.cpptrunk/lib/IR/AsmWriter.cpp
The file was modified/llvm/trunk/lib/IR/DIBuilder.cpptrunk/lib/IR/DIBuilder.cpp
The file was modified/llvm/trunk/lib/IR/DebugInfoMetadata.cpptrunk/lib/IR/DebugInfoMetadata.cpp
The file was modified/llvm/trunk/lib/IR/LLVMContextImpl.htrunk/lib/IR/LLVMContextImpl.h
The file was modified/llvm/trunk/lib/IR/Verifier.cpptrunk/lib/IR/Verifier.cpp
The file was added/llvm/trunk/test/Assembler/DICommonBlock.lltrunk/test/Assembler/DICommonBlock.ll
The file was added/llvm/trunk/test/DebugInfo/Generic/DICommonBlock.lltrunk/test/DebugInfo/Generic/DICommonBlock.ll
Revision 357932 by steven_wu:
Revert [ThinLTO] Fix ThinLTOCodegenerator to export llvm.used symbols

This reverts r357931 (git commit 8b70a5c11e08116955a875b9085433f14737bcaf)
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/LTO/LTO.htrunk/include/llvm/LTO/LTO.h
The file was modified/llvm/trunk/include/llvm/LTO/legacy/ThinLTOCodeGenerator.htrunk/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h
The file was modified/llvm/trunk/lib/LTO/LTO.cpptrunk/lib/LTO/LTO.cpp
The file was modified/llvm/trunk/lib/LTO/ThinLTOCodeGenerator.cpptrunk/lib/LTO/ThinLTOCodeGenerator.cpp
The file was removed/llvm/trunk/test/LTO/X86/Inputs/thinlto-internalize-used2.lltrunk/test/LTO/X86/Inputs/thinlto-internalize-used2.ll
The file was removed/llvm/trunk/test/LTO/X86/thinlto-internalize-used.lltrunk/test/LTO/X86/thinlto-internalize-used.ll
The file was modified/llvm/trunk/tools/llvm-lto/llvm-lto.cpptrunk/tools/llvm-lto/llvm-lto.cpp
Revision 357931 by steven_wu:
[ThinLTO] Fix ThinLTOCodegenerator to export llvm.used symbols

Summary:
ThinLTOCodeGenerator currently does not preserve llvm.used symbols and
it can internalize them. In order to pass the necessary information to the
legacy ThinLTOCodeGenerator, the input to the code generator is
rewritten to be based on lto::InputFile.

This fixes: PR41236
rdar://problem/49293439

Reviewers: tejohnson, pcc, dexonsmith

Reviewed By: tejohnson

Subscribers: mehdi_amini, inglorion, eraman, hiraditya, jkorous, dang, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60226
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/LTO/LTO.htrunk/include/llvm/LTO/LTO.h
The file was modified/llvm/trunk/include/llvm/LTO/legacy/ThinLTOCodeGenerator.htrunk/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h
The file was modified/llvm/trunk/lib/LTO/LTO.cpptrunk/lib/LTO/LTO.cpp
The file was modified/llvm/trunk/lib/LTO/ThinLTOCodeGenerator.cpptrunk/lib/LTO/ThinLTOCodeGenerator.cpp
The file was added/llvm/trunk/test/LTO/X86/Inputs/thinlto-internalize-used2.lltrunk/test/LTO/X86/Inputs/thinlto-internalize-used2.ll
The file was added/llvm/trunk/test/LTO/X86/thinlto-internalize-used.lltrunk/test/LTO/X86/thinlto-internalize-used.ll
The file was modified/llvm/trunk/tools/llvm-lto/llvm-lto.cpptrunk/tools/llvm-lto/llvm-lto.cpp
Revision 357930 by brzycki:
[JumpThreading] Fix incorrect fold conditional after indirectbr/callbr

Fixes bug 40992: https://bugs.llvm.org/show_bug.cgi?id=40992

There is potential for miscompiled code emitted from JumpThreading when
analyzing a block with one or more indirectbr or callbr predecessors. The
ProcessThreadableEdges() function incorrectly folds conditional branches
into an unconditional branch.

This patch prevents incorrect branch folding without fully pessimizing
other potential threading opportunities through the same basic block.

This IR shape was manually fed in via opt and is unclear if clang and the
full pass pipeline will ever emit similar code shapes.

Thanks to Matthias Liedtke for the bug report and simplified IR example.

Differential Revision: https://reviews.llvm.org/D60284
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpptrunk/lib/Transforms/Scalar/JumpThreading.cpp
The file was added/llvm/trunk/test/Transforms/JumpThreading/pr40992-indirectbr-folding.lltrunk/test/Transforms/JumpThreading/pr40992-indirectbr-folding.ll
Revision 357920 by maskray:
[llvm-objdump] Migrate relocation handling functions from error_code to Error
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-objdump/COFFDump.cpptrunk/tools/llvm-objdump/COFFDump.cpp
The file was modified/llvm/trunk/tools/llvm-objdump/ELFDump.cpptrunk/tools/llvm-objdump/ELFDump.cpp
The file was modified/llvm/trunk/tools/llvm-objdump/MachODump.cpptrunk/tools/llvm-objdump/MachODump.cpp
The file was modified/llvm/trunk/tools/llvm-objdump/WasmDump.cpptrunk/tools/llvm-objdump/WasmDump.cpp
The file was modified/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpptrunk/tools/llvm-objdump/llvm-objdump.cpp
The file was modified/llvm/trunk/tools/llvm-objdump/llvm-objdump.htrunk/tools/llvm-objdump/llvm-objdump.h
Revision 357919 by adibiagio:
[llvm-mca][scheduler-stats] Print issued micro opcodes per cycle. NFCI

It makes more sense to print out the number of micro opcodes that are issued
every cycle rather than the number of instructions issued per cycle.
This behavior is also consistent with the dispatch-stats: numbers from the two
views can now be easily compared.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/CommandGuide/llvm-mca.rsttrunk/docs/CommandGuide/llvm-mca.rst
The file was modified/llvm/trunk/test/tools/llvm-mca/AArch64/Exynos/scheduler-queue-usage.strunk/test/tools/llvm-mca/AArch64/Exynos/scheduler-queue-usage.s
The file was modified/llvm/trunk/test/tools/llvm-mca/X86/BdVer2/load-throughput.strunk/test/tools/llvm-mca/X86/BdVer2/load-throughput.s
The file was modified/llvm/trunk/test/tools/llvm-mca/X86/BdVer2/scheduler-queue-usage.strunk/test/tools/llvm-mca/X86/BdVer2/scheduler-queue-usage.s
The file was modified/llvm/trunk/test/tools/llvm-mca/X86/BdVer2/store-throughput.strunk/test/tools/llvm-mca/X86/BdVer2/store-throughput.s
The file was modified/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/scheduler-queue-usage.strunk/test/tools/llvm-mca/X86/BtVer2/scheduler-queue-usage.s
The file was modified/llvm/trunk/test/tools/llvm-mca/X86/option-all-stats-1.strunk/test/tools/llvm-mca/X86/option-all-stats-1.s
The file was modified/llvm/trunk/test/tools/llvm-mca/X86/option-all-stats-2.strunk/test/tools/llvm-mca/X86/option-all-stats-2.s
The file was modified/llvm/trunk/test/tools/llvm-mca/X86/option-all-views-1.strunk/test/tools/llvm-mca/X86/option-all-views-1.s
The file was modified/llvm/trunk/test/tools/llvm-mca/X86/option-all-views-2.strunk/test/tools/llvm-mca/X86/option-all-views-2.s
The file was modified/llvm/trunk/test/tools/llvm-mca/X86/scheduler-queue-usage.strunk/test/tools/llvm-mca/X86/scheduler-queue-usage.s
The file was modified/llvm/trunk/tools/llvm-mca/Views/SchedulerStatistics.cpptrunk/tools/llvm-mca/Views/SchedulerStatistics.cpp
The file was modified/llvm/trunk/tools/llvm-mca/Views/SchedulerStatistics.htrunk/tools/llvm-mca/Views/SchedulerStatistics.h
Revision 357914 by rksimon:
[X86][AVX] Add PR34380 shuffle test cases
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/avx512-shuffles/partial_permute.lltrunk/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
Revision 357912 by spatel:
[x86] make 8-bit shl undesirable

I was looking at a potential DAGCombiner fix for 1 of the regressions in D60278, and it caused severe regression test pain because x86 TLI lies about the desirability of 8-bit shift ops.

We've hinted at making all 8-bit ops undesirable for the reason in the code comment:

// TODO: Almost no 8-bit ops are desirable because they have no actual
//       size/speed advantages vs. 32-bit ops, but they do have a major
//       potential disadvantage by causing partial register stalls.

...but that leads to massive diffs and exposes all kinds of optimization holes itself.

Differential Revision: https://reviews.llvm.org/D60286
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/bt.lltrunk/test/CodeGen/X86/bt.ll
The file was modified/llvm/trunk/test/CodeGen/X86/btc_bts_btr.lltrunk/test/CodeGen/X86/btc_bts_btr.ll
The file was modified/llvm/trunk/test/CodeGen/X86/rotate4.lltrunk/test/CodeGen/X86/rotate4.ll
The file was modified/llvm/trunk/test/CodeGen/X86/scheduler-backtracking.lltrunk/test/CodeGen/X86/scheduler-backtracking.ll
The file was modified/llvm/trunk/test/CodeGen/X86/select_const.lltrunk/test/CodeGen/X86/select_const.ll
Revision 357911 by evgeny777:
Use llvm::crc32 instead of crc32. NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/DebugInfo/Symbolize/Symbolize.cpptrunk/lib/DebugInfo/Symbolize/Symbolize.cpp
Revision 357910 by spatel:
[InstCombine] remove overzealous assert for shuffles (PR41419)

As the TODO indicates, instsimplify could be improved.

Should fix:
https://bugs.llvm.org/show_bug.cgi?id=41419
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineVectorOps.cpptrunk/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/shuffle_select.lltrunk/test/Transforms/InstCombine/shuffle_select.ll
Revision 357909 by rksimon:
[InstCombine][X86] Expand MOVMSK to generic IR (PR39927)

First step towards removing the MOVMSK intrinsics completely - this patch expands MOVMSK to the pattern:

e.g. PMOVMSKB(v16i8 x):
%cmp = icmp slt <16 x i8> %x, zeroinitializer
%int = bitcast <16 x i8> %cmp to i16
%res = zext i16 %int to i32

Which is correctly handled by ISel and FastIsel (give or take an annoying movzx move....): https://godbolt.org/z/rkrSFW

Differential Revision: https://reviews.llvm.org/D60256
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpptrunk/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/X86/x86-movmsk.lltrunk/test/Transforms/InstCombine/X86/x86-movmsk.ll
Revision 357907 by nico:
gn build: Merge r357905
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/utils/gn/secondary/llvm/lib/Support/BUILD.gntrunk/utils/gn/secondary/llvm/lib/Support/BUILD.gn
The file was modified/llvm/trunk/utils/gn/secondary/llvm/unittests/Support/BUILD.gntrunk/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
Revision 357906 by nico:
gn-build: Re-run `git ls-files '*.gn' '*.gni' | xargs llvm/utils/gn/gn.py format`
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/utils/gn/secondary/compiler-rt/lib/hwasan/BUILD.gntrunk/utils/gn/secondary/compiler-rt/lib/hwasan/BUILD.gn
Revision 357905 by evgeny777:
Attempt to recommit r357901
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/include/llvm/Support/CRC.htrunk/include/llvm/Support/CRC.h
The file was modified/llvm/trunk/lib/DebugInfo/Symbolize/Symbolize.cpptrunk/lib/DebugInfo/Symbolize/Symbolize.cpp
The file was modified/llvm/trunk/lib/Support/CMakeLists.txttrunk/lib/Support/CMakeLists.txt
The file was added/llvm/trunk/lib/Support/CRC.cpptrunk/lib/Support/CRC.cpp
The file was modified/llvm/trunk/unittests/Support/CMakeLists.txttrunk/unittests/Support/CMakeLists.txt
The file was added/llvm/trunk/unittests/Support/CRCTest.cpptrunk/unittests/Support/CRCTest.cpp
Revision 357904 by shchenz:
[InstCombine] sdiv exact flag fixup.

Differential Revision: https://reviews.llvm.org/D60396
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineAddSub.cpptrunk/lib/Transforms/InstCombine/InstCombineAddSub.cpp
The file was modified/llvm/trunk/test/Transforms/InstCombine/div.lltrunk/test/Transforms/InstCombine/div.ll
Revision 357903 by Xing:
[llvm-readobj] Use `reinterpret_cast` instead of C-style casting. NFC.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-readobj/ELFDumper.cpptrunk/tools/llvm-readobj/ELFDumper.cpp
Revision 357902 by evgeny777:
Reverting r357901 as fails to build on some of the buildbots
Change TypePath in RepositoryPath in Workspace
The file was removed/llvm/trunk/include/llvm/Support/CRC.htrunk/include/llvm/Support/CRC.h
The file was modified/llvm/trunk/lib/DebugInfo/Symbolize/Symbolize.cpptrunk/lib/DebugInfo/Symbolize/Symbolize.cpp
The file was modified/llvm/trunk/lib/Support/CMakeLists.txttrunk/lib/Support/CMakeLists.txt
The file was removed/llvm/trunk/lib/Support/CRC.cpptrunk/lib/Support/CRC.cpp
The file was modified/llvm/trunk/unittests/Support/CMakeLists.txttrunk/unittests/Support/CMakeLists.txt
The file was removed/llvm/trunk/unittests/Support/CRCTest.cpptrunk/unittests/Support/CRCTest.cpp
Revision 357901 by evgeny777:
[Support] Add zlib independent CRC32

Differential revision: https://reviews.llvm.org/D59816
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/include/llvm/Support/CRC.htrunk/include/llvm/Support/CRC.h
The file was modified/llvm/trunk/lib/DebugInfo/Symbolize/Symbolize.cpptrunk/lib/DebugInfo/Symbolize/Symbolize.cpp
The file was modified/llvm/trunk/lib/Support/CMakeLists.txttrunk/lib/Support/CMakeLists.txt
The file was added/llvm/trunk/lib/Support/CRC.cpptrunk/lib/Support/CRC.cpp
The file was modified/llvm/trunk/unittests/Support/CMakeLists.txttrunk/unittests/Support/CMakeLists.txt
The file was added/llvm/trunk/unittests/Support/CRCTest.cpptrunk/unittests/Support/CRCTest.cpp
Revision 357900 by lebedevri:
[llvm-exegesis] benchmarkMain(): less cryptic error if built w/o libpfm

Wanted to check if inablility to measure latency of CMOV32rm
is a regression from D60041 / D60138, but unable to do that
because the llvm-exegesis-{8,9} from debian sid fails
with that cryptic, unhelpful error.

I suspect this will be a better error.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-exegesis/llvm-exegesis.cpptrunk/tools/llvm-exegesis/llvm-exegesis.cpp
Revision 357899 by Justin Bogner:
[CMake] Replace LLVM_ENABLE_CXX1Y and friends with LLVM_CXX_STD

Simplify building with particular C++ standards by replacing the
specific "enable standard X" flags with a flag that allows specifying
the standard you want directly.

We preserve compatibility with the existing flags so that anyone with
those flags in existing caches won't break mysteriously.

Differential Revision: https://reviews.llvm.org/D60399
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/CMakeLists.txttrunk/CMakeLists.txt
The file was modified/llvm/trunk/cmake/modules/HandleLLVMOptions.cmaketrunk/cmake/modules/HandleLLVMOptions.cmake
The file was modified/llvm/trunk/docs/CMake.rsttrunk/docs/CMake.rst
Revision 357898 by lebedevri:
[llvm-exegesis][X86] Randomize CMOVcc/SETcc OPERAND_COND_CODE CondCodes

Reviewers: courbet, gchatelet

Reviewed By: gchatelet

Subscribers: tschuett, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60066
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/tools/llvm-exegesis/X86/latency-CMOV32rr.strunk/test/tools/llvm-exegesis/X86/latency-CMOV32rr.s
The file was modified/llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.cpptrunk/tools/llvm-exegesis/lib/SnippetGenerator.cpp
The file was modified/llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.htrunk/tools/llvm-exegesis/lib/SnippetGenerator.h
The file was modified/llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpptrunk/tools/llvm-exegesis/lib/X86/Target.cpp
Revision 357897 by labath:
Object/Minidump: Add support for reading the ModuleList stream

Summary:
The ModuleList stream consists of an integer giving the number of
entries in the list, followed by the list itself. Each entry in the list
describes a module (dynamically loaded objects which were loaded in the
process when it crashed (or when the minidump was generated).

The code for reading the list is relatively straight-forward, with a
single gotcha. Some minidump writers are emitting padding after the
"count" field in order to align the subsequent list on 8 byte boundary
(this depends on how their ModuleList type was defined and the native
alignment of various types on their platform). Fortunately, the minidump
format contains enough redundancy (in the form of the stream length
field in the stream directory), which allows us to detect this situation
and correct it.

This patch just adds the ability to parse the stream. Code for
conversion to/from yaml will come in a follow-up patch.

Reviewers: zturner, amccarth, jhenderson, clayborg

Subscribers: jdoerfert, markmentovai, lldb-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60121
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/BinaryFormat/Minidump.htrunk/include/llvm/BinaryFormat/Minidump.h
The file was modified/llvm/trunk/include/llvm/Object/Minidump.htrunk/include/llvm/Object/Minidump.h
The file was modified/llvm/trunk/lib/Object/Minidump.cpptrunk/lib/Object/Minidump.cpp
The file was modified/llvm/trunk/unittests/Object/MinidumpTest.cpptrunk/unittests/Object/MinidumpTest.cpp
Revision 357894 by shchenz:
[InstCombine] add more testcases for sdiv exact flag fixup.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/div.lltrunk/test/Transforms/InstCombine/div.ll
Revision 357887 by ctopper:
[X86] Make LowerOperationWrapper more robust. Remove now unnecessary ReplaceAllUsesWith from LowerMSCATTER.

Previously LowerOperationWrapper took the number of results from the original
node and counted that many results from the new node. This was intended to drop
chain operands from FP_TO_SINT lowering that uses X87 with memory operations to
stack temporaries. The final load had an extra chain output that needs to be
ignored.

Unfortunately, it didn't work with scatter which has 2 result operands, the
mask output which is discarded and a chain output. The chain output is the one
that is needed but it comes second and it would be dropped by the previous
logic here. To workaround this we were doing a ReplaceAllUses in the lowering
code so that the generic legalization code wouldn't see any uses to replace
since it had been given the wrong result/type.

After this change we take the LowerOperation result directly if the original
node has one result. This allows us to directly return the chain from scatter
or the load data from the FP_TO_SINT case. When the original node has multiple
results we'll ensure the returned node has the same number and copy them over.
For cases where the original node has multiple results and the new code for some
reason has even more results, MERGE_VALUES can be used to pass only the needed
results.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
Revision 357886 by maskray:
[ConstantRange] Delete redundnt {z,s}extOrSelf for multiplication

These calls are redundant because the quotients have the same BitWidth
as MinValue/MaxValue.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/IR/ConstantRange.cpptrunk/lib/IR/ConstantRange.cpp
Revision 357884 by shchenz:
[InstCombine] add testcases for sdiv exact flag fixing - NFC.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/div.lltrunk/test/Transforms/InstCombine/div.ll
Revision 357883 by shchenz:
[InstCombine]add testcase for sdiv canonicalizetion - NFC
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/Transforms/InstCombine/sdiv-canonicalize.lltrunk/test/Transforms/InstCombine/sdiv-canonicalize.ll
Revision 357882 by ctopper:
[X86] Split floating point tests out of atomic-mi.ll into atomic-fp.ll. Add avx and avx512f command lines. NFC
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/CodeGen/X86/atomic-fp.lltrunk/test/CodeGen/X86/atomic-fp.ll
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-mi.lltrunk/test/CodeGen/X86/atomic-mi.ll
Revision 357881 by ctopper:
[X86] Add avx and avx512f command lines to atomic-non-integer.ll. NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/atomic-non-integer.lltrunk/test/CodeGen/X86/atomic-non-integer.ll
Revision 357880 by maskray:
[llvm-objdump] Fix MC/ARM/arm-macho-calls.s
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpptrunk/tools/llvm-objdump/llvm-objdump.cpp
Revision 357876 by nikic:
[ConstantRange] Add signed/unsigned unionWith()

This extends D59959 to unionWith(), allowing to specify that a
non-wrapping unsigned/signed range is preferred. This is somewhat
less useful than the intersect case, because union operations are
rarer. An example use would the the phi union computed in SCEV.

The implementation is mostly a straightforward use of getPreferredRange(),
but I also had to adjust some <=/< checks to make sure that no ranges with
lower==upper get constructed before they're passed to getPreferredRange(),
as these have additional constraints.

Differential Revision: https://reviews.llvm.org/D60377
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/ConstantRange.htrunk/include/llvm/IR/ConstantRange.h
The file was modified/llvm/trunk/lib/IR/ConstantRange.cpptrunk/lib/IR/ConstantRange.cpp
The file was modified/llvm/trunk/unittests/IR/ConstantRangeTest.cpptrunk/unittests/IR/ConstantRangeTest.cpp
Revision 357875 by ctopper:
[X86] Use (SUBREG_TO_REG (MOV32rm)) for extloadi64i8/extloadi64i16 when the load is 4 byte aligned or better and not volatile.

Summary:
Previously we would use MOVZXrm8/MOVZXrm16, but those are longer encodings.

This is similar to what we do in the loadi32 predicate.

Reviewers: RKSimon, spatel

Reviewed By: RKSimon

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60341
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86InstrCompiler.tdtrunk/lib/Target/X86/X86InstrCompiler.td
The file was modified/llvm/trunk/lib/Target/X86/X86InstrInfo.tdtrunk/lib/Target/X86/X86InstrInfo.td
The file was modified/llvm/trunk/test/CodeGen/X86/fp128-cast.lltrunk/test/CodeGen/X86/fp128-cast.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-sext-widen.lltrunk/test/CodeGen/X86/vector-sext-widen.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-sext.lltrunk/test/CodeGen/X86/vector-sext.ll
The file was modified/llvm/trunk/test/CodeGen/X86/zext-logicop-shift-load.lltrunk/test/CodeGen/X86/zext-logicop-shift-load.ll
Revision 357874 by nikic:
[ConstantRangeTest] Generalize intersection testing code; NFC

Extract the exhaustive intersection tests into a separate function,
so that it may be reused for unions as well.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/unittests/IR/ConstantRangeTest.cpptrunk/unittests/IR/ConstantRangeTest.cpp
Revision 357873 by nikic:
[ConstantRange] Add unsigned and signed intersection types

The intersection of two ConstantRanges may consist of two disjoint
ranges. As we can only return one range as the result, we need to
return one of the two possible ranges that cover both. Currently the
result is picked based on set size. However, this is not always
optimal: If we're in an unsigned context, we'd prefer to get a large
unsigned range over a small signed range -- the latter effectively
becomes a full set in the unsigned domain.

This revision adds a PreferredRangeType, which can be either Smallest,
Unsigned or Signed. Smallest is the current behavior and Unsigned and
Signed are new variants that prefer not to wrap the unsigned/signed
domain. The new type isn't used anywhere yet (but SCEV will be a good
first user, see D60035).

I've also added some comments to illustrate the various cases in
intersectWith(), which should hopefully make it more obvious what is
going on.

Differential Revision: https://reviews.llvm.org/D59959
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/ConstantRange.htrunk/include/llvm/IR/ConstantRange.h
The file was modified/llvm/trunk/lib/IR/ConstantRange.cpptrunk/lib/IR/ConstantRange.cpp
The file was modified/llvm/trunk/unittests/IR/ConstantRangeTest.cpptrunk/unittests/IR/ConstantRangeTest.cpp
Revision 357872 by codafi:
[LLVM-C] Allow Access to the Type of a Binary

Summary:  Add an accessor for the type of a binary file.

Reviewers: whitequark, deadalnix

Reviewed By: whitequark

Subscribers: hiraditya, aheejin, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60366
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm-c/Object.htrunk/include/llvm-c/Object.h
The file was modified/llvm/trunk/lib/Object/Object.cpptrunk/lib/Object/Object.cpp
Revision 357871 by nikic:
[ConstantRange] Add isAllNegative() and isAllNonNegative() methods

Add isAllNegative() and isAllNonNegative() methods to ConstantRange,
which determine whether all values in the constant range are
negative/non-negative.

This is useful for replacing KnownBits isNegative() and isNonNegative()
calls when changing code to use constant ranges.

Differential Revision: https://reviews.llvm.org/D60264
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/IR/ConstantRange.htrunk/include/llvm/IR/ConstantRange.h
The file was modified/llvm/trunk/lib/IR/ConstantRange.cpptrunk/lib/IR/ConstantRange.cpp
The file was modified/llvm/trunk/unittests/IR/ConstantRangeTest.cpptrunk/unittests/IR/ConstantRangeTest.cpp
Revision 357870 by nikic:
Reapply [ValueTracking] Support min/max selects in computeConstantRange()

Add support for min/max flavor selects in computeConstantRange(),
which allows us to fold comparisons of a min/max against a constant
in InstSimplify. This fixes an infinite InstCombine loop, with the
test case taken from D59378.

Relative to the previous iteration, this contains some adjustments for
AMDGPU med3 tests: The AMDGPU target runs InstSimplify prior to codegen,
which ends up constant folding some existing med3 tests after this
change. To preserve these tests a hidden -amdgpu-scalar-ir-passes option
is added, which allows disabling scalar IR passes (that use InstSimplify)
for testing purposes.

Differential Revision: https://reviews.llvm.org/D59506
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Analysis/ValueTracking.cpptrunk/lib/Analysis/ValueTracking.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpptrunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was added/llvm/trunk/test/CodeGen/AMDGPU/med3-no-simplify.lltrunk/test/CodeGen/AMDGPU/med3-no-simplify.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/smed3.lltrunk/test/CodeGen/AMDGPU/smed3.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/umed3.lltrunk/test/CodeGen/AMDGPU/umed3.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/minmax-fold.lltrunk/test/Transforms/InstCombine/minmax-fold.ll
The file was modified/llvm/trunk/test/Transforms/InstCombine/sub.lltrunk/test/Transforms/InstCombine/sub.ll
The file was modified/llvm/trunk/test/Transforms/InstSimplify/cmp_of_min_max.lltrunk/test/Transforms/InstSimplify/cmp_of_min_max.ll
Revision 357869 by maskray:
[llvm-objdump] Split disassembleObject and simplify --{start,stop}-address handling

The main disassembly loop is hard to read due to special handling of ARM
ELF data & ELF data. Split off the logic into two functions
dumpARMELFData and dumpELFData. Hoist some checks outside of the loop.

--start-address --stop-address have redundant checks and minor off-by-1
issues. Fix them.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpptrunk/tools/llvm-objdump/llvm-objdump.cpp
Revision 357868 by lattner:
last changes for now
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/index.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/index.rst
Revision 357867 by lattner:
various improvements in wording, also unbreak the bot
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/tutorial/LangImpl02.rsttrunk/docs/tutorial/LangImpl02.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl01.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl01.rst
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/index.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/index.rst
Revision 357866 by maskray:
[DWARF] DWARFDebugLine: delete unused parameter `Offset`
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/DebugInfo/DWARF/DWARFDebugLine.htrunk/include/llvm/DebugInfo/DWARF/DWARFDebugLine.h
The file was modified/llvm/trunk/lib/DebugInfo/DWARF/DWARFDebugLine.cpptrunk/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
Revision 357865 by lattner:
make a bunch of cleanups in wording and tone
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/index.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/index.rst
Revision 357864 by rksimon:
[CostModel][X86] Masked load legalization requires an binary-shuffle not a select (PR39812)

Expansion/truncation is better described by SK_PermuteTwoSrc than SK_Select
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpptrunk/lib/Target/X86/X86TargetTransformInfo.cpp
Revision 357863 by lattner:
remove some unhelpful language from the tutorial
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/tutorial/LangImpl10.rsttrunk/docs/tutorial/LangImpl10.rst
The file was added/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/index.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/index.rst
Revision 357862 by lattner:
Copy the C++ kaleidoscope tutorial into a subdirectory and clean up various things, aligning with the direction of the WiCT workshop, and Meike Baumgärtner's view of how this should work.  The old version of the documentation is unmodified, this is an experiment.
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/docs/tutorial/MyFirstLanguageFrontendtrunk/docs/tutorial/MyFirstLanguageFrontend
The file was added/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl01.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl01.rst
The file was added/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl02.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl02.rst
The file was added/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl03.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl03.rst
The file was added/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl04.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl04.rst
The file was added/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl05-cfg.pngtrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl05-cfg.png
The file was added/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl05.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl05.rst
The file was added/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl06.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl06.rst
The file was added/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl07.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl07.rst
The file was added/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rst
The file was added/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl09.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl09.rst
The file was added/llvm/trunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl10.rsttrunk/docs/tutorial/MyFirstLanguageFrontend/LangImpl10.rst
Revision 357861 by rksimon:
[DAG] Pull out ComputeNumSignBits call to make debugging easier. NFCI.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpptrunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Revision 357859 by rksimon:
[X86][SSE] SimplifyDemandedBitsForTargetNode - Add initial PACKSS support

In the case where we only want the sign bit (e.g. when using PACKSS truncation of comparison results for MOVMSK) then we can just demand the sign bit of the source operands.

This makes use of the fact that PACKSS saturates out of range values to the min/max int values - so the sign bit is always preserved.

Differential Revision: https://reviews.llvm.org/D60333
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-512.lltrunk/test/CodeGen/X86/bitcast-and-setcc-512.ll
The file was modified/llvm/trunk/test/CodeGen/X86/bitcast-setcc-128.lltrunk/test/CodeGen/X86/bitcast-setcc-128.ll
The file was modified/llvm/trunk/test/CodeGen/X86/bitcast-setcc-256.lltrunk/test/CodeGen/X86/bitcast-setcc-256.ll
The file was modified/llvm/trunk/test/CodeGen/X86/bitcast-setcc-512.lltrunk/test/CodeGen/X86/bitcast-setcc-512.ll
The file was modified/llvm/trunk/test/CodeGen/X86/movmsk-cmp.lltrunk/test/CodeGen/X86/movmsk-cmp.ll
Revision 357858 by maskray:
[llvm-objdump] Fix split of source lines; don't ltrim source lines

If the file does not end with a newline, it may be dropped. Fix the
splitting algorithm.

Also delete an unnecessary SourceCache lookup.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/tools/llvm-objdump/X86/source-interleave-x86_64.lltrunk/test/tools/llvm-objdump/X86/source-interleave-x86_64.ll
The file was modified/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpptrunk/tools/llvm-objdump/llvm-objdump.cpp
Revision 357857 by maskray:
[llvm-objdump] Simplify some ELF typename: ELFFile<ELFT>::Elf_xxx -> ELFT::xxx
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-objdump/ELFDump.cpptrunk/tools/llvm-objdump/ELFDump.cpp
Revision 357856 by maskray:
.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-objdump/ELFDump.cpptrunk/tools/llvm-objdump/ELFDump.cpp
Revision 357855 by maskray:
[llvm-objdump] Simplify Expected<T> handling with unwrapOrError
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/tools/llvm-objdump/ELFDump.cpptrunk/tools/llvm-objdump/ELFDump.cpp
The file was modified/llvm/trunk/tools/llvm-objdump/MachODump.cpptrunk/tools/llvm-objdump/MachODump.cpp
The file was modified/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpptrunk/tools/llvm-objdump/llvm-objdump.cpp
The file was modified/llvm/trunk/tools/llvm-objdump/llvm-objdump.htrunk/tools/llvm-objdump/llvm-objdump.h
Revision 357854 by mggm:
[ConstantRange] Shl considers full-set shifting to last bit position.

if we do SHL of two 16-bit ranges like [0, 30000) with [1,2) we get
"full-set" instead of what I would have expected [0, 60000) which is
still in the 16-bit unsigned range.

This patch changes the SHL algorithm to allow getting a usable range
even in this case.

Differential Revision: https://reviews.llvm.org/D57983
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/IR/ConstantRange.cpptrunk/lib/IR/ConstantRange.cpp
The file was modified/llvm/trunk/unittests/IR/ConstantRangeTest.cpptrunk/unittests/IR/ConstantRangeTest.cpp
Revision 357853 by maskray:
[llvm-objdump] Simplify disassembleObject

* Use std::binary_search to replace some std::lower_bound
* Use llvm::upper_bound to replace some std::upper_bound
* Use format_hex and support::endian::read{16,32}
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/tools/llvm-objdump/AArch64/elf-aarch64-mapping-symbols.testtrunk/test/tools/llvm-objdump/AArch64/elf-aarch64-mapping-symbols.test
The file was modified/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpptrunk/tools/llvm-objdump/llvm-objdump.cpp
Revision 357852 by maskray:
Change some StringRef::data() reinterpret_cast to bytes_begin() or arrayRefFromStringRef()
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/Bitcode/BitstreamReader.htrunk/include/llvm/Bitcode/BitstreamReader.h
The file was modified/llvm/trunk/include/llvm/Object/ELF.htrunk/include/llvm/Object/ELF.h
The file was modified/llvm/trunk/include/llvm/ObjectYAML/YAML.htrunk/include/llvm/ObjectYAML/YAML.h
The file was modified/llvm/trunk/lib/DebugInfo/DWARF/DWARFFormValue.cpptrunk/lib/DebugInfo/DWARF/DWARFFormValue.cpp
The file was modified/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpptrunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
The file was modified/llvm/trunk/lib/IR/Constants.cpptrunk/lib/IR/Constants.cpp
The file was modified/llvm/trunk/lib/Object/WasmObjectFile.cpptrunk/lib/Object/WasmObjectFile.cpp
The file was modified/llvm/trunk/lib/ProfileData/Coverage/CoverageMappingReader.cpptrunk/lib/ProfileData/Coverage/CoverageMappingReader.cpp
The file was modified/llvm/trunk/lib/ProfileData/InstrProf.cpptrunk/lib/ProfileData/InstrProf.cpp
The file was modified/llvm/trunk/tools/llvm-objdump/MachODump.cpptrunk/tools/llvm-objdump/MachODump.cpp
The file was modified/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpptrunk/tools/llvm-objdump/llvm-objdump.cpp
The file was modified/llvm/trunk/tools/llvm-readobj/COFFDumper.cpptrunk/tools/llvm-readobj/COFFDumper.cpp
The file was modified/llvm/trunk/tools/llvm-readobj/MachODumper.cpptrunk/tools/llvm-readobj/MachODumper.cpp
The file was modified/llvm/trunk/tools/sancov/sancov.cpptrunk/tools/sancov/sancov.cpp
The file was modified/llvm/trunk/unittests/MC/DwarfLineTables.cpptrunk/unittests/MC/DwarfLineTables.cpp
Revision 357850 by phosek:
[gn] Support for per-target runtime directory layout

This change also introduces the clang_enable_per_target_runtime_dir
to enable the use of per-target runtime directory layout which is the
equivalent of LLVM_ENABLE_PER_TARGET_RUNTIME_DIR CMake option.

Differential Revision: https://reviews.llvm.org/D60332
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/utils/gn/secondary/clang/runtimes.gnitrunk/utils/gn/secondary/clang/runtimes.gni
The file was modified/llvm/trunk/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gntrunk/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
The file was modified/llvm/trunk/utils/gn/secondary/compiler-rt/lib/hwasan/BUILD.gntrunk/utils/gn/secondary/compiler-rt/lib/hwasan/BUILD.gn
The file was modified/llvm/trunk/utils/gn/secondary/compiler-rt/target.gnitrunk/utils/gn/secondary/compiler-rt/target.gni
The file was modified/llvm/trunk/utils/gn/secondary/compiler-rt/test/hwasan/BUILD.gntrunk/utils/gn/secondary/compiler-rt/test/hwasan/BUILD.gn
Revision 357849 by nicholas:
[NFC] Fix typo in comment.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/ADT/BreadthFirstIterator.htrunk/include/llvm/ADT/BreadthFirstIterator.h
Revision 357848 by ctopper:
[X86] When converting (x << C1) AND C2 to (x AND (C2>>C1)) << C1 during isel, try using andl over andq by favoring 32-bit unsigned immediates.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpptrunk/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/narrow-shl-cst.lltrunk/test/CodeGen/X86/narrow-shl-cst.ll
Revision 357847 by rksimon:
[X86] combineBitcastvxi1 - provide dst VT and src SDValue directly. NFCI.

Prep work to make it easier to reuse the BITCAST->MOVSMK combine in other cases.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
Revision 357846 by ctopper:
[X86] Use a signed mask in foldMaskedShiftToScaledMask to enable a shorter immediate encoding.

This function reorders AND and SHL to enable the SHL to fold into an LEA. The
upper bits of the AND will be shifted out by the SHL so it doesn't matter what
mask value we use for these bits. By using sign bits from the original mask in
these upper bits we might enable a shorter immediate encoding to be used.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpptrunk/lib/Target/X86/X86ISelDAGToDAG.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/fold-and-shift-x86_64.lltrunk/test/CodeGen/X86/fold-and-shift-x86_64.ll
The file was modified/llvm/trunk/test/CodeGen/X86/fold-and-shift.lltrunk/test/CodeGen/X86/fold-and-shift.ll
Revision 357845 by ctopper:
[X86] Add test cases to show missed opportunities to use a sign extended 8 or 32 bit immediate AND when reversing SHL+AND to form an LEA.

When we shift the AND mask over we should shift in sign bits instead of zero bits. The scale in the LEA will shift these bits out so it doesn't matter whether we mask the bits off or not. Using sign bits will potentially allow a sign extended immediate to be used.

Also add some other test cases for cases that are currently optimal.
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/CodeGen/X86/fold-and-shift-x86_64.lltrunk/test/CodeGen/X86/fold-and-shift-x86_64.ll
The file was modified/llvm/trunk/test/CodeGen/X86/fold-and-shift.lltrunk/test/CodeGen/X86/fold-and-shift.ll
Revision 357844 by ctopper:
[X86] Autogenerate complete checks. NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/fold-and-shift.lltrunk/test/CodeGen/X86/fold-and-shift.ll
Revision 357843 by rksimon:
Fix spelling mistake. NFCI.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
Revision 357842 by rksimon:
[X86] Add AVX-target expandload and compressstore tests
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/masked_compressstore.lltrunk/test/CodeGen/X86/masked_compressstore.ll
The file was modified/llvm/trunk/test/CodeGen/X86/masked_expandload.lltrunk/test/CodeGen/X86/masked_expandload.ll
Revision 357841 by lebedevri:
[llvm-exegesis][X86] Handle CMOVcc/SETcc OPERAND_COND_CODE OperandType

Summary:
D60041 / D60138 refactoring changed how CMOV/SETcc opcodes
are handled. concode is now an immediate, with it's own operand type.

This at least allows to not crash on the opcode.
However, this still won't generate all the snippets
with all the condcode enumerators. D60066 does that.

Reviewers: courbet, gchatelet

Reviewed By: gchatelet

Subscribers: tschuett, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60057
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/tools/llvm-exegesis/X86/latency-CMOV32rr.strunk/test/tools/llvm-exegesis/X86/latency-CMOV32rr.s
The file was modified/llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.cpptrunk/tools/llvm-exegesis/lib/SnippetGenerator.cpp
The file was modified/llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.htrunk/tools/llvm-exegesis/lib/SnippetGenerator.h
The file was modified/llvm/trunk/tools/llvm-exegesis/lib/Target.cpptrunk/tools/llvm-exegesis/lib/Target.cpp
The file was modified/llvm/trunk/tools/llvm-exegesis/lib/Target.htrunk/tools/llvm-exegesis/lib/Target.h
The file was modified/llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpptrunk/tools/llvm-exegesis/lib/X86/Target.cpp
Revision 357840 by rksimon:
[X86] Split expandload and compressstore tests
Change TypePath in RepositoryPath in Workspace
The file was removed/llvm/trunk/test/CodeGen/X86/compress_expand.lltrunk/test/CodeGen/X86/compress_expand.ll
The file was added/llvm/trunk/test/CodeGen/X86/masked_compressstore.lltrunk/test/CodeGen/X86/masked_compressstore.ll
The file was added/llvm/trunk/test/CodeGen/X86/masked_expandload.lltrunk/test/CodeGen/X86/masked_expandload.ll
Revision 357839 by rksimon:
[X86][SSE] Add more exhaustive masked load/store tests

Reordered/renamed some existing tests to match the cleaned up order
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/X86/masked_load.lltrunk/test/CodeGen/X86/masked_load.ll
The file was modified/llvm/trunk/test/CodeGen/X86/masked_store.lltrunk/test/CodeGen/X86/masked_store.ll
Revision 357838 by rksimon:
[CostModel][X86] Add more exhaustive masked load/store/gather/scatter/expand/compress cost tests
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Analysis/CostModel/X86/masked-intrinsic-cost-widen.lltrunk/test/Analysis/CostModel/X86/masked-intrinsic-cost-widen.ll
The file was modified/llvm/trunk/test/Analysis/CostModel/X86/masked-intrinsic-cost.lltrunk/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
Revision 357835 by rampitec:
[AMDGPU] Sort out and rename multiple CI/VI predicates

Differential Revision: https://reviews.llvm.org/D60346
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPU.tdtrunk/lib/Target/AMDGPU/AMDGPU.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/BUFInstructions.tdtrunk/lib/Target/AMDGPU/BUFInstructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/DSInstructions.tdtrunk/lib/Target/AMDGPU/DSInstructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpptrunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/FLATInstructions.tdtrunk/lib/Target/AMDGPU/FLATInstructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.tdtrunk/lib/Target/AMDGPU/MIMGInstructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.tdtrunk/lib/Target/AMDGPU/SIInstrInfo.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/SMInstructions.tdtrunk/lib/Target/AMDGPU/SMInstructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/SOPInstructions.tdtrunk/lib/Target/AMDGPU/SOPInstructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.tdtrunk/lib/Target/AMDGPU/VOP1Instructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.tdtrunk/lib/Target/AMDGPU/VOP2Instructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.tdtrunk/lib/Target/AMDGPU/VOP3Instructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOP3PInstructions.tdtrunk/lib/Target/AMDGPU/VOP3PInstructions.td
The file was modified/llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.tdtrunk/lib/Target/AMDGPU/VOPCInstructions.td
Revision 357834 by maskray:
[DWARF] Simplify DWARFDebugAranges::findAddress

The current lower_bound approach has to check two iterators pos and pos-1.
Changing it to upper_bound allows us to check one iterator (similar to
DWARFUnitVector::getUnitFor*).
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/DebugInfo/DWARF/DWARFDebugAranges.htrunk/include/llvm/DebugInfo/DWARF/DWARFDebugAranges.h
The file was modified/llvm/trunk/lib/DebugInfo/DWARF/DWARFDebugAranges.cpptrunk/lib/DebugInfo/DWARF/DWARFDebugAranges.cpp
Revision 357833 by maskray:
[Symbolize] Uniquify sorted vector<pair<SymbolDesc, StringRef>>
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/DebugInfo/Symbolize/SymbolizableObjectFile.cpptrunk/lib/DebugInfo/Symbolize/SymbolizableObjectFile.cpp
The file was modified/llvm/trunk/lib/DebugInfo/Symbolize/SymbolizableObjectFile.htrunk/lib/DebugInfo/Symbolize/SymbolizableObjectFile.h
Revision 357830 by nico:
gn build: Pacify `gn format`
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gntrunk/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
Revision 357826 by zturner:
[PDB Docs] Add documentation for the hash table format.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/PDB/HashTable.rsttrunk/docs/PDB/HashTable.rst
Revision 357825 by zturner:
[PDB Docs] The IPI Stream actually has index 4.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/PDB/TpiStream.rsttrunk/docs/PDB/TpiStream.rst
Revision 357822 by codafi:
[LLVM-C] Begin to Expose A More General Binary Interface

Summary:
Provides a new type, `LLVMBinaryRef`, and a binding to `llvm::object::createBinary` for more general interoperation with binary files than `LLVMObjectFileRef`.  It also provides the proper non-consuming API for input buffers and populates an out parameter for error handling if necessary - two things the previous API did not do.

In a follow-up, I'll define section and symbol iterators and begin to build upon the existing test infrastructure.

This patch is a first step towards deprecating that API and replacing it with something more robust.

Reviewers: deadalnix, whitequark

Reviewed By: whitequark

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60322
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm-c/Object.htrunk/include/llvm-c/Object.h
The file was modified/llvm/trunk/include/llvm-c/Types.htrunk/include/llvm-c/Types.h
The file was modified/llvm/trunk/include/llvm/Object/Binary.htrunk/include/llvm/Object/Binary.h
The file was modified/llvm/trunk/lib/Object/Object.cpptrunk/lib/Object/Object.cpp
Revision 357821 by phosek:
[gn] Support for building compiler-rt builtins

This is support for building compiler-rt builtins, The library build
should be complete for a subset of supported platforms, but not all
CMake options have been replicated in GN.

We always use the just built compiler to build all the runtimes, which
is equivalent to the CMake runtimes build. This simplifies the build
configuration because we don't need to support arbitrary host compiler
and can always assume the latest Clang. With GN's toolchain support,
this is significantly more efficient than the CMake runtimes build.

Differential Revision: https://reviews.llvm.org/D60331
Change TypePath in RepositoryPath in Workspace
The file was modified/compiler-rt/trunk/lib/builtins/CMakeLists.txtN/A
The file was modified/llvm/trunk/utils/gn/build/sync_source_lists_from_cmake.pytrunk/utils/gn/build/sync_source_lists_from_cmake.py
The file was modified/llvm/trunk/utils/gn/secondary/BUILD.gntrunk/utils/gn/secondary/BUILD.gn
The file was added/llvm/trunk/utils/gn/secondary/compiler-rt/BUILD.gntrunk/utils/gn/secondary/compiler-rt/BUILD.gn
The file was added/llvm/trunk/utils/gn/secondary/compiler-rt/lib/BUILD.gntrunk/utils/gn/secondary/compiler-rt/lib/BUILD.gn
The file was added/llvm/trunk/utils/gn/secondary/compiler-rt/lib/builtinstrunk/utils/gn/secondary/compiler-rt/lib/builtins
The file was added/llvm/trunk/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gntrunk/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
Revision 357820 by dsanders:
[globalisel] Allow combiners to query legality
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerInfo.htrunk/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
Revision 357819 by zturner:
[PDB Docs] Delete * LINKER * Stream information.

This is actually just a module debug info stream, so it should
technically be covered by a discussion of the module list.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/docs/PDB/index.rsttrunk/docs/PDB/index.rst
Revision 357816 by spatel:
[InstCombine] add more tests for fmul+fdiv+sqrt; NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/Transforms/InstCombine/fmul-sqrt.lltrunk/test/Transforms/InstCombine/fmul-sqrt.ll
Revision 357815 by dsanders:
[globalisel] Support 3-type legalForCartesianProduct()
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerInfo.htrunk/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
Revision 357812 by codafi:
[LLVM-C] Add bindings to insert basic blocks

Summary:
Now that we can create standalone basic blocks, it's useful to be able to append them.  Add bindings to

- Insert a basic block after the current insertion block
- Append a basic block to the end of a function's list of basic blocks

Reviewers: whitequark, deadalnix, harlanhaskins

Reviewed By: whitequark, harlanhaskins

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59658
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm-c/Core.htrunk/include/llvm-c/Core.h
The file was modified/llvm/trunk/lib/IR/Core.cpptrunk/lib/IR/Core.cpp
Revision 357809 by thegameg:
[X86] Enable tail calls for CallingConv::Swift

It's currently only enabled on AArch64 (enabled in r281376).
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/swiftcc.lltrunk/test/CodeGen/X86/swiftcc.ll
Revision 357808 by thegameg:
[X86] Preserve operand flag when expanding TCRETURNri

The expansion of TCRETURNri(64) would not keep operand flags like
undef/renamable/etc. which can result in machine verifier issues.

Also add plumbing to be able to use `-run-pass=x86-pseudo`.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86.htrunk/lib/Target/X86/X86.h
The file was modified/llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpptrunk/lib/Target/X86/X86ExpandPseudo.cpp
The file was modified/llvm/trunk/lib/Target/X86/X86TargetMachine.cpptrunk/lib/Target/X86/X86TargetMachine.cpp
The file was added/llvm/trunk/test/CodeGen/X86/tailcall-pseudo-64.mirtrunk/test/CodeGen/X86/tailcall-pseudo-64.mir
The file was added/llvm/trunk/test/CodeGen/X86/tailcall-pseudo.mirtrunk/test/CodeGen/X86/tailcall-pseudo.mir
Revision 357805 by rampitec:
[AMDGPU] Add MachineDCE pass after RenameIndependentSubregs

Detect dead lanes can create some dead defs. Then RenameIndependentSubregs
will break a REG_SEQUENCE which may use these dead defs. At this point
a dead instruction can be removed but we do not run a DCE anymore.

MachineDCE was only running before live variable analysis. The patch
adds a mean to preserve LiveIntervals and SlotIndexes in case it works
past this.

Differential Revision: https://reviews.llvm.org/D59626
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpptrunk/lib/CodeGen/DeadMachineInstructionElim.cpp
The file was modified/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpptrunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was added/llvm/trunk/test/CodeGen/AMDGPU/dead-lane.mirtrunk/test/CodeGen/AMDGPU/dead-lane.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/salu-to-valu.lltrunk/test/CodeGen/AMDGPU/salu-to-valu.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/sdwa-peephole.lltrunk/test/CodeGen/AMDGPU/sdwa-peephole.ll
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/shrink-carry.mirtrunk/test/CodeGen/AMDGPU/shrink-carry.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mirtrunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
The file was modified/llvm/trunk/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.lltrunk/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
Revision 357802 by ctopper:
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.

Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.

Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.

Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon

Reviewed By: RKSimon

Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60228
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