FailedChanges

Summary

  1. [X86][SSE] Add SSE vector shift support to SimplifyDemandedVectorEltsForTargetNode vector splitting
  2. Wrap to 80 columns, no behavior change
  3. [X86][SSE] Split 512-bit -> 128-bit vector directly in SimplifyDemandedVectorEltsForTargetNode
Revision 359680 by rksimon:
[X86][SSE] Add SSE vector shift support to SimplifyDemandedVectorEltsForTargetNode vector splitting
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/combine-udiv.lltrunk/test/CodeGen/X86/combine-udiv.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-fshl-256.lltrunk/test/CodeGen/X86/vector-fshl-256.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-fshl-512.lltrunk/test/CodeGen/X86/vector-fshl-512.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-fshl-rot-256.lltrunk/test/CodeGen/X86/vector-fshl-rot-256.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-fshl-rot-512.lltrunk/test/CodeGen/X86/vector-fshl-rot-512.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-fshr-256.lltrunk/test/CodeGen/X86/vector-fshr-256.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-fshr-512.lltrunk/test/CodeGen/X86/vector-fshr-512.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-fshr-rot-256.lltrunk/test/CodeGen/X86/vector-fshr-rot-256.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-fshr-rot-512.lltrunk/test/CodeGen/X86/vector-fshr-rot-512.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-mul-widen.lltrunk/test/CodeGen/X86/vector-reduce-mul-widen.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-mul.lltrunk/test/CodeGen/X86/vector-reduce-mul.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-rotate-256.lltrunk/test/CodeGen/X86/vector-rotate-256.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-rotate-512.lltrunk/test/CodeGen/X86/vector-rotate-512.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shift-ashr-256.lltrunk/test/CodeGen/X86/vector-shift-ashr-256.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shift-ashr-512.lltrunk/test/CodeGen/X86/vector-shift-ashr-512.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shift-lshr-256.lltrunk/test/CodeGen/X86/vector-shift-lshr-256.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shift-lshr-512.lltrunk/test/CodeGen/X86/vector-shift-lshr-512.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shift-shl-256.lltrunk/test/CodeGen/X86/vector-shift-shl-256.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-shift-shl-512.lltrunk/test/CodeGen/X86/vector-shift-shl-512.ll
Revision 359679 by nico:
Wrap to 80 columns, no behavior change
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Option/OptTable.cpptrunk/lib/Option/OptTable.cpp
Revision 359678 by rksimon:
[X86][SSE] Split 512-bit -> 128-bit vector directly in SimplifyDemandedVectorEltsForTargetNode
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpptrunk/lib/Target/X86/X86ISelLowering.cpp
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-mul-widen.lltrunk/test/CodeGen/X86/vector-reduce-mul-widen.ll
The file was modified/llvm/trunk/test/CodeGen/X86/vector-reduce-mul.lltrunk/test/CodeGen/X86/vector-reduce-mul.ll